2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
15 * Copyright IBM Corp. 2007
17 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
20 #include <linux/types.h>
21 #include <linux/string.h>
22 #include <linux/kvm.h>
23 #include <linux/kvm_host.h>
24 #include <linux/highmem.h>
25 #include <asm/mmu-44x.h>
26 #include <asm/kvm_ppc.h>
30 #define PPC44x_TLB_USER_PERM_MASK (PPC44x_TLB_UX|PPC44x_TLB_UR|PPC44x_TLB_UW)
31 #define PPC44x_TLB_SUPER_PERM_MASK (PPC44x_TLB_SX|PPC44x_TLB_SR|PPC44x_TLB_SW)
33 static unsigned int kvmppc_tlb_44x_pos;
36 void kvmppc_dump_tlbs(struct kvm_vcpu *vcpu)
38 struct kvmppc_44x_tlbe *tlbe;
41 printk("vcpu %d TLB dump:\n", vcpu->vcpu_id);
42 printk("| %2s | %3s | %8s | %8s | %8s |\n",
43 "nr", "tid", "word0", "word1", "word2");
45 for (i = 0; i < PPC44x_TLB_SIZE; i++) {
46 tlbe = &vcpu->arch.guest_tlb[i];
47 if (tlbe->word0 & PPC44x_TLB_VALID)
48 printk(" G%2d | %02X | %08X | %08X | %08X |\n",
49 i, tlbe->tid, tlbe->word0, tlbe->word1,
53 for (i = 0; i < PPC44x_TLB_SIZE; i++) {
54 tlbe = &vcpu->arch.shadow_tlb[i];
55 if (tlbe->word0 & PPC44x_TLB_VALID)
56 printk(" S%2d | %02X | %08X | %08X | %08X |\n",
57 i, tlbe->tid, tlbe->word0, tlbe->word1,
63 static u32 kvmppc_44x_tlb_shadow_attrib(u32 attrib, int usermode)
65 /* Mask off reserved bits. */
66 attrib &= PPC44x_TLB_PERM_MASK|PPC44x_TLB_ATTR_MASK;
69 /* Guest is in supervisor mode, so we need to translate guest
70 * supervisor permissions into user permissions. */
71 attrib &= ~PPC44x_TLB_USER_PERM_MASK;
72 attrib |= (attrib & PPC44x_TLB_SUPER_PERM_MASK) << 3;
75 /* Make sure host can always access this memory. */
76 attrib |= PPC44x_TLB_SX|PPC44x_TLB_SR|PPC44x_TLB_SW;
81 /* Search the guest TLB for a matching entry. */
82 int kvmppc_44x_tlb_index(struct kvm_vcpu *vcpu, gva_t eaddr, unsigned int pid,
87 /* XXX Replace loop with fancy data structures. */
88 for (i = 0; i < PPC44x_TLB_SIZE; i++) {
89 struct kvmppc_44x_tlbe *tlbe = &vcpu->arch.guest_tlb[i];
92 if (eaddr < get_tlb_eaddr(tlbe))
95 if (eaddr > get_tlb_end(tlbe))
98 tid = get_tlb_tid(tlbe);
99 if (tid && (tid != pid))
102 if (!get_tlb_v(tlbe))
105 if (get_tlb_ts(tlbe) != as)
114 struct kvmppc_44x_tlbe *kvmppc_44x_itlb_search(struct kvm_vcpu *vcpu,
117 unsigned int as = !!(vcpu->arch.msr & MSR_IS);
120 index = kvmppc_44x_tlb_index(vcpu, eaddr, vcpu->arch.pid, as);
123 return &vcpu->arch.guest_tlb[index];
126 struct kvmppc_44x_tlbe *kvmppc_44x_dtlb_search(struct kvm_vcpu *vcpu,
129 unsigned int as = !!(vcpu->arch.msr & MSR_DS);
132 index = kvmppc_44x_tlb_index(vcpu, eaddr, vcpu->arch.pid, as);
135 return &vcpu->arch.guest_tlb[index];
138 static int kvmppc_44x_tlbe_is_writable(struct kvmppc_44x_tlbe *tlbe)
140 return tlbe->word2 & (PPC44x_TLB_SW|PPC44x_TLB_UW);
143 static void kvmppc_44x_shadow_release(struct kvm_vcpu *vcpu,
146 struct kvmppc_44x_tlbe *stlbe = &vcpu->arch.shadow_tlb[index];
147 struct page *page = vcpu->arch.shadow_pages[index];
149 if (get_tlb_v(stlbe)) {
150 if (kvmppc_44x_tlbe_is_writable(stlbe))
151 kvm_release_page_dirty(page);
153 kvm_release_page_clean(page);
157 void kvmppc_core_destroy_mmu(struct kvm_vcpu *vcpu)
161 for (i = 0; i <= tlb_44x_hwater; i++)
162 kvmppc_44x_shadow_release(vcpu, i);
165 void kvmppc_tlbe_set_modified(struct kvm_vcpu *vcpu, unsigned int i)
167 vcpu->arch.shadow_tlb_mod[i] = 1;
170 /* Caller must ensure that the specified guest TLB entry is safe to insert into
172 void kvmppc_mmu_map(struct kvm_vcpu *vcpu, u64 gvaddr, gfn_t gfn, u64 asid,
175 struct page *new_page;
176 struct kvmppc_44x_tlbe *stlbe;
180 /* Future optimization: don't overwrite the TLB entry containing the
181 * current PC (or stack?). */
182 victim = kvmppc_tlb_44x_pos++;
183 if (kvmppc_tlb_44x_pos > tlb_44x_hwater)
184 kvmppc_tlb_44x_pos = 0;
185 stlbe = &vcpu->arch.shadow_tlb[victim];
187 /* Get reference to new page. */
188 new_page = gfn_to_page(vcpu->kvm, gfn);
189 if (is_error_page(new_page)) {
190 printk(KERN_ERR "Couldn't get guest page for gfn %lx!\n", gfn);
191 kvm_release_page_clean(new_page);
194 hpaddr = page_to_phys(new_page);
196 /* Drop reference to old page. */
197 kvmppc_44x_shadow_release(vcpu, victim);
199 vcpu->arch.shadow_pages[victim] = new_page;
201 /* XXX Make sure (va, size) doesn't overlap any other
202 * entries. 440x6 user manual says the result would be
205 /* XXX what about AS? */
207 stlbe->tid = !(asid & 0xff);
209 /* Force TS=1 for all guest mappings. */
210 /* For now we hardcode 4KB mappings, but it will be important to
211 * use host large pages in the future. */
212 stlbe->word0 = (gvaddr & PAGE_MASK) | PPC44x_TLB_VALID | PPC44x_TLB_TS
214 stlbe->word1 = (hpaddr & 0xfffffc00) | ((hpaddr >> 32) & 0xf);
215 stlbe->word2 = kvmppc_44x_tlb_shadow_attrib(flags,
216 vcpu->arch.msr & MSR_PR);
217 kvmppc_tlbe_set_modified(vcpu, victim);
219 KVMTRACE_5D(STLB_WRITE, vcpu, victim,
220 stlbe->tid, stlbe->word0, stlbe->word1, stlbe->word2,
224 static void kvmppc_mmu_invalidate(struct kvm_vcpu *vcpu, gva_t eaddr,
225 gva_t eend, u32 asid)
227 unsigned int pid = !(asid & 0xff);
230 /* XXX Replace loop with fancy data structures. */
231 for (i = 0; i <= tlb_44x_hwater; i++) {
232 struct kvmppc_44x_tlbe *stlbe = &vcpu->arch.shadow_tlb[i];
235 if (!get_tlb_v(stlbe))
238 if (eend < get_tlb_eaddr(stlbe))
241 if (eaddr > get_tlb_end(stlbe))
244 tid = get_tlb_tid(stlbe);
245 if (tid && (tid != pid))
248 kvmppc_44x_shadow_release(vcpu, i);
250 kvmppc_tlbe_set_modified(vcpu, i);
251 KVMTRACE_5D(STLB_INVAL, vcpu, i,
252 stlbe->tid, stlbe->word0, stlbe->word1,
253 stlbe->word2, handler);
257 /* Invalidate all mappings on the privilege switch after PID has been changed.
258 * The guest always runs with PID=1, so we must clear the entire TLB when
259 * switching address spaces. */
260 void kvmppc_mmu_priv_switch(struct kvm_vcpu *vcpu, int usermode)
264 if (vcpu->arch.swap_pid) {
265 /* XXX Replace loop with fancy data structures. */
266 for (i = 0; i <= tlb_44x_hwater; i++) {
267 struct kvmppc_44x_tlbe *stlbe = &vcpu->arch.shadow_tlb[i];
269 /* Future optimization: clear only userspace mappings. */
270 kvmppc_44x_shadow_release(vcpu, i);
272 kvmppc_tlbe_set_modified(vcpu, i);
273 KVMTRACE_5D(STLB_INVAL, vcpu, i,
274 stlbe->tid, stlbe->word0, stlbe->word1,
275 stlbe->word2, handler);
277 vcpu->arch.swap_pid = 0;
280 vcpu->arch.shadow_pid = !usermode;
283 static int tlbe_is_host_safe(const struct kvm_vcpu *vcpu,
284 const struct kvmppc_44x_tlbe *tlbe)
288 if (!get_tlb_v(tlbe))
291 /* Does it match current guest AS? */
292 /* XXX what about IS != DS? */
293 if (get_tlb_ts(tlbe) != !!(vcpu->arch.msr & MSR_IS))
296 gpa = get_tlb_raddr(tlbe);
297 if (!gfn_to_memslot(vcpu->kvm, gpa >> PAGE_SHIFT))
298 /* Mapping is not for RAM. */
304 int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
310 struct kvmppc_44x_tlbe *tlbe;
313 index = vcpu->arch.gpr[ra];
314 if (index > PPC44x_TLB_SIZE) {
315 printk("%s: index %d\n", __func__, index);
316 kvmppc_dump_vcpu(vcpu);
320 tlbe = &vcpu->arch.guest_tlb[index];
322 /* Invalidate shadow mappings for the about-to-be-clobbered TLBE. */
323 if (tlbe->word0 & PPC44x_TLB_VALID) {
324 eaddr = get_tlb_eaddr(tlbe);
325 asid = (tlbe->word0 & PPC44x_TLB_TS) | tlbe->tid;
326 kvmppc_mmu_invalidate(vcpu, eaddr, get_tlb_end(tlbe), asid);
330 case PPC44x_TLB_PAGEID:
331 tlbe->tid = vcpu->arch.mmucr & 0xff;
332 tlbe->word0 = vcpu->arch.gpr[rs];
335 case PPC44x_TLB_XLAT:
336 tlbe->word1 = vcpu->arch.gpr[rs];
339 case PPC44x_TLB_ATTRIB:
340 tlbe->word2 = vcpu->arch.gpr[rs];
347 if (tlbe_is_host_safe(vcpu, tlbe)) {
348 eaddr = get_tlb_eaddr(tlbe);
349 raddr = get_tlb_raddr(tlbe);
350 asid = (tlbe->word0 & PPC44x_TLB_TS) | tlbe->tid;
351 flags = tlbe->word2 & 0xffff;
353 /* Create a 4KB mapping on the host. If the guest wanted a
354 * large page, only the first 4KB is mapped here and the rest
355 * are mapped on the fly. */
356 kvmppc_mmu_map(vcpu, eaddr, raddr >> PAGE_SHIFT, asid, flags);
359 KVMTRACE_5D(GTLB_WRITE, vcpu, index,
360 tlbe->tid, tlbe->word0, tlbe->word1, tlbe->word2,
366 int kvmppc_44x_emul_tlbsx(struct kvm_vcpu *vcpu, u8 rt, u8 ra, u8 rb, u8 rc)
370 unsigned int as = get_mmucr_sts(vcpu);
371 unsigned int pid = get_mmucr_stid(vcpu);
373 ea = vcpu->arch.gpr[rb];
375 ea += vcpu->arch.gpr[ra];
377 index = kvmppc_44x_tlb_index(vcpu, ea, pid, as);
380 vcpu->arch.cr &= ~0x20000000;
382 vcpu->arch.cr |= 0x20000000;
384 vcpu->arch.gpr[rt] = index;