2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
15 * Copyright IBM Corp. 2007
17 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
20 #include <linux/types.h>
21 #include <linux/string.h>
22 #include <linux/kvm.h>
23 #include <linux/kvm_host.h>
24 #include <linux/highmem.h>
25 #include <asm/mmu-44x.h>
26 #include <asm/kvm_ppc.h>
30 #define PPC44x_TLB_USER_PERM_MASK (PPC44x_TLB_UX|PPC44x_TLB_UR|PPC44x_TLB_UW)
31 #define PPC44x_TLB_SUPER_PERM_MASK (PPC44x_TLB_SX|PPC44x_TLB_SR|PPC44x_TLB_SW)
33 static unsigned int kvmppc_tlb_44x_pos;
36 void kvmppc_dump_tlbs(struct kvm_vcpu *vcpu)
38 struct kvmppc_44x_tlbe *tlbe;
41 printk("vcpu %d TLB dump:\n", vcpu->vcpu_id);
42 printk("| %2s | %3s | %8s | %8s | %8s |\n",
43 "nr", "tid", "word0", "word1", "word2");
45 for (i = 0; i < PPC44x_TLB_SIZE; i++) {
46 tlbe = &vcpu->arch.guest_tlb[i];
47 if (tlbe->word0 & PPC44x_TLB_VALID)
48 printk(" G%2d | %02X | %08X | %08X | %08X |\n",
49 i, tlbe->tid, tlbe->word0, tlbe->word1,
53 for (i = 0; i < PPC44x_TLB_SIZE; i++) {
54 tlbe = &vcpu->arch.shadow_tlb[i];
55 if (tlbe->word0 & PPC44x_TLB_VALID)
56 printk(" S%2d | %02X | %08X | %08X | %08X |\n",
57 i, tlbe->tid, tlbe->word0, tlbe->word1,
63 static u32 kvmppc_44x_tlb_shadow_attrib(u32 attrib, int usermode)
65 /* Mask off reserved bits. */
66 attrib &= PPC44x_TLB_PERM_MASK|PPC44x_TLB_ATTR_MASK;
69 /* Guest is in supervisor mode, so we need to translate guest
70 * supervisor permissions into user permissions. */
71 attrib &= ~PPC44x_TLB_USER_PERM_MASK;
72 attrib |= (attrib & PPC44x_TLB_SUPER_PERM_MASK) << 3;
75 /* Make sure host can always access this memory. */
76 attrib |= PPC44x_TLB_SX|PPC44x_TLB_SR|PPC44x_TLB_SW;
81 /* Search the guest TLB for a matching entry. */
82 int kvmppc_44x_tlb_index(struct kvm_vcpu *vcpu, gva_t eaddr, unsigned int pid,
87 /* XXX Replace loop with fancy data structures. */
88 for (i = 0; i < PPC44x_TLB_SIZE; i++) {
89 struct tlbe *tlbe = &vcpu->arch.guest_tlb[i];
92 if (eaddr < get_tlb_eaddr(tlbe))
95 if (eaddr > get_tlb_end(tlbe))
98 tid = get_tlb_tid(tlbe);
99 if (tid && (tid != pid))
102 if (!get_tlb_v(tlbe))
105 if (get_tlb_ts(tlbe) != as)
114 struct tlbe *kvmppc_44x_itlb_search(struct kvm_vcpu *vcpu, gva_t eaddr)
116 unsigned int as = !!(vcpu->arch.msr & MSR_IS);
119 index = kvmppc_44x_tlb_index(vcpu, eaddr, vcpu->arch.pid, as);
122 return &vcpu->arch.guest_tlb[index];
125 struct tlbe *kvmppc_44x_dtlb_search(struct kvm_vcpu *vcpu, gva_t eaddr)
127 unsigned int as = !!(vcpu->arch.msr & MSR_DS);
130 index = kvmppc_44x_tlb_index(vcpu, eaddr, vcpu->arch.pid, as);
133 return &vcpu->arch.guest_tlb[index];
136 static int kvmppc_44x_tlbe_is_writable(struct tlbe *tlbe)
138 return tlbe->word2 & (PPC44x_TLB_SW|PPC44x_TLB_UW);
141 static void kvmppc_44x_shadow_release(struct kvm_vcpu *vcpu,
144 struct tlbe *stlbe = &vcpu->arch.shadow_tlb[index];
145 struct page *page = vcpu->arch.shadow_pages[index];
147 if (get_tlb_v(stlbe)) {
148 if (kvmppc_44x_tlbe_is_writable(stlbe))
149 kvm_release_page_dirty(page);
151 kvm_release_page_clean(page);
155 void kvmppc_core_destroy_mmu(struct kvm_vcpu *vcpu)
159 for (i = 0; i <= tlb_44x_hwater; i++)
160 kvmppc_44x_shadow_release(vcpu, i);
163 void kvmppc_tlbe_set_modified(struct kvm_vcpu *vcpu, unsigned int i)
165 vcpu->arch.shadow_tlb_mod[i] = 1;
168 /* Caller must ensure that the specified guest TLB entry is safe to insert into
170 void kvmppc_mmu_map(struct kvm_vcpu *vcpu, u64 gvaddr, gfn_t gfn, u64 asid,
173 struct page *new_page;
178 /* Future optimization: don't overwrite the TLB entry containing the
179 * current PC (or stack?). */
180 victim = kvmppc_tlb_44x_pos++;
181 if (kvmppc_tlb_44x_pos > tlb_44x_hwater)
182 kvmppc_tlb_44x_pos = 0;
183 stlbe = &vcpu->arch.shadow_tlb[victim];
185 /* Get reference to new page. */
186 new_page = gfn_to_page(vcpu->kvm, gfn);
187 if (is_error_page(new_page)) {
188 printk(KERN_ERR "Couldn't get guest page for gfn %lx!\n", gfn);
189 kvm_release_page_clean(new_page);
192 hpaddr = page_to_phys(new_page);
194 /* Drop reference to old page. */
195 kvmppc_44x_shadow_release(vcpu, victim);
197 vcpu->arch.shadow_pages[victim] = new_page;
199 /* XXX Make sure (va, size) doesn't overlap any other
200 * entries. 440x6 user manual says the result would be
203 /* XXX what about AS? */
205 stlbe->tid = !(asid & 0xff);
207 /* Force TS=1 for all guest mappings. */
208 /* For now we hardcode 4KB mappings, but it will be important to
209 * use host large pages in the future. */
210 stlbe->word0 = (gvaddr & PAGE_MASK) | PPC44x_TLB_VALID | PPC44x_TLB_TS
212 stlbe->word1 = (hpaddr & 0xfffffc00) | ((hpaddr >> 32) & 0xf);
213 stlbe->word2 = kvmppc_44x_tlb_shadow_attrib(flags,
214 vcpu->arch.msr & MSR_PR);
215 kvmppc_tlbe_set_modified(vcpu, victim);
217 KVMTRACE_5D(STLB_WRITE, vcpu, victim,
218 stlbe->tid, stlbe->word0, stlbe->word1, stlbe->word2,
222 static void kvmppc_mmu_invalidate(struct kvm_vcpu *vcpu, gva_t eaddr,
223 gva_t eend, u32 asid)
225 unsigned int pid = !(asid & 0xff);
228 /* XXX Replace loop with fancy data structures. */
229 for (i = 0; i <= tlb_44x_hwater; i++) {
230 struct tlbe *stlbe = &vcpu->arch.shadow_tlb[i];
233 if (!get_tlb_v(stlbe))
236 if (eend < get_tlb_eaddr(stlbe))
239 if (eaddr > get_tlb_end(stlbe))
242 tid = get_tlb_tid(stlbe);
243 if (tid && (tid != pid))
246 kvmppc_44x_shadow_release(vcpu, i);
248 kvmppc_tlbe_set_modified(vcpu, i);
249 KVMTRACE_5D(STLB_INVAL, vcpu, i,
250 stlbe->tid, stlbe->word0, stlbe->word1,
251 stlbe->word2, handler);
255 /* Invalidate all mappings on the privilege switch after PID has been changed.
256 * The guest always runs with PID=1, so we must clear the entire TLB when
257 * switching address spaces. */
258 void kvmppc_mmu_priv_switch(struct kvm_vcpu *vcpu, int usermode)
262 if (vcpu->arch.swap_pid) {
263 /* XXX Replace loop with fancy data structures. */
264 for (i = 0; i <= tlb_44x_hwater; i++) {
265 struct tlbe *stlbe = &vcpu->arch.shadow_tlb[i];
267 /* Future optimization: clear only userspace mappings. */
268 kvmppc_44x_shadow_release(vcpu, i);
270 kvmppc_tlbe_set_modified(vcpu, i);
271 KVMTRACE_5D(STLB_INVAL, vcpu, i,
272 stlbe->tid, stlbe->word0, stlbe->word1,
273 stlbe->word2, handler);
275 vcpu->arch.swap_pid = 0;
278 vcpu->arch.shadow_pid = !usermode;
281 static int tlbe_is_host_safe(const struct kvm_vcpu *vcpu,
282 const struct tlbe *tlbe)
286 if (!get_tlb_v(tlbe))
289 /* Does it match current guest AS? */
290 /* XXX what about IS != DS? */
291 if (get_tlb_ts(tlbe) != !!(vcpu->arch.msr & MSR_IS))
294 gpa = get_tlb_raddr(tlbe);
295 if (!gfn_to_memslot(vcpu->kvm, gpa >> PAGE_SHIFT))
296 /* Mapping is not for RAM. */
302 int kvmppc_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
311 index = vcpu->arch.gpr[ra];
312 if (index > PPC44x_TLB_SIZE) {
313 printk("%s: index %d\n", __func__, index);
314 kvmppc_dump_vcpu(vcpu);
318 tlbe = &vcpu->arch.guest_tlb[index];
320 /* Invalidate shadow mappings for the about-to-be-clobbered TLBE. */
321 if (tlbe->word0 & PPC44x_TLB_VALID) {
322 eaddr = get_tlb_eaddr(tlbe);
323 asid = (tlbe->word0 & PPC44x_TLB_TS) | tlbe->tid;
324 kvmppc_mmu_invalidate(vcpu, eaddr, get_tlb_end(tlbe), asid);
328 case PPC44x_TLB_PAGEID:
329 tlbe->tid = vcpu->arch.mmucr & 0xff;
330 tlbe->word0 = vcpu->arch.gpr[rs];
333 case PPC44x_TLB_XLAT:
334 tlbe->word1 = vcpu->arch.gpr[rs];
337 case PPC44x_TLB_ATTRIB:
338 tlbe->word2 = vcpu->arch.gpr[rs];
345 if (tlbe_is_host_safe(vcpu, tlbe)) {
346 eaddr = get_tlb_eaddr(tlbe);
347 raddr = get_tlb_raddr(tlbe);
348 asid = (tlbe->word0 & PPC44x_TLB_TS) | tlbe->tid;
349 flags = tlbe->word2 & 0xffff;
351 /* Create a 4KB mapping on the host. If the guest wanted a
352 * large page, only the first 4KB is mapped here and the rest
353 * are mapped on the fly. */
354 kvmppc_mmu_map(vcpu, eaddr, raddr >> PAGE_SHIFT, asid, flags);
357 KVMTRACE_5D(GTLB_WRITE, vcpu, index,
358 tlbe->tid, tlbe->word0, tlbe->word1, tlbe->word2,
364 int kvmppc_emul_tlbsx(struct kvm_vcpu *vcpu, u8 rt, u8 ra, u8 rb, u8 rc)
368 unsigned int as = get_mmucr_sts(vcpu);
369 unsigned int pid = get_mmucr_stid(vcpu);
371 ea = vcpu->arch.gpr[rb];
373 ea += vcpu->arch.gpr[ra];
375 index = kvmppc_44x_tlb_index(vcpu, ea, pid, as);
378 vcpu->arch.cr &= ~0x20000000;
380 vcpu->arch.cr |= 0x20000000;
382 vcpu->arch.gpr[rt] = index;