2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/kvm_ppc.h>
21 #include <asm/disassemble.h>
22 #include <asm/kvm_book3s.h>
24 #include <asm/switch_to.h>
27 #define OP_19_XOP_RFID 18
28 #define OP_19_XOP_RFI 50
30 #define OP_31_XOP_MFMSR 83
31 #define OP_31_XOP_MTMSR 146
32 #define OP_31_XOP_MTMSRD 178
33 #define OP_31_XOP_MTSR 210
34 #define OP_31_XOP_MTSRIN 242
35 #define OP_31_XOP_TLBIEL 274
36 #define OP_31_XOP_TLBIE 306
37 #define OP_31_XOP_SLBMTE 402
38 #define OP_31_XOP_SLBIE 434
39 #define OP_31_XOP_SLBIA 498
40 #define OP_31_XOP_MFSR 595
41 #define OP_31_XOP_MFSRIN 659
42 #define OP_31_XOP_DCBA 758
43 #define OP_31_XOP_SLBMFEV 851
44 #define OP_31_XOP_EIOIO 854
45 #define OP_31_XOP_SLBMFEE 915
47 /* DCBZ is actually 1014, but we patch it to 1010 so we get a trap */
48 #define OP_31_XOP_DCBZ 1010
64 /* Book3S_32 defines mfsrin(v) - but that messes up our abstract
65 * function pointers, so let's just disable the define. */
74 static bool spr_allowed(struct kvm_vcpu *vcpu, enum priv_level level)
76 /* PAPR VMs only access supervisor SPRs */
77 if (vcpu->arch.papr_enabled && (level > PRIV_SUPER))
80 /* Limit user space to its own small SPR set */
81 if ((vcpu->arch.shared->msr & MSR_PR) && level > PRIV_PROBLEM)
87 int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
88 unsigned int inst, int *advance)
90 int emulated = EMULATE_DONE;
91 int rt = get_rt(inst);
92 int rs = get_rs(inst);
93 int ra = get_ra(inst);
94 int rb = get_rb(inst);
96 switch (get_op(inst)) {
98 switch (get_xop(inst)) {
101 kvmppc_set_pc(vcpu, vcpu->arch.shared->srr0);
102 kvmppc_set_msr(vcpu, vcpu->arch.shared->srr1);
107 emulated = EMULATE_FAIL;
112 switch (get_xop(inst)) {
113 case OP_31_XOP_MFMSR:
114 kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->msr);
116 case OP_31_XOP_MTMSRD:
118 ulong rs_val = kvmppc_get_gpr(vcpu, rs);
119 if (inst & 0x10000) {
120 ulong new_msr = vcpu->arch.shared->msr;
121 new_msr &= ~(MSR_RI | MSR_EE);
122 new_msr |= rs_val & (MSR_RI | MSR_EE);
123 vcpu->arch.shared->msr = new_msr;
125 kvmppc_set_msr(vcpu, rs_val);
128 case OP_31_XOP_MTMSR:
129 kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, rs));
135 srnum = kvmppc_get_field(inst, 12 + 32, 15 + 32);
136 if (vcpu->arch.mmu.mfsrin) {
138 sr = vcpu->arch.mmu.mfsrin(vcpu, srnum);
139 kvmppc_set_gpr(vcpu, rt, sr);
143 case OP_31_XOP_MFSRIN:
147 srnum = (kvmppc_get_gpr(vcpu, rb) >> 28) & 0xf;
148 if (vcpu->arch.mmu.mfsrin) {
150 sr = vcpu->arch.mmu.mfsrin(vcpu, srnum);
151 kvmppc_set_gpr(vcpu, rt, sr);
156 vcpu->arch.mmu.mtsrin(vcpu,
158 kvmppc_get_gpr(vcpu, rs));
160 case OP_31_XOP_MTSRIN:
161 vcpu->arch.mmu.mtsrin(vcpu,
162 (kvmppc_get_gpr(vcpu, rb) >> 28) & 0xf,
163 kvmppc_get_gpr(vcpu, rs));
165 case OP_31_XOP_TLBIE:
166 case OP_31_XOP_TLBIEL:
168 bool large = (inst & 0x00200000) ? true : false;
169 ulong addr = kvmppc_get_gpr(vcpu, rb);
170 vcpu->arch.mmu.tlbie(vcpu, addr, large);
173 case OP_31_XOP_EIOIO:
175 case OP_31_XOP_SLBMTE:
176 if (!vcpu->arch.mmu.slbmte)
179 vcpu->arch.mmu.slbmte(vcpu,
180 kvmppc_get_gpr(vcpu, rs),
181 kvmppc_get_gpr(vcpu, rb));
183 case OP_31_XOP_SLBIE:
184 if (!vcpu->arch.mmu.slbie)
187 vcpu->arch.mmu.slbie(vcpu,
188 kvmppc_get_gpr(vcpu, rb));
190 case OP_31_XOP_SLBIA:
191 if (!vcpu->arch.mmu.slbia)
194 vcpu->arch.mmu.slbia(vcpu);
196 case OP_31_XOP_SLBMFEE:
197 if (!vcpu->arch.mmu.slbmfee) {
198 emulated = EMULATE_FAIL;
202 rb_val = kvmppc_get_gpr(vcpu, rb);
203 t = vcpu->arch.mmu.slbmfee(vcpu, rb_val);
204 kvmppc_set_gpr(vcpu, rt, t);
207 case OP_31_XOP_SLBMFEV:
208 if (!vcpu->arch.mmu.slbmfev) {
209 emulated = EMULATE_FAIL;
213 rb_val = kvmppc_get_gpr(vcpu, rb);
214 t = vcpu->arch.mmu.slbmfev(vcpu, rb_val);
215 kvmppc_set_gpr(vcpu, rt, t);
219 /* Gets treated as NOP */
223 ulong rb_val = kvmppc_get_gpr(vcpu, rb);
226 u32 zeros[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
231 ra_val = kvmppc_get_gpr(vcpu, ra);
233 addr = (ra_val + rb_val) & ~31ULL;
234 if (!(vcpu->arch.shared->msr & MSR_SF))
238 r = kvmppc_st(vcpu, &addr, 32, zeros, true);
239 if ((r == -ENOENT) || (r == -EPERM)) {
240 struct kvmppc_book3s_shadow_vcpu *svcpu;
242 svcpu = svcpu_get(vcpu);
244 vcpu->arch.shared->dar = vaddr;
245 svcpu->fault_dar = vaddr;
247 dsisr = DSISR_ISSTORE;
249 dsisr |= DSISR_NOHPTE;
250 else if (r == -EPERM)
251 dsisr |= DSISR_PROTFAULT;
253 vcpu->arch.shared->dsisr = dsisr;
254 svcpu->fault_dsisr = dsisr;
257 kvmppc_book3s_queue_irqprio(vcpu,
258 BOOK3S_INTERRUPT_DATA_STORAGE);
264 emulated = EMULATE_FAIL;
268 emulated = EMULATE_FAIL;
271 if (emulated == EMULATE_FAIL)
272 emulated = kvmppc_emulate_paired_single(run, vcpu);
277 void kvmppc_set_bat(struct kvm_vcpu *vcpu, struct kvmppc_bat *bat, bool upper,
282 u32 bl = (val >> 2) & 0x7ff;
283 bat->bepi_mask = (~bl << 17);
284 bat->bepi = val & 0xfffe0000;
285 bat->vs = (val & 2) ? 1 : 0;
286 bat->vp = (val & 1) ? 1 : 0;
287 bat->raw = (bat->raw & 0xffffffff00000000ULL) | val;
290 bat->brpn = val & 0xfffe0000;
291 bat->wimg = (val >> 3) & 0xf;
293 bat->raw = (bat->raw & 0x00000000ffffffffULL) | ((u64)val << 32);
297 static struct kvmppc_bat *kvmppc_find_bat(struct kvm_vcpu *vcpu, int sprn)
299 struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu);
300 struct kvmppc_bat *bat;
303 case SPRN_IBAT0U ... SPRN_IBAT3L:
304 bat = &vcpu_book3s->ibat[(sprn - SPRN_IBAT0U) / 2];
306 case SPRN_IBAT4U ... SPRN_IBAT7L:
307 bat = &vcpu_book3s->ibat[4 + ((sprn - SPRN_IBAT4U) / 2)];
309 case SPRN_DBAT0U ... SPRN_DBAT3L:
310 bat = &vcpu_book3s->dbat[(sprn - SPRN_DBAT0U) / 2];
312 case SPRN_DBAT4U ... SPRN_DBAT7L:
313 bat = &vcpu_book3s->dbat[4 + ((sprn - SPRN_DBAT4U) / 2)];
322 int kvmppc_core_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
324 int emulated = EMULATE_DONE;
328 if (!spr_allowed(vcpu, PRIV_HYPER))
330 to_book3s(vcpu)->sdr1 = spr_val;
333 vcpu->arch.shared->dsisr = spr_val;
336 vcpu->arch.shared->dar = spr_val;
339 to_book3s(vcpu)->hior = spr_val;
341 case SPRN_IBAT0U ... SPRN_IBAT3L:
342 case SPRN_IBAT4U ... SPRN_IBAT7L:
343 case SPRN_DBAT0U ... SPRN_DBAT3L:
344 case SPRN_DBAT4U ... SPRN_DBAT7L:
346 struct kvmppc_bat *bat = kvmppc_find_bat(vcpu, sprn);
348 kvmppc_set_bat(vcpu, bat, !(sprn % 2), (u32)spr_val);
349 /* BAT writes happen so rarely that we're ok to flush
351 kvmppc_mmu_pte_flush(vcpu, 0, 0);
352 kvmppc_mmu_flush_segments(vcpu);
356 to_book3s(vcpu)->hid[0] = spr_val;
359 to_book3s(vcpu)->hid[1] = spr_val;
362 to_book3s(vcpu)->hid[2] = spr_val;
364 case SPRN_HID2_GEKKO:
365 to_book3s(vcpu)->hid[2] = spr_val;
366 /* HID2.PSE controls paired single on gekko */
367 switch (vcpu->arch.pvr) {
368 case 0x00080200: /* lonestar 2.0 */
369 case 0x00088202: /* lonestar 2.2 */
370 case 0x70000100: /* gekko 1.0 */
371 case 0x00080100: /* gekko 2.0 */
372 case 0x00083203: /* gekko 2.3a */
373 case 0x00083213: /* gekko 2.3b */
374 case 0x00083204: /* gekko 2.4 */
375 case 0x00083214: /* gekko 2.4e (8SE) - retail HW2 */
376 case 0x00087200: /* broadway */
377 if (vcpu->arch.hflags & BOOK3S_HFLAG_NATIVE_PS) {
378 /* Native paired singles */
379 } else if (spr_val & (1 << 29)) { /* HID2.PSE */
380 vcpu->arch.hflags |= BOOK3S_HFLAG_PAIRED_SINGLE;
381 kvmppc_giveup_ext(vcpu, MSR_FP);
383 vcpu->arch.hflags &= ~BOOK3S_HFLAG_PAIRED_SINGLE;
389 case SPRN_HID4_GEKKO:
390 to_book3s(vcpu)->hid[4] = spr_val;
393 to_book3s(vcpu)->hid[5] = spr_val;
394 /* guest HID5 set can change is_dcbz32 */
395 if (vcpu->arch.mmu.is_dcbz32(vcpu) &&
397 vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32;
400 to_book3s(vcpu)->purr_offset = spr_val - get_tb();
403 to_book3s(vcpu)->spurr_offset = spr_val - get_tb();
413 to_book3s(vcpu)->gqr[sprn - SPRN_GQR0] = spr_val;
423 case SPRN_MMCR0_GEKKO:
424 case SPRN_MMCR1_GEKKO:
425 case SPRN_PMC1_GEKKO:
426 case SPRN_PMC2_GEKKO:
427 case SPRN_PMC3_GEKKO:
428 case SPRN_PMC4_GEKKO:
429 case SPRN_WPAR_GEKKO:
433 printk(KERN_INFO "KVM: invalid SPR write: %d\n", sprn);
435 emulated = EMULATE_FAIL;
443 int kvmppc_core_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val)
445 int emulated = EMULATE_DONE;
448 case SPRN_IBAT0U ... SPRN_IBAT3L:
449 case SPRN_IBAT4U ... SPRN_IBAT7L:
450 case SPRN_DBAT0U ... SPRN_DBAT3L:
451 case SPRN_DBAT4U ... SPRN_DBAT7L:
453 struct kvmppc_bat *bat = kvmppc_find_bat(vcpu, sprn);
456 *spr_val = bat->raw >> 32;
463 if (!spr_allowed(vcpu, PRIV_HYPER))
465 *spr_val = to_book3s(vcpu)->sdr1;
468 *spr_val = vcpu->arch.shared->dsisr;
471 *spr_val = vcpu->arch.shared->dar;
474 *spr_val = to_book3s(vcpu)->hior;
477 *spr_val = to_book3s(vcpu)->hid[0];
480 *spr_val = to_book3s(vcpu)->hid[1];
483 case SPRN_HID2_GEKKO:
484 *spr_val = to_book3s(vcpu)->hid[2];
487 case SPRN_HID4_GEKKO:
488 *spr_val = to_book3s(vcpu)->hid[4];
491 *spr_val = to_book3s(vcpu)->hid[5];
498 *spr_val = get_tb() + to_book3s(vcpu)->purr_offset;
501 *spr_val = get_tb() + to_book3s(vcpu)->purr_offset;
511 *spr_val = to_book3s(vcpu)->gqr[sprn - SPRN_GQR0];
519 case SPRN_MMCR0_GEKKO:
520 case SPRN_MMCR1_GEKKO:
521 case SPRN_PMC1_GEKKO:
522 case SPRN_PMC2_GEKKO:
523 case SPRN_PMC3_GEKKO:
524 case SPRN_PMC4_GEKKO:
525 case SPRN_WPAR_GEKKO:
530 printk(KERN_INFO "KVM: invalid SPR read: %d\n", sprn);
532 emulated = EMULATE_FAIL;
540 u32 kvmppc_alignment_dsisr(struct kvm_vcpu *vcpu, unsigned int inst)
545 * This is what the spec says about DSISR bits (not mentioned = 0):
547 * 12:13 [DS] Set to bits 30:31
548 * 15:16 [X] Set to bits 29:30
549 * 17 [X] Set to bit 25
550 * [D/DS] Set to bit 5
551 * 18:21 [X] Set to bits 21:24
552 * [D/DS] Set to bits 1:4
553 * 22:26 Set to bits 6:10 (RT/RS/FRT/FRS)
554 * 27:31 Set to bits 11:15 (RA)
557 switch (get_op(inst)) {
563 dsisr |= (inst >> 12) & 0x4000; /* bit 17 */
564 dsisr |= (inst >> 17) & 0x3c00; /* bits 18:21 */
568 dsisr |= (inst << 14) & 0x18000; /* bits 15:16 */
569 dsisr |= (inst << 8) & 0x04000; /* bit 17 */
570 dsisr |= (inst << 3) & 0x03c00; /* bits 18:21 */
573 printk(KERN_INFO "KVM: Unaligned instruction 0x%x\n", inst);
577 dsisr |= (inst >> 16) & 0x03ff; /* bits 22:31 */
582 ulong kvmppc_alignment_dar(struct kvm_vcpu *vcpu, unsigned int inst)
585 ulong ra = get_ra(inst);
586 ulong rb = get_rb(inst);
588 switch (get_op(inst)) {
594 dar = kvmppc_get_gpr(vcpu, ra);
595 dar += (s32)((s16)inst);
599 dar = kvmppc_get_gpr(vcpu, ra);
600 dar += kvmppc_get_gpr(vcpu, rb);
603 printk(KERN_INFO "KVM: Unaligned instruction 0x%x\n", inst);