2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * Copyright 2010-2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
9 #include <linux/types.h>
10 #include <linux/string.h>
11 #include <linux/kvm.h>
12 #include <linux/kvm_host.h>
13 #include <linux/hugetlb.h>
14 #include <linux/module.h>
16 #include <asm/tlbflush.h>
17 #include <asm/kvm_ppc.h>
18 #include <asm/kvm_book3s.h>
19 #include <asm/mmu-hash64.h>
20 #include <asm/hvcall.h>
21 #include <asm/synch.h>
22 #include <asm/ppc-opcode.h>
24 /* Translate address of a vmalloc'd thing to a linear map address */
25 static void *real_vmalloc_addr(void *x)
27 unsigned long addr = (unsigned long) x;
30 p = find_linux_pte_or_hugepte(swapper_pg_dir, addr, NULL);
31 if (!p || !pte_present(*p))
33 /* assume we don't have huge pages in vmalloc space... */
34 addr = (pte_pfn(*p) << PAGE_SHIFT) | (addr & ~PAGE_MASK);
38 /* Return 1 if we need to do a global tlbie, 0 if we can use tlbiel */
39 static int global_invalidates(struct kvm *kvm, unsigned long flags)
44 * If there is only one vcore, and it's currently running,
45 * we can use tlbiel as long as we mark all other physical
46 * cores as potentially having stale TLB entries for this lpid.
47 * If we're not using MMU notifiers, we never take pages away
48 * from the guest, so we can use tlbiel if requested.
49 * Otherwise, don't use tlbiel.
51 if (kvm->arch.online_vcores == 1 && local_paca->kvm_hstate.kvm_vcore)
53 else if (kvm->arch.using_mmu_notifiers)
56 global = !(flags & H_LOCAL);
59 /* any other core might now have stale TLB entries... */
61 cpumask_setall(&kvm->arch.need_tlb_flush);
62 cpumask_clear_cpu(local_paca->kvm_hstate.kvm_vcore->pcpu,
63 &kvm->arch.need_tlb_flush);
70 * Add this HPTE into the chain for the real page.
71 * Must be called with the chain locked; it unlocks the chain.
73 void kvmppc_add_revmap_chain(struct kvm *kvm, struct revmap_entry *rev,
74 unsigned long *rmap, long pte_index, int realmode)
76 struct revmap_entry *head, *tail;
79 if (*rmap & KVMPPC_RMAP_PRESENT) {
80 i = *rmap & KVMPPC_RMAP_INDEX;
81 head = &kvm->arch.revmap[i];
83 head = real_vmalloc_addr(head);
84 tail = &kvm->arch.revmap[head->back];
86 tail = real_vmalloc_addr(tail);
88 rev->back = head->back;
89 tail->forw = pte_index;
90 head->back = pte_index;
92 rev->forw = rev->back = pte_index;
93 *rmap = (*rmap & ~KVMPPC_RMAP_INDEX) |
94 pte_index | KVMPPC_RMAP_PRESENT;
98 EXPORT_SYMBOL_GPL(kvmppc_add_revmap_chain);
100 /* Remove this HPTE from the chain for a real page */
101 static void remove_revmap_chain(struct kvm *kvm, long pte_index,
102 struct revmap_entry *rev,
103 unsigned long hpte_v, unsigned long hpte_r)
105 struct revmap_entry *next, *prev;
106 unsigned long gfn, ptel, head;
107 struct kvm_memory_slot *memslot;
109 unsigned long rcbits;
111 rcbits = hpte_r & (HPTE_R_R | HPTE_R_C);
112 ptel = rev->guest_rpte |= rcbits;
113 gfn = hpte_rpn(ptel, hpte_page_size(hpte_v, ptel));
114 memslot = __gfn_to_memslot(kvm_memslots(kvm), gfn);
118 rmap = real_vmalloc_addr(&memslot->arch.rmap[gfn - memslot->base_gfn]);
121 head = *rmap & KVMPPC_RMAP_INDEX;
122 next = real_vmalloc_addr(&kvm->arch.revmap[rev->forw]);
123 prev = real_vmalloc_addr(&kvm->arch.revmap[rev->back]);
124 next->back = rev->back;
125 prev->forw = rev->forw;
126 if (head == pte_index) {
128 if (head == pte_index)
129 *rmap &= ~(KVMPPC_RMAP_PRESENT | KVMPPC_RMAP_INDEX);
131 *rmap = (*rmap & ~KVMPPC_RMAP_INDEX) | head;
133 *rmap |= rcbits << KVMPPC_RMAP_RC_SHIFT;
137 static pte_t lookup_linux_pte(pgd_t *pgdir, unsigned long hva,
138 int writing, unsigned long *pte_sizep)
141 unsigned long ps = *pte_sizep;
142 unsigned int hugepage_shift;
144 ptep = find_linux_pte_or_hugepte(pgdir, hva, &hugepage_shift);
148 *pte_sizep = 1ul << hugepage_shift;
150 *pte_sizep = PAGE_SIZE;
153 return kvmppc_read_update_linux_pte(ptep, writing, hugepage_shift);
156 static inline void unlock_hpte(unsigned long *hpte, unsigned long hpte_v)
158 asm volatile(PPC_RELEASE_BARRIER "" : : : "memory");
162 long kvmppc_do_h_enter(struct kvm *kvm, unsigned long flags,
163 long pte_index, unsigned long pteh, unsigned long ptel,
164 pgd_t *pgdir, bool realmode, unsigned long *pte_idx_ret)
166 unsigned long i, pa, gpa, gfn, psize;
167 unsigned long slot_fn, hva;
169 struct revmap_entry *rev;
170 unsigned long g_ptel;
171 struct kvm_memory_slot *memslot;
172 unsigned long *physp, pte_size;
176 unsigned int writing;
177 unsigned long mmu_seq;
178 unsigned long rcbits;
180 psize = hpte_page_size(pteh, ptel);
183 writing = hpte_is_writable(ptel);
184 pteh &= ~(HPTE_V_HVLOCK | HPTE_V_ABSENT | HPTE_V_VALID);
185 ptel &= ~HPTE_GR_RESERVED;
188 /* used later to detect if we might have been invalidated */
189 mmu_seq = kvm->mmu_notifier_seq;
192 /* Find the memslot (if any) for this address */
193 gpa = (ptel & HPTE_R_RPN) & ~(psize - 1);
194 gfn = gpa >> PAGE_SHIFT;
195 memslot = __gfn_to_memslot(kvm_memslots(kvm), gfn);
199 if (!(memslot && !(memslot->flags & KVM_MEMSLOT_INVALID))) {
200 /* PPC970 can't do emulated MMIO */
201 if (!cpu_has_feature(CPU_FTR_ARCH_206))
203 /* Emulated MMIO - mark this with key=31 */
204 pteh |= HPTE_V_ABSENT;
205 ptel |= HPTE_R_KEY_HI | HPTE_R_KEY_LO;
209 /* Check if the requested page fits entirely in the memslot. */
210 if (!slot_is_aligned(memslot, psize))
212 slot_fn = gfn - memslot->base_gfn;
213 rmap = &memslot->arch.rmap[slot_fn];
215 if (!kvm->arch.using_mmu_notifiers) {
216 physp = memslot->arch.slot_phys;
221 physp = real_vmalloc_addr(physp);
225 is_io = pa & (HPTE_R_I | HPTE_R_W);
226 pte_size = PAGE_SIZE << (pa & KVMPPC_PAGE_ORDER_MASK);
229 /* Translate to host virtual address */
230 hva = __gfn_to_hva_memslot(memslot, gfn);
232 /* Look up the Linux PTE for the backing page */
234 pte = lookup_linux_pte(pgdir, hva, writing, &pte_size);
235 if (pte_present(pte)) {
236 if (writing && !pte_write(pte))
237 /* make the actual HPTE be read-only */
238 ptel = hpte_make_readonly(ptel);
239 is_io = hpte_cache_bits(pte_val(pte));
240 pa = pte_pfn(pte) << PAGE_SHIFT;
244 if (pte_size < psize)
246 if (pa && pte_size > psize)
247 pa |= gpa & (pte_size - 1);
249 ptel &= ~(HPTE_R_PP0 - psize);
253 pteh |= HPTE_V_VALID;
255 pteh |= HPTE_V_ABSENT;
258 if (is_io != ~0ul && !hpte_cache_flags_ok(ptel, is_io)) {
262 * Allow guest to map emulated device memory as
263 * uncacheable, but actually make it cacheable.
265 ptel &= ~(HPTE_R_W|HPTE_R_I|HPTE_R_G);
269 /* Find and lock the HPTEG slot to use */
271 if (pte_index >= kvm->arch.hpt_npte)
273 if (likely((flags & H_EXACT) == 0)) {
275 hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
276 for (i = 0; i < 8; ++i) {
277 if ((*hpte & HPTE_V_VALID) == 0 &&
278 try_lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID |
285 * Since try_lock_hpte doesn't retry (not even stdcx.
286 * failures), it could be that there is a free slot
287 * but we transiently failed to lock it. Try again,
288 * actually locking each slot and checking it.
291 for (i = 0; i < 8; ++i) {
292 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
294 if (!(*hpte & (HPTE_V_VALID | HPTE_V_ABSENT)))
296 *hpte &= ~HPTE_V_HVLOCK;
304 hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
305 if (!try_lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID |
307 /* Lock the slot and check again */
308 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
310 if (*hpte & (HPTE_V_VALID | HPTE_V_ABSENT)) {
311 *hpte &= ~HPTE_V_HVLOCK;
317 /* Save away the guest's idea of the second HPTE dword */
318 rev = &kvm->arch.revmap[pte_index];
320 rev = real_vmalloc_addr(rev);
322 rev->guest_rpte = g_ptel;
323 note_hpte_modification(kvm, rev);
326 /* Link HPTE into reverse-map chain */
327 if (pteh & HPTE_V_VALID) {
329 rmap = real_vmalloc_addr(rmap);
331 /* Check for pending invalidations under the rmap chain lock */
332 if (kvm->arch.using_mmu_notifiers &&
333 mmu_notifier_retry(kvm, mmu_seq)) {
334 /* inval in progress, write a non-present HPTE */
335 pteh |= HPTE_V_ABSENT;
336 pteh &= ~HPTE_V_VALID;
339 kvmppc_add_revmap_chain(kvm, rev, rmap, pte_index,
341 /* Only set R/C in real HPTE if already set in *rmap */
342 rcbits = *rmap >> KVMPPC_RMAP_RC_SHIFT;
343 ptel &= rcbits | ~(HPTE_R_R | HPTE_R_C);
349 /* Write the first HPTE dword, unlocking the HPTE and making it valid */
352 asm volatile("ptesync" : : : "memory");
354 *pte_idx_ret = pte_index;
357 EXPORT_SYMBOL_GPL(kvmppc_do_h_enter);
359 long kvmppc_h_enter(struct kvm_vcpu *vcpu, unsigned long flags,
360 long pte_index, unsigned long pteh, unsigned long ptel)
362 return kvmppc_do_h_enter(vcpu->kvm, flags, pte_index, pteh, ptel,
363 vcpu->arch.pgdir, true, &vcpu->arch.gpr[4]);
366 #ifdef __BIG_ENDIAN__
367 #define LOCK_TOKEN (*(u32 *)(&get_paca()->lock_token))
369 #define LOCK_TOKEN (*(u32 *)(&get_paca()->paca_index))
372 static inline int try_lock_tlbie(unsigned int *lock)
374 unsigned int tmp, old;
375 unsigned int token = LOCK_TOKEN;
377 asm volatile("1:lwarx %1,0,%2\n"
384 : "=&r" (tmp), "=&r" (old)
385 : "r" (lock), "r" (token)
390 long kvmppc_do_h_remove(struct kvm *kvm, unsigned long flags,
391 unsigned long pte_index, unsigned long avpn,
392 unsigned long *hpret)
395 unsigned long v, r, rb;
396 struct revmap_entry *rev;
398 if (pte_index >= kvm->arch.hpt_npte)
400 hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
401 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
403 if ((hpte[0] & (HPTE_V_ABSENT | HPTE_V_VALID)) == 0 ||
404 ((flags & H_AVPN) && (hpte[0] & ~0x7fUL) != avpn) ||
405 ((flags & H_ANDCOND) && (hpte[0] & avpn) != 0)) {
406 hpte[0] &= ~HPTE_V_HVLOCK;
410 rev = real_vmalloc_addr(&kvm->arch.revmap[pte_index]);
411 v = hpte[0] & ~HPTE_V_HVLOCK;
412 if (v & HPTE_V_VALID) {
413 hpte[0] &= ~HPTE_V_VALID;
414 rb = compute_tlbie_rb(v, hpte[1], pte_index);
415 if (global_invalidates(kvm, flags)) {
416 while (!try_lock_tlbie(&kvm->arch.tlbie_lock))
418 asm volatile("ptesync" : : : "memory");
419 asm volatile(PPC_TLBIE(%1,%0)"; eieio; tlbsync"
420 : : "r" (rb), "r" (kvm->arch.lpid));
421 asm volatile("ptesync" : : : "memory");
422 kvm->arch.tlbie_lock = 0;
424 asm volatile("ptesync" : : : "memory");
425 asm volatile("tlbiel %0" : : "r" (rb));
426 asm volatile("ptesync" : : : "memory");
428 /* Read PTE low word after tlbie to get final R/C values */
429 remove_revmap_chain(kvm, pte_index, rev, v, hpte[1]);
431 r = rev->guest_rpte & ~HPTE_GR_RESERVED;
432 note_hpte_modification(kvm, rev);
433 unlock_hpte(hpte, 0);
439 EXPORT_SYMBOL_GPL(kvmppc_do_h_remove);
441 long kvmppc_h_remove(struct kvm_vcpu *vcpu, unsigned long flags,
442 unsigned long pte_index, unsigned long avpn)
444 return kvmppc_do_h_remove(vcpu->kvm, flags, pte_index, avpn,
448 long kvmppc_h_bulk_remove(struct kvm_vcpu *vcpu)
450 struct kvm *kvm = vcpu->kvm;
451 unsigned long *args = &vcpu->arch.gpr[4];
452 unsigned long *hp, *hptes[4], tlbrb[4];
453 long int i, j, k, n, found, indexes[4];
454 unsigned long flags, req, pte_index, rcbits;
456 long int ret = H_SUCCESS;
457 struct revmap_entry *rev, *revs[4];
459 if (atomic_read(&kvm->online_vcpus) == 1)
461 for (i = 0; i < 4 && ret == H_SUCCESS; ) {
466 flags = pte_index >> 56;
467 pte_index &= ((1ul << 56) - 1);
470 if (req == 3) { /* no more requests */
474 if (req != 1 || flags == 3 ||
475 pte_index >= kvm->arch.hpt_npte) {
476 /* parameter error */
477 args[j] = ((0xa0 | flags) << 56) + pte_index;
481 hp = (unsigned long *)
482 (kvm->arch.hpt_virt + (pte_index << 4));
483 /* to avoid deadlock, don't spin except for first */
484 if (!try_lock_hpte(hp, HPTE_V_HVLOCK)) {
487 while (!try_lock_hpte(hp, HPTE_V_HVLOCK))
491 if (hp[0] & (HPTE_V_ABSENT | HPTE_V_VALID)) {
493 case 0: /* absolute */
496 case 1: /* andcond */
497 if (!(hp[0] & args[j + 1]))
501 if ((hp[0] & ~0x7fUL) == args[j + 1])
507 hp[0] &= ~HPTE_V_HVLOCK;
508 args[j] = ((0x90 | flags) << 56) + pte_index;
512 args[j] = ((0x80 | flags) << 56) + pte_index;
513 rev = real_vmalloc_addr(&kvm->arch.revmap[pte_index]);
514 note_hpte_modification(kvm, rev);
516 if (!(hp[0] & HPTE_V_VALID)) {
517 /* insert R and C bits from PTE */
518 rcbits = rev->guest_rpte & (HPTE_R_R|HPTE_R_C);
519 args[j] |= rcbits << (56 - 5);
524 hp[0] &= ~HPTE_V_VALID; /* leave it locked */
525 tlbrb[n] = compute_tlbie_rb(hp[0], hp[1], pte_index);
535 /* Now that we've collected a batch, do the tlbies */
537 while(!try_lock_tlbie(&kvm->arch.tlbie_lock))
539 asm volatile("ptesync" : : : "memory");
540 for (k = 0; k < n; ++k)
541 asm volatile(PPC_TLBIE(%1,%0) : :
543 "r" (kvm->arch.lpid));
544 asm volatile("eieio; tlbsync; ptesync" : : : "memory");
545 kvm->arch.tlbie_lock = 0;
547 asm volatile("ptesync" : : : "memory");
548 for (k = 0; k < n; ++k)
549 asm volatile("tlbiel %0" : : "r" (tlbrb[k]));
550 asm volatile("ptesync" : : : "memory");
553 /* Read PTE low words after tlbie to get final R/C values */
554 for (k = 0; k < n; ++k) {
556 pte_index = args[j] & ((1ul << 56) - 1);
559 remove_revmap_chain(kvm, pte_index, rev, hp[0], hp[1]);
560 rcbits = rev->guest_rpte & (HPTE_R_R|HPTE_R_C);
561 args[j] |= rcbits << (56 - 5);
569 long kvmppc_h_protect(struct kvm_vcpu *vcpu, unsigned long flags,
570 unsigned long pte_index, unsigned long avpn,
573 struct kvm *kvm = vcpu->kvm;
575 struct revmap_entry *rev;
576 unsigned long v, r, rb, mask, bits;
578 if (pte_index >= kvm->arch.hpt_npte)
581 hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
582 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
584 if ((hpte[0] & (HPTE_V_ABSENT | HPTE_V_VALID)) == 0 ||
585 ((flags & H_AVPN) && (hpte[0] & ~0x7fUL) != avpn)) {
586 hpte[0] &= ~HPTE_V_HVLOCK;
591 bits = (flags << 55) & HPTE_R_PP0;
592 bits |= (flags << 48) & HPTE_R_KEY_HI;
593 bits |= flags & (HPTE_R_PP | HPTE_R_N | HPTE_R_KEY_LO);
595 /* Update guest view of 2nd HPTE dword */
596 mask = HPTE_R_PP0 | HPTE_R_PP | HPTE_R_N |
597 HPTE_R_KEY_HI | HPTE_R_KEY_LO;
598 rev = real_vmalloc_addr(&kvm->arch.revmap[pte_index]);
600 r = (rev->guest_rpte & ~mask) | bits;
602 note_hpte_modification(kvm, rev);
604 r = (hpte[1] & ~mask) | bits;
607 if (v & HPTE_V_VALID) {
608 rb = compute_tlbie_rb(v, r, pte_index);
609 hpte[0] = v & ~HPTE_V_VALID;
610 if (global_invalidates(kvm, flags)) {
611 while(!try_lock_tlbie(&kvm->arch.tlbie_lock))
613 asm volatile("ptesync" : : : "memory");
614 asm volatile(PPC_TLBIE(%1,%0)"; eieio; tlbsync"
615 : : "r" (rb), "r" (kvm->arch.lpid));
616 asm volatile("ptesync" : : : "memory");
617 kvm->arch.tlbie_lock = 0;
619 asm volatile("ptesync" : : : "memory");
620 asm volatile("tlbiel %0" : : "r" (rb));
621 asm volatile("ptesync" : : : "memory");
624 * If the host has this page as readonly but the guest
625 * wants to make it read/write, reduce the permissions.
626 * Checking the host permissions involves finding the
627 * memslot and then the Linux PTE for the page.
629 if (hpte_is_writable(r) && kvm->arch.using_mmu_notifiers) {
630 unsigned long psize, gfn, hva;
631 struct kvm_memory_slot *memslot;
632 pgd_t *pgdir = vcpu->arch.pgdir;
635 psize = hpte_page_size(v, r);
636 gfn = ((r & HPTE_R_RPN) & ~(psize - 1)) >> PAGE_SHIFT;
637 memslot = __gfn_to_memslot(kvm_memslots(kvm), gfn);
639 hva = __gfn_to_hva_memslot(memslot, gfn);
640 pte = lookup_linux_pte(pgdir, hva, 1, &psize);
641 if (pte_present(pte) && !pte_write(pte))
642 r = hpte_make_readonly(r);
648 hpte[0] = v & ~HPTE_V_HVLOCK;
649 asm volatile("ptesync" : : : "memory");
653 long kvmppc_h_read(struct kvm_vcpu *vcpu, unsigned long flags,
654 unsigned long pte_index)
656 struct kvm *kvm = vcpu->kvm;
657 unsigned long *hpte, v, r;
659 struct revmap_entry *rev = NULL;
661 if (pte_index >= kvm->arch.hpt_npte)
663 if (flags & H_READ_4) {
667 rev = real_vmalloc_addr(&kvm->arch.revmap[pte_index]);
668 for (i = 0; i < n; ++i, ++pte_index) {
669 hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
670 v = hpte[0] & ~HPTE_V_HVLOCK;
672 if (v & HPTE_V_ABSENT) {
676 if (v & HPTE_V_VALID) {
677 r = rev[i].guest_rpte | (r & (HPTE_R_R | HPTE_R_C));
678 r &= ~HPTE_GR_RESERVED;
680 vcpu->arch.gpr[4 + i * 2] = v;
681 vcpu->arch.gpr[5 + i * 2] = r;
686 void kvmppc_invalidate_hpte(struct kvm *kvm, unsigned long *hptep,
687 unsigned long pte_index)
691 hptep[0] &= ~HPTE_V_VALID;
692 rb = compute_tlbie_rb(hptep[0], hptep[1], pte_index);
693 while (!try_lock_tlbie(&kvm->arch.tlbie_lock))
695 asm volatile("ptesync" : : : "memory");
696 asm volatile(PPC_TLBIE(%1,%0)"; eieio; tlbsync"
697 : : "r" (rb), "r" (kvm->arch.lpid));
698 asm volatile("ptesync" : : : "memory");
699 kvm->arch.tlbie_lock = 0;
701 EXPORT_SYMBOL_GPL(kvmppc_invalidate_hpte);
703 void kvmppc_clear_ref_hpte(struct kvm *kvm, unsigned long *hptep,
704 unsigned long pte_index)
709 rb = compute_tlbie_rb(hptep[0], hptep[1], pte_index);
710 rbyte = (hptep[1] & ~HPTE_R_R) >> 8;
711 /* modify only the second-last byte, which contains the ref bit */
712 *((char *)hptep + 14) = rbyte;
713 while (!try_lock_tlbie(&kvm->arch.tlbie_lock))
715 asm volatile(PPC_TLBIE(%1,%0)"; eieio; tlbsync"
716 : : "r" (rb), "r" (kvm->arch.lpid));
717 asm volatile("ptesync" : : : "memory");
718 kvm->arch.tlbie_lock = 0;
720 EXPORT_SYMBOL_GPL(kvmppc_clear_ref_hpte);
722 static int slb_base_page_shift[4] = {
726 20, /* 1M, unsupported */
729 long kvmppc_hv_find_lock_hpte(struct kvm *kvm, gva_t eaddr, unsigned long slb_v,
734 unsigned long somask;
735 unsigned long vsid, hash;
738 unsigned long mask, val;
741 /* Get page shift, work out hash and AVPN etc. */
742 mask = SLB_VSID_B | HPTE_V_AVPN | HPTE_V_SECONDARY;
745 if (slb_v & SLB_VSID_L) {
746 mask |= HPTE_V_LARGE;
748 pshift = slb_base_page_shift[(slb_v & SLB_VSID_LP) >> 4];
750 if (slb_v & SLB_VSID_B_1T) {
751 somask = (1UL << 40) - 1;
752 vsid = (slb_v & ~SLB_VSID_B) >> SLB_VSID_SHIFT_1T;
755 somask = (1UL << 28) - 1;
756 vsid = (slb_v & ~SLB_VSID_B) >> SLB_VSID_SHIFT;
758 hash = (vsid ^ ((eaddr & somask) >> pshift)) & kvm->arch.hpt_mask;
759 avpn = slb_v & ~(somask >> 16); /* also includes B */
760 avpn |= (eaddr & somask) >> 16;
763 avpn &= ~((1UL << (pshift - 16)) - 1);
769 hpte = (unsigned long *)(kvm->arch.hpt_virt + (hash << 7));
771 for (i = 0; i < 16; i += 2) {
772 /* Read the PTE racily */
773 v = hpte[i] & ~HPTE_V_HVLOCK;
775 /* Check valid/absent, hash, segment size and AVPN */
776 if (!(v & valid) || (v & mask) != val)
779 /* Lock the PTE and read it under the lock */
780 while (!try_lock_hpte(&hpte[i], HPTE_V_HVLOCK))
782 v = hpte[i] & ~HPTE_V_HVLOCK;
786 * Check the HPTE again, including large page size
787 * Since we don't currently allow any MPSS (mixed
788 * page-size segment) page sizes, it is sufficient
789 * to check against the actual page size.
791 if ((v & valid) && (v & mask) == val &&
792 hpte_page_size(v, r) == (1ul << pshift))
793 /* Return with the HPTE still locked */
794 return (hash << 3) + (i >> 1);
796 /* Unlock and move on */
800 if (val & HPTE_V_SECONDARY)
802 val |= HPTE_V_SECONDARY;
803 hash = hash ^ kvm->arch.hpt_mask;
807 EXPORT_SYMBOL(kvmppc_hv_find_lock_hpte);
810 * Called in real mode to check whether an HPTE not found fault
811 * is due to accessing a paged-out page or an emulated MMIO page,
812 * or if a protection fault is due to accessing a page that the
813 * guest wanted read/write access to but which we made read-only.
814 * Returns a possibly modified status (DSISR) value if not
815 * (i.e. pass the interrupt to the guest),
816 * -1 to pass the fault up to host kernel mode code, -2 to do that
817 * and also load the instruction word (for MMIO emulation),
818 * or 0 if we should make the guest retry the access.
820 long kvmppc_hpte_hv_fault(struct kvm_vcpu *vcpu, unsigned long addr,
821 unsigned long slb_v, unsigned int status, bool data)
823 struct kvm *kvm = vcpu->kvm;
825 unsigned long v, r, gr;
828 struct revmap_entry *rev;
829 unsigned long pp, key;
831 /* For protection fault, expect to find a valid HPTE */
832 valid = HPTE_V_VALID;
833 if (status & DSISR_NOHPTE)
834 valid |= HPTE_V_ABSENT;
836 index = kvmppc_hv_find_lock_hpte(kvm, addr, slb_v, valid);
838 if (status & DSISR_NOHPTE)
839 return status; /* there really was no HPTE */
840 return 0; /* for prot fault, HPTE disappeared */
842 hpte = (unsigned long *)(kvm->arch.hpt_virt + (index << 4));
843 v = hpte[0] & ~HPTE_V_HVLOCK;
845 rev = real_vmalloc_addr(&kvm->arch.revmap[index]);
846 gr = rev->guest_rpte;
848 unlock_hpte(hpte, v);
850 /* For not found, if the HPTE is valid by now, retry the instruction */
851 if ((status & DSISR_NOHPTE) && (v & HPTE_V_VALID))
854 /* Check access permissions to the page */
855 pp = gr & (HPTE_R_PP0 | HPTE_R_PP);
856 key = (vcpu->arch.shregs.msr & MSR_PR) ? SLB_VSID_KP : SLB_VSID_KS;
857 status &= ~DSISR_NOHPTE; /* DSISR_NOHPTE == SRR1_ISI_NOPT */
859 if (gr & (HPTE_R_N | HPTE_R_G))
860 return status | SRR1_ISI_N_OR_G;
861 if (!hpte_read_permission(pp, slb_v & key))
862 return status | SRR1_ISI_PROT;
863 } else if (status & DSISR_ISSTORE) {
864 /* check write permission */
865 if (!hpte_write_permission(pp, slb_v & key))
866 return status | DSISR_PROTFAULT;
868 if (!hpte_read_permission(pp, slb_v & key))
869 return status | DSISR_PROTFAULT;
872 /* Check storage key, if applicable */
873 if (data && (vcpu->arch.shregs.msr & MSR_DR)) {
874 unsigned int perm = hpte_get_skey_perm(gr, vcpu->arch.amr);
875 if (status & DSISR_ISSTORE)
878 return status | DSISR_KEYFAULT;
881 /* Save HPTE info for virtual-mode handler */
882 vcpu->arch.pgfault_addr = addr;
883 vcpu->arch.pgfault_index = index;
884 vcpu->arch.pgfault_hpte[0] = v;
885 vcpu->arch.pgfault_hpte[1] = r;
887 /* Check the storage key to see if it is possibly emulated MMIO */
888 if (data && (vcpu->arch.shregs.msr & MSR_IR) &&
889 (r & (HPTE_R_KEY_HI | HPTE_R_KEY_LO)) ==
890 (HPTE_R_KEY_HI | HPTE_R_KEY_LO))
891 return -2; /* MMIO emulation - load instr word */
893 return -1; /* send fault up to host kernel mode */