2 * Copyright 2012 Michael Ellerman, IBM Corporation.
3 * Copyright 2012 Benjamin Herrenschmidt, IBM Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
10 #include <linux/kernel.h>
11 #include <linux/kvm_host.h>
12 #include <linux/err.h>
14 #include <asm/kvm_book3s.h>
15 #include <asm/kvm_ppc.h>
16 #include <asm/hvcall.h>
18 #include <asm/debug.h>
19 #include <asm/synch.h>
20 #include <asm/ppc-opcode.h>
22 #include "book3s_xics.h"
26 static void icp_rm_deliver_irq(struct kvmppc_xics *xics, struct kvmppc_icp *icp,
29 /* -- ICS routines -- */
30 static void ics_rm_check_resend(struct kvmppc_xics *xics,
31 struct kvmppc_ics *ics, struct kvmppc_icp *icp)
35 arch_spin_lock(&ics->lock);
37 for (i = 0; i < KVMPPC_XICS_IRQ_PER_ICS; i++) {
38 struct ics_irq_state *state = &ics->irq_state[i];
43 arch_spin_unlock(&ics->lock);
44 icp_rm_deliver_irq(xics, icp, state->number);
45 arch_spin_lock(&ics->lock);
48 arch_spin_unlock(&ics->lock);
51 /* -- ICP routines -- */
53 static void icp_rm_set_vcpu_irq(struct kvm_vcpu *vcpu,
54 struct kvm_vcpu *this_vcpu)
56 struct kvmppc_icp *this_icp = this_vcpu->arch.icp;
59 /* Mark the target VCPU as having an interrupt pending */
60 vcpu->stat.queue_intr++;
61 set_bit(BOOK3S_IRQPRIO_EXTERNAL_LEVEL, &vcpu->arch.pending_exceptions);
63 /* Kick self ? Just set MER and return */
64 if (vcpu == this_vcpu) {
65 mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) | LPCR_MER);
69 /* Check if the core is loaded, if not, too hard */
71 if (cpu < 0 || cpu >= nr_cpu_ids) {
72 this_icp->rm_action |= XICS_RM_KICK_VCPU;
73 this_icp->rm_kick_target = vcpu;
76 /* In SMT cpu will always point to thread 0, we adjust it */
77 cpu += vcpu->arch.ptid;
80 kvmhv_rm_send_ipi(cpu);
83 static void icp_rm_clr_vcpu_irq(struct kvm_vcpu *vcpu)
85 /* Note: Only called on self ! */
86 clear_bit(BOOK3S_IRQPRIO_EXTERNAL_LEVEL,
87 &vcpu->arch.pending_exceptions);
88 mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) & ~LPCR_MER);
91 static inline bool icp_rm_try_update(struct kvmppc_icp *icp,
92 union kvmppc_icp_state old,
93 union kvmppc_icp_state new)
95 struct kvm_vcpu *this_vcpu = local_paca->kvm_hstate.kvm_vcpu;
98 /* Calculate new output value */
99 new.out_ee = (new.xisr && (new.pending_pri < new.cppr));
101 /* Attempt atomic update */
102 success = cmpxchg64(&icp->state.raw, old.raw, new.raw) == old.raw;
107 * Check for output state update
109 * Note that this is racy since another processor could be updating
110 * the state already. This is why we never clear the interrupt output
111 * here, we only ever set it. The clear only happens prior to doing
112 * an update and only by the processor itself. Currently we do it
113 * in Accept (H_XIRR) and Up_Cppr (H_XPPR).
115 * We also do not try to figure out whether the EE state has changed,
116 * we unconditionally set it if the new state calls for it. The reason
117 * for that is that we opportunistically remove the pending interrupt
118 * flag when raising CPPR, so we need to set it back here if an
119 * interrupt is still pending.
122 icp_rm_set_vcpu_irq(icp->vcpu, this_vcpu);
124 /* Expose the state change for debug purposes */
125 this_vcpu->arch.icp->rm_dbgstate = new;
126 this_vcpu->arch.icp->rm_dbgtgt = icp->vcpu;
132 static inline int check_too_hard(struct kvmppc_xics *xics,
133 struct kvmppc_icp *icp)
135 return (xics->real_mode_dbg || icp->rm_action) ? H_TOO_HARD : H_SUCCESS;
138 static void icp_rm_check_resend(struct kvmppc_xics *xics,
139 struct kvmppc_icp *icp)
143 /* Order this load with the test for need_resend in the caller */
145 for_each_set_bit(icsid, icp->resend_map, xics->max_icsid + 1) {
146 struct kvmppc_ics *ics = xics->ics[icsid];
148 if (!test_and_clear_bit(icsid, icp->resend_map))
152 ics_rm_check_resend(xics, ics, icp);
156 static bool icp_rm_try_to_deliver(struct kvmppc_icp *icp, u32 irq, u8 priority,
159 union kvmppc_icp_state old_state, new_state;
163 old_state = new_state = READ_ONCE(icp->state);
167 /* See if we can deliver */
168 success = new_state.cppr > priority &&
169 new_state.mfrr > priority &&
170 new_state.pending_pri > priority;
173 * If we can, check for a rejection and perform the
177 *reject = new_state.xisr;
178 new_state.xisr = irq;
179 new_state.pending_pri = priority;
182 * If we failed to deliver we set need_resend
183 * so a subsequent CPPR state change causes us
184 * to try a new delivery.
186 new_state.need_resend = true;
189 } while (!icp_rm_try_update(icp, old_state, new_state));
194 static void icp_rm_deliver_irq(struct kvmppc_xics *xics, struct kvmppc_icp *icp,
197 struct ics_irq_state *state;
198 struct kvmppc_ics *ics;
203 * This is used both for initial delivery of an interrupt and
204 * for subsequent rejection.
206 * Rejection can be racy vs. resends. We have evaluated the
207 * rejection in an atomic ICP transaction which is now complete,
208 * so potentially the ICP can already accept the interrupt again.
210 * So we need to retry the delivery. Essentially the reject path
211 * boils down to a failed delivery. Always.
213 * Now the interrupt could also have moved to a different target,
214 * thus we may need to re-do the ICP lookup as well
218 /* Get the ICS state and lock it */
219 ics = kvmppc_xics_find_ics(xics, new_irq, &src);
221 /* Unsafe increment, but this does not need to be accurate */
225 state = &ics->irq_state[src];
227 /* Get a lock on the ICS */
228 arch_spin_lock(&ics->lock);
231 if (!icp || state->server != icp->server_num) {
232 icp = kvmppc_xics_find_server(xics->kvm, state->server);
234 /* Unsafe increment again*/
240 /* Clear the resend bit of that interrupt */
244 * If masked, bail out
246 * Note: PAPR doesn't mention anything about masked pending
247 * when doing a resend, only when doing a delivery.
249 * However that would have the effect of losing a masked
250 * interrupt that was rejected and isn't consistent with
251 * the whole masked_pending business which is about not
252 * losing interrupts that occur while masked.
254 * I don't differentiate normal deliveries and resends, this
255 * implementation will differ from PAPR and not lose such
258 if (state->priority == MASKED) {
259 state->masked_pending = 1;
264 * Try the delivery, this will set the need_resend flag
265 * in the ICP as part of the atomic transaction if the
266 * delivery is not possible.
268 * Note that if successful, the new delivery might have itself
269 * rejected an interrupt that was "delivered" before we took the
272 * In this case we do the whole sequence all over again for the
273 * new guy. We cannot assume that the rejected interrupt is less
274 * favored than the new one, and thus doesn't need to be delivered,
275 * because by the time we exit icp_rm_try_to_deliver() the target
276 * processor may well have already consumed & completed it, and thus
277 * the rejected interrupt might actually be already acceptable.
279 if (icp_rm_try_to_deliver(icp, new_irq, state->priority, &reject)) {
281 * Delivery was successful, did we reject somebody else ?
283 if (reject && reject != XICS_IPI) {
284 arch_spin_unlock(&ics->lock);
290 * We failed to deliver the interrupt we need to set the
291 * resend map bit and mark the ICS state as needing a resend
293 set_bit(ics->icsid, icp->resend_map);
297 * If the need_resend flag got cleared in the ICP some time
298 * between icp_rm_try_to_deliver() atomic update and now, then
299 * we know it might have missed the resend_map bit. So we
303 if (!icp->state.need_resend) {
304 arch_spin_unlock(&ics->lock);
309 arch_spin_unlock(&ics->lock);
312 static void icp_rm_down_cppr(struct kvmppc_xics *xics, struct kvmppc_icp *icp,
315 union kvmppc_icp_state old_state, new_state;
319 * This handles several related states in one operation:
321 * ICP State: Down_CPPR
323 * Load CPPR with new value and if the XISR is 0
324 * then check for resends:
328 * If MFRR is more favored than CPPR, check for IPIs
329 * and notify ICS of a potential resend. This is done
330 * asynchronously (when used in real mode, we will have
333 * We do not handle the complete Check_IPI as documented
334 * here. In the PAPR, this state will be used for both
335 * Set_MFRR and Down_CPPR. However, we know that we aren't
336 * changing the MFRR state here so we don't need to handle
337 * the case of an MFRR causing a reject of a pending irq,
338 * this will have been handled when the MFRR was set in the
341 * Thus we don't have to handle rejects, only resends.
343 * When implementing real mode for HV KVM, resend will lead to
344 * a H_TOO_HARD return and the whole transaction will be handled
348 old_state = new_state = READ_ONCE(icp->state);
351 new_state.cppr = new_cppr;
354 * Cut down Resend / Check_IPI / IPI
356 * The logic is that we cannot have a pending interrupt
357 * trumped by an IPI at this point (see above), so we
358 * know that either the pending interrupt is already an
359 * IPI (in which case we don't care to override it) or
360 * it's either more favored than us or non existent
362 if (new_state.mfrr < new_cppr &&
363 new_state.mfrr <= new_state.pending_pri) {
364 new_state.pending_pri = new_state.mfrr;
365 new_state.xisr = XICS_IPI;
368 /* Latch/clear resend bit */
369 resend = new_state.need_resend;
370 new_state.need_resend = 0;
372 } while (!icp_rm_try_update(icp, old_state, new_state));
375 * Now handle resend checks. Those are asynchronous to the ICP
376 * state update in HW (ie bus transactions) so we can handle them
377 * separately here as well.
380 icp->n_check_resend++;
381 icp_rm_check_resend(xics, icp);
386 unsigned long kvmppc_rm_h_xirr(struct kvm_vcpu *vcpu)
388 union kvmppc_icp_state old_state, new_state;
389 struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
390 struct kvmppc_icp *icp = vcpu->arch.icp;
393 if (!xics || !xics->real_mode)
396 /* First clear the interrupt */
397 icp_rm_clr_vcpu_irq(icp->vcpu);
400 * ICP State: Accept_Interrupt
402 * Return the pending interrupt (if any) along with the
403 * current CPPR, then clear the XISR & set CPPR to the
407 old_state = new_state = READ_ONCE(icp->state);
409 xirr = old_state.xisr | (((u32)old_state.cppr) << 24);
412 new_state.cppr = new_state.pending_pri;
413 new_state.pending_pri = 0xff;
416 } while (!icp_rm_try_update(icp, old_state, new_state));
418 /* Return the result in GPR4 */
419 vcpu->arch.gpr[4] = xirr;
421 return check_too_hard(xics, icp);
424 int kvmppc_rm_h_ipi(struct kvm_vcpu *vcpu, unsigned long server,
427 union kvmppc_icp_state old_state, new_state;
428 struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
429 struct kvmppc_icp *icp, *this_icp = vcpu->arch.icp;
434 if (!xics || !xics->real_mode)
437 local = this_icp->server_num == server;
441 icp = kvmppc_xics_find_server(vcpu->kvm, server);
446 * ICP state: Set_MFRR
448 * If the CPPR is more favored than the new MFRR, then
449 * nothing needs to be done as there can be no XISR to
452 * ICP state: Check_IPI
454 * If the CPPR is less favored, then we might be replacing
455 * an interrupt, and thus need to possibly reject it.
459 * Besides rejecting any pending interrupts, we also
460 * update XISR and pending_pri to mark IPI as pending.
462 * PAPR does not describe this state, but if the MFRR is being
463 * made less favored than its earlier value, there might be
464 * a previously-rejected interrupt needing to be resent.
465 * Ideally, we would want to resend only if
466 * prio(pending_interrupt) < mfrr &&
467 * prio(pending_interrupt) < cppr
468 * where pending interrupt is the one that was rejected. But
469 * we don't have that state, so we simply trigger a resend
470 * whenever the MFRR is made less favored.
473 old_state = new_state = READ_ONCE(icp->state);
476 new_state.mfrr = mfrr;
481 if (mfrr < new_state.cppr) {
482 /* Reject a pending interrupt if not an IPI */
483 if (mfrr <= new_state.pending_pri) {
484 reject = new_state.xisr;
485 new_state.pending_pri = mfrr;
486 new_state.xisr = XICS_IPI;
490 if (mfrr > old_state.mfrr) {
491 resend = new_state.need_resend;
492 new_state.need_resend = 0;
494 } while (!icp_rm_try_update(icp, old_state, new_state));
496 /* Handle reject in real mode */
497 if (reject && reject != XICS_IPI) {
498 this_icp->n_reject++;
499 icp_rm_deliver_irq(xics, icp, reject);
502 /* Handle resends in real mode */
504 this_icp->n_check_resend++;
505 icp_rm_check_resend(xics, icp);
508 return check_too_hard(xics, this_icp);
511 int kvmppc_rm_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr)
513 union kvmppc_icp_state old_state, new_state;
514 struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
515 struct kvmppc_icp *icp = vcpu->arch.icp;
518 if (!xics || !xics->real_mode)
522 * ICP State: Set_CPPR
524 * We can safely compare the new value with the current
525 * value outside of the transaction as the CPPR is only
526 * ever changed by the processor on itself
528 if (cppr > icp->state.cppr) {
529 icp_rm_down_cppr(xics, icp, cppr);
531 } else if (cppr == icp->state.cppr)
537 * The processor is raising its priority, this can result
538 * in a rejection of a pending interrupt:
540 * ICP State: Reject_Current
542 * We can remove EE from the current processor, the update
543 * transaction will set it again if needed
545 icp_rm_clr_vcpu_irq(icp->vcpu);
548 old_state = new_state = READ_ONCE(icp->state);
551 new_state.cppr = cppr;
553 if (cppr <= new_state.pending_pri) {
554 reject = new_state.xisr;
556 new_state.pending_pri = 0xff;
559 } while (!icp_rm_try_update(icp, old_state, new_state));
562 * Check for rejects. They are handled by doing a new delivery
563 * attempt (see comments in icp_rm_deliver_irq).
565 if (reject && reject != XICS_IPI) {
567 icp_rm_deliver_irq(xics, icp, reject);
570 return check_too_hard(xics, icp);
573 int kvmppc_rm_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr)
575 struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
576 struct kvmppc_icp *icp = vcpu->arch.icp;
577 struct kvmppc_ics *ics;
578 struct ics_irq_state *state;
579 u32 irq = xirr & 0x00ffffff;
582 if (!xics || !xics->real_mode)
588 * Note: If EOI is incorrectly used by SW to lower the CPPR
589 * value (ie more favored), we do not check for rejection of
590 * a pending interrupt, this is a SW error and PAPR sepcifies
591 * that we don't have to deal with it.
593 * The sending of an EOI to the ICS is handled after the
596 * ICP State: Down_CPPR which we handle
597 * in a separate function as it's shared with H_CPPR.
599 icp_rm_down_cppr(xics, icp, xirr >> 24);
601 /* IPIs have no EOI */
605 * EOI handling: If the interrupt is still asserted, we need to
606 * resend it. We can take a lockless "peek" at the ICS state here.
608 * "Message" interrupts will never have "asserted" set
610 ics = kvmppc_xics_find_ics(xics, irq, &src);
613 state = &ics->irq_state[src];
615 /* Still asserted, resend it */
616 if (state->asserted) {
618 icp_rm_deliver_irq(xics, icp, irq);
621 if (!hlist_empty(&vcpu->kvm->irq_ack_notifier_list)) {
622 icp->rm_action |= XICS_RM_NOTIFY_EOI;
623 icp->rm_eoied_irq = irq;
626 return check_too_hard(xics, icp);