2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/mmu-hash64.h>
32 #ifdef __LITTLE_ENDIAN__
33 #error Need to fix lppaca and SLB shadow accesses in little endian mode
36 /*****************************************************************************
38 * Real Mode handlers that need to be in the linear mapping *
40 ****************************************************************************/
42 .globl kvmppc_skip_interrupt
43 kvmppc_skip_interrupt:
51 .globl kvmppc_skip_Hinterrupt
52 kvmppc_skip_Hinterrupt:
61 * Call kvmppc_hv_entry in real mode.
62 * Must be called with interrupts hard-disabled.
66 * LR = return address to continue at after eventually re-enabling MMU
68 _GLOBAL(kvmppc_hv_entry_trampoline)
70 LOAD_REG_ADDR(r5, kvmppc_hv_entry)
75 mtmsrd r0,1 /* clear RI in MSR */
80 /******************************************************************************
84 *****************************************************************************/
87 * We come in here when wakened from nap mode on a secondary hw thread.
88 * Relocation is off and most register values are lost.
89 * r13 points to the PACA.
91 .globl kvm_start_guest
93 ld r1,PACAEMERGSP(r13)
94 subi r1,r1,STACK_FRAME_OVERHEAD
97 li r0,KVM_HWTHREAD_IN_KVM
98 stb r0,HSTATE_HWTHREAD_STATE(r13)
100 /* NV GPR values from power7_idle() will no longer be valid */
102 stb r0,PACA_NAPSTATELOST(r13)
104 /* were we napping due to cede? */
105 lbz r0,HSTATE_NAPPING(r13)
110 * We weren't napping due to cede, so this must be a secondary
111 * thread being woken up to run a guest, or being woken up due
112 * to a stray IPI. (Or due to some machine check or hypervisor
113 * maintenance interrupt while the core is in KVM.)
116 /* Check the wake reason in SRR1 to see why we got here */
118 rlwinm r3,r3,44-31,0x7 /* extract wake reason field */
119 cmpwi r3,4 /* was it an external interrupt? */
121 ld r5,HSTATE_XICS_PHYS(r13)
122 li r7,XICS_XIRR /* if it was an external interrupt, */
123 lwzcix r8,r5,r7 /* get and ack the interrupt */
125 clrldi. r9,r8,40 /* get interrupt source ID. */
126 beq 28f /* none there? */
127 cmpwi r9,XICS_IPI /* was it an IPI? */
131 stbcix r0,r5,r6 /* clear IPI */
132 stwcix r8,r5,r7 /* EOI the interrupt */
133 sync /* order loading of vcpu after that */
135 /* get vcpu pointer, NULL if we have no vcpu to run */
136 ld r4,HSTATE_KVM_VCPU(r13)
138 /* if we have no vcpu to run, go back to sleep */
142 27: /* XXX should handle hypervisor maintenance interrupts etc. here */
144 28: /* SRR1 said external but ICP said nope?? */
146 29: /* External non-IPI interrupt to offline secondary thread? help?? */
147 stw r8,HSTATE_SAVED_XIRR(r13)
150 .global kvmppc_hv_entry
159 * all other volatile GPRS = free
162 std r0, HSTATE_VMHANDLER(r13)
164 /* Set partition DABR */
165 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
172 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
174 /* Load guest PMU registers */
175 /* R4 is live here (vcpu pointer) */
177 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
178 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
180 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
181 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
182 lwz r6, VCPU_PMC + 8(r4)
183 lwz r7, VCPU_PMC + 12(r4)
184 lwz r8, VCPU_PMC + 16(r4)
185 lwz r9, VCPU_PMC + 20(r4)
187 lwz r10, VCPU_PMC + 24(r4)
188 lwz r11, VCPU_PMC + 28(r4)
189 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
199 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
201 ld r5, VCPU_MMCR + 8(r4)
202 ld r6, VCPU_MMCR + 16(r4)
208 /* Load up FP, VMX and VSX registers */
211 ld r14, VCPU_GPR(R14)(r4)
212 ld r15, VCPU_GPR(R15)(r4)
213 ld r16, VCPU_GPR(R16)(r4)
214 ld r17, VCPU_GPR(R17)(r4)
215 ld r18, VCPU_GPR(R18)(r4)
216 ld r19, VCPU_GPR(R19)(r4)
217 ld r20, VCPU_GPR(R20)(r4)
218 ld r21, VCPU_GPR(R21)(r4)
219 ld r22, VCPU_GPR(R22)(r4)
220 ld r23, VCPU_GPR(R23)(r4)
221 ld r24, VCPU_GPR(R24)(r4)
222 ld r25, VCPU_GPR(R25)(r4)
223 ld r26, VCPU_GPR(R26)(r4)
224 ld r27, VCPU_GPR(R27)(r4)
225 ld r28, VCPU_GPR(R28)(r4)
226 ld r29, VCPU_GPR(R29)(r4)
227 ld r30, VCPU_GPR(R30)(r4)
228 ld r31, VCPU_GPR(R31)(r4)
231 /* Switch DSCR to guest value */
234 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
237 * Set the decrementer to the guest decrementer.
239 ld r8,VCPU_DEC_EXPIRES(r4)
245 ld r5, VCPU_SPRG0(r4)
246 ld r6, VCPU_SPRG1(r4)
247 ld r7, VCPU_SPRG2(r4)
248 ld r8, VCPU_SPRG3(r4)
254 /* Save R1 in the PACA */
255 std r1, HSTATE_HOST_R1(r13)
257 /* Increment yield count if they have a VPA */
261 lwz r5, LPPACA_YIELDCOUNT(r3)
263 stw r5, LPPACA_YIELDCOUNT(r3)
265 stb r6, VCPU_VPA_DIRTY(r4)
267 /* Load up DAR and DSISR */
269 lwz r6, VCPU_DSISR(r4)
274 /* Restore AMR and UAMOR, set AMOR to all 1s */
281 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
291 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
293 * POWER7 host -> guest partition switch code.
294 * We don't have to lock against concurrent tlbies,
295 * but we do have to coordinate across hardware threads.
297 /* Increment entry count iff exit count is zero. */
298 ld r5,HSTATE_KVM_VCORE(r13)
299 addi r9,r5,VCORE_ENTRY_EXIT
301 cmpwi r3,0x100 /* any threads starting to exit? */
302 bge secondary_too_late /* if so we're too late to the party */
307 /* Primary thread switches to guest partition. */
308 ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
314 li r0,LPID_RSVD /* switch to reserved LPID */
317 mtspr SPRN_SDR1,r6 /* switch to partition page table */
321 /* See if we need to flush the TLB */
322 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
323 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
324 srdi r6,r6,6 /* doubleword number */
325 sldi r6,r6,3 /* address offset */
327 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
333 23: ldarx r7,0,r6 /* if set, clear the bit */
337 li r6,128 /* and flush the TLB */
339 li r7,0x800 /* IS field = 0b10 */
347 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
350 /* Secondary threads wait for primary to have done partition switch */
351 20: lbz r0,VCORE_IN_GUEST(r5)
355 /* Set LPCR and RMOR. */
356 10: ld r8,KVM_LPCR(r9)
362 /* Check if HDEC expires soon */
365 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
369 /* Save purr/spurr */
372 std r5,HSTATE_PURR(r13)
373 std r6,HSTATE_SPURR(r13)
381 * PPC970 host -> guest partition switch code.
382 * We have to lock against concurrent tlbies,
383 * using native_tlbie_lock to lock against host tlbies
384 * and kvm->arch.tlbie_lock to lock against guest tlbies.
385 * We also have to invalidate the TLB since its
386 * entries aren't tagged with the LPID.
388 30: ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
390 /* first take native_tlbie_lock */
393 .tc native_tlbie_lock[TC],native_tlbie_lock
395 ld r3,toc_tlbie_lock@toc(2)
396 lwz r8,PACA_LOCK_TOKEN(r13)
404 ld r7,KVM_LPCR(r9) /* use kvm->arch.lpcr to store HID4 */
406 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
410 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
413 stw r0,0(r3) /* drop native_tlbie_lock */
415 /* invalidate the whole TLB */
424 /* Take the guest's tlbie_lock */
425 addi r3,r9,KVM_TLBIE_LOCK
433 mtspr SPRN_SDR1,r6 /* switch to partition page table */
435 /* Set up HID4 with the guest's LPID etc. */
440 /* drop the guest's tlbie_lock */
444 /* Check if HDEC expires soon */
447 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
451 /* Enable HDEC interrupts */
454 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
464 /* Load up guest SLB entries */
465 31: lwz r5,VCPU_SLB_MAX(r4)
470 1: ld r8,VCPU_SLB_E(r6)
473 addi r6,r6,VCPU_SLB_SIZE
477 /* Restore state of CTRL run bit; assume 1 on entry */
493 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
497 /* r11 = vcpu->arch.msr & ~MSR_HV */
498 rldicl r11, r11, 63 - MSR_HV_LG, 1
499 rotldi r11, r11, 1 + MSR_HV_LG
502 /* Check if we can deliver an external or decrementer interrupt now */
503 ld r0,VCPU_PENDING_EXC(r4)
504 lis r8,(1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h
514 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
516 li r0,BOOK3S_INTERRUPT_EXTERNAL
520 li r11,(MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
526 li r0,BOOK3S_INTERRUPT_DECREMENTER
529 /* Move SRR0 and SRR1 into the respective regs */
530 5: mtspr SPRN_SRR0, r6
535 stb r0,VCPU_CEDED(r4) /* cancel cede */
539 /* Activate guest mode, so faults get handled by KVM */
540 li r9, KVM_GUEST_MODE_GUEST
541 stb r9, HSTATE_IN_GUEST(r13)
548 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
555 ld r0, VCPU_GPR(R0)(r4)
556 ld r1, VCPU_GPR(R1)(r4)
557 ld r2, VCPU_GPR(R2)(r4)
558 ld r3, VCPU_GPR(R3)(r4)
559 ld r5, VCPU_GPR(R5)(r4)
560 ld r6, VCPU_GPR(R6)(r4)
561 ld r7, VCPU_GPR(R7)(r4)
562 ld r8, VCPU_GPR(R8)(r4)
563 ld r9, VCPU_GPR(R9)(r4)
564 ld r10, VCPU_GPR(R10)(r4)
565 ld r11, VCPU_GPR(R11)(r4)
566 ld r12, VCPU_GPR(R12)(r4)
567 ld r13, VCPU_GPR(R13)(r4)
569 ld r4, VCPU_GPR(R4)(r4)
574 /******************************************************************************
578 *****************************************************************************/
581 * We come here from the first-level interrupt handlers.
583 .globl kvmppc_interrupt
587 * R12 = interrupt vector
589 * guest CR, R12 saved in shadow VCPU SCRATCH1/0
590 * guest R13 saved in SPRN_SCRATCH0
592 /* abuse host_r2 as third scratch area; we get r2 from PACATOC(r13) */
593 std r9, HSTATE_HOST_R2(r13)
594 ld r9, HSTATE_KVM_VCPU(r13)
598 std r0, VCPU_GPR(R0)(r9)
599 std r1, VCPU_GPR(R1)(r9)
600 std r2, VCPU_GPR(R2)(r9)
601 std r3, VCPU_GPR(R3)(r9)
602 std r4, VCPU_GPR(R4)(r9)
603 std r5, VCPU_GPR(R5)(r9)
604 std r6, VCPU_GPR(R6)(r9)
605 std r7, VCPU_GPR(R7)(r9)
606 std r8, VCPU_GPR(R8)(r9)
607 ld r0, HSTATE_HOST_R2(r13)
608 std r0, VCPU_GPR(R9)(r9)
609 std r10, VCPU_GPR(R10)(r9)
610 std r11, VCPU_GPR(R11)(r9)
611 ld r3, HSTATE_SCRATCH0(r13)
612 lwz r4, HSTATE_SCRATCH1(r13)
613 std r3, VCPU_GPR(R12)(r9)
616 ld r3, HSTATE_CFAR(r13)
617 std r3, VCPU_CFAR(r9)
618 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
620 /* Restore R1/R2 so we can handle faults */
621 ld r1, HSTATE_HOST_R1(r13)
626 std r10, VCPU_SRR0(r9)
627 std r11, VCPU_SRR1(r9)
628 andi. r0, r12, 2 /* need to read HSRR0/1? */
630 mfspr r10, SPRN_HSRR0
631 mfspr r11, SPRN_HSRR1
633 1: std r10, VCPU_PC(r9)
634 std r11, VCPU_MSR(r9)
638 std r3, VCPU_GPR(R13)(r9)
641 /* Unset guest mode */
642 li r0, KVM_GUEST_MODE_NONE
643 stb r0, HSTATE_IN_GUEST(r13)
645 stw r12,VCPU_TRAP(r9)
647 /* Save HEIR (HV emulation assist reg) in last_inst
648 if this is an HEI (HV emulation interrupt, e40) */
649 li r3,KVM_INST_FETCH_FAILED
651 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
654 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
655 11: stw r3,VCPU_LAST_INST(r9)
657 /* these are volatile across C function calls */
664 /* If this is a page table miss then see if it's theirs or ours */
665 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
667 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
669 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
671 /* See if this is a leftover HDEC interrupt */
672 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
678 /* See if this is an hcall we can handle in real mode */
679 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
680 beq hcall_try_real_mode
682 /* Only handle external interrupts here on arch 206 and later */
684 b ext_interrupt_to_host
685 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
687 /* External interrupt ? */
688 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
689 bne+ ext_interrupt_to_host
691 /* External interrupt, first check for host_ipi. If this is
692 * set, we know the host wants us out so let's do it now
695 lbz r0, HSTATE_HOST_IPI(r13)
697 bne ext_interrupt_to_host
699 /* Now read the interrupt from the ICP */
700 ld r5, HSTATE_XICS_PHYS(r13)
703 beq- ext_interrupt_to_host
705 rlwinm. r0, r3, 0, 0xffffff
707 beq 3f /* if nothing pending in the ICP */
709 /* We found something in the ICP...
711 * If it's not an IPI, stash it in the PACA and return to
712 * the host, we don't (yet) handle directing real external
713 * interrupts directly to the guest
716 bne ext_stash_for_host
718 /* It's an IPI, clear the MFRR and EOI it */
721 stbcix r0, r5, r6 /* clear the IPI */
722 stwcix r3, r5, r7 /* EOI it */
725 /* We need to re-check host IPI now in case it got set in the
726 * meantime. If it's clear, we bounce the interrupt to the
729 lbz r0, HSTATE_HOST_IPI(r13)
733 /* Allright, looks like an IPI for the guest, we need to set MER */
735 /* Check if any CPU is heading out to the host, if so head out too */
736 ld r5, HSTATE_KVM_VCORE(r13)
737 lwz r0, VCORE_ENTRY_EXIT(r5)
739 bge ext_interrupt_to_host
741 /* See if there is a pending interrupt for the guest */
743 ld r0, VCPU_PENDING_EXC(r9)
744 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
745 rldicl. r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
746 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
749 /* And if the guest EE is set, we can deliver immediately, else
750 * we return to the guest with MER set
752 andi. r0, r11, MSR_EE
756 li r10, BOOK3S_INTERRUPT_EXTERNAL
757 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
763 /* We raced with the host, we need to resend that IPI, bummer */
764 1: li r0, IPI_PRIORITY
765 stbcix r0, r5, r6 /* set the IPI */
767 b ext_interrupt_to_host
770 /* It's not an IPI and it's for the host, stash it in the PACA
771 * before exit, it will be picked up by the host ICP driver
773 stw r3, HSTATE_SAVED_XIRR(r13)
774 ext_interrupt_to_host:
776 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
782 std r5,VCPU_DEC_EXPIRES(r9)
784 /* Save more register state */
788 stw r7, VCPU_DSISR(r9)
790 /* don't overwrite fault_dar/fault_dsisr if HDSI */
791 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
793 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
794 std r6, VCPU_FAULT_DAR(r9)
795 stw r7, VCPU_FAULT_DSISR(r9)
797 /* See if it is a machine check */
798 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
799 beq machine_check_realmode
802 /* Save guest CTRL register, set runlatch to 1 */
803 6: mfspr r6,SPRN_CTRLF
810 /* Read the guest SLB and save it away */
811 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
817 andis. r0,r8,SLB_ESID_V@h
819 add r8,r8,r6 /* put index in */
821 std r8,VCPU_SLB_E(r7)
822 std r3,VCPU_SLB_V(r7)
823 addi r7,r7,VCPU_SLB_SIZE
827 stw r5,VCPU_SLB_MAX(r9)
830 * Save the guest PURR/SPURR
838 std r6,VCPU_SPURR(r9)
843 * Restore host PURR/SPURR and add guest times
844 * so that the time in the guest gets accounted.
846 ld r3,HSTATE_PURR(r13)
847 ld r4,HSTATE_SPURR(r13)
852 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
860 hdec_soon: /* r9 = vcpu, r12 = trap, r13 = paca */
863 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
865 * POWER7 guest -> host partition switch code.
866 * We don't have to lock against tlbies but we do
867 * have to coordinate the hardware threads.
869 /* Increment the threads-exiting-guest count in the 0xff00
870 bits of vcore->entry_exit_count */
872 ld r5,HSTATE_KVM_VCORE(r13)
873 addi r6,r5,VCORE_ENTRY_EXIT
881 * At this point we have an interrupt that we have to pass
882 * up to the kernel or qemu; we can't handle it in real mode.
883 * Thus we have to do a partition switch, so we have to
884 * collect the other threads, if we are the first thread
885 * to take an interrupt. To do this, we set the HDEC to 0,
886 * which causes an HDEC interrupt in all threads within 2ns
887 * because the HDEC register is shared between all 4 threads.
888 * However, we don't need to bother if this is an HDEC
889 * interrupt, since the other threads will already be on their
890 * way here in that case.
892 cmpwi r3,0x100 /* Are we the first here? */
894 cmpwi r3,1 /* Are any other threads in the guest? */
896 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
902 * Send an IPI to any napping threads, since an HDEC interrupt
903 * doesn't wake CPUs up from nap.
905 lwz r3,VCORE_NAPPING_THREADS(r5)
909 andc. r3,r3,r0 /* no sense IPI'ing ourselves */
911 mulli r4,r4,PACA_SIZE /* get paca for thread 0 */
915 ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */
918 stbcix r0,r7,r8 /* trigger the IPI */
923 /* Secondary threads wait for primary to do partition switch */
924 43: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
925 ld r5,HSTATE_KVM_VCORE(r13)
930 13: lbz r3,VCORE_IN_GUEST(r5)
936 /* Primary thread waits for all the secondaries to exit guest */
937 15: lwz r3,VCORE_ENTRY_EXIT(r5)
944 /* Primary thread switches back to host partition */
945 ld r6,KVM_HOST_SDR1(r4)
946 lwz r7,KVM_HOST_LPID(r4)
947 li r8,LPID_RSVD /* switch to reserved LPID */
950 mtspr SPRN_SDR1,r6 /* switch to partition page table */
954 stb r0,VCORE_IN_GUEST(r5)
955 lis r8,0x7fff /* MAX_INT@h */
958 16: ld r8,KVM_HOST_LPCR(r4)
964 * PPC970 guest -> host partition switch code.
965 * We have to lock against concurrent tlbies, and
966 * we have to flush the whole TLB.
968 32: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
970 /* Take the guest's tlbie_lock */
971 lwz r8,PACA_LOCK_TOKEN(r13)
972 addi r3,r4,KVM_TLBIE_LOCK
980 ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */
982 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
986 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
989 stw r0,0(r3) /* drop guest tlbie_lock */
991 /* invalidate the whole TLB */
1000 /* take native_tlbie_lock */
1001 ld r3,toc_tlbie_lock@toc(2)
1009 ld r6,KVM_HOST_SDR1(r4)
1010 mtspr SPRN_SDR1,r6 /* switch to host page table */
1012 /* Set up host HID4 value */
1017 stw r0,0(r3) /* drop native_tlbie_lock */
1019 lis r8,0x7fff /* MAX_INT@h */
1022 /* Disable HDEC interrupts */
1025 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
1035 /* load host SLB entries */
1036 33: ld r8,PACA_SLBSHADOWPTR(r13)
1038 .rept SLB_NUM_BOLTED
1039 ld r5,SLBSHADOW_SAVEAREA(r8)
1040 ld r6,SLBSHADOW_SAVEAREA+8(r8)
1041 andis. r7,r5,SLB_ESID_V@h
1047 /* Save and reset AMR and UAMOR before turning on the MMU */
1052 std r6,VCPU_UAMOR(r9)
1055 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1057 /* Switch DSCR back to host value */
1060 ld r7, HSTATE_DSCR(r13)
1061 std r8, VCPU_DSCR(r7)
1063 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1065 /* Save non-volatile GPRs */
1066 std r14, VCPU_GPR(R14)(r9)
1067 std r15, VCPU_GPR(R15)(r9)
1068 std r16, VCPU_GPR(R16)(r9)
1069 std r17, VCPU_GPR(R17)(r9)
1070 std r18, VCPU_GPR(R18)(r9)
1071 std r19, VCPU_GPR(R19)(r9)
1072 std r20, VCPU_GPR(R20)(r9)
1073 std r21, VCPU_GPR(R21)(r9)
1074 std r22, VCPU_GPR(R22)(r9)
1075 std r23, VCPU_GPR(R23)(r9)
1076 std r24, VCPU_GPR(R24)(r9)
1077 std r25, VCPU_GPR(R25)(r9)
1078 std r26, VCPU_GPR(R26)(r9)
1079 std r27, VCPU_GPR(R27)(r9)
1080 std r28, VCPU_GPR(R28)(r9)
1081 std r29, VCPU_GPR(R29)(r9)
1082 std r30, VCPU_GPR(R30)(r9)
1083 std r31, VCPU_GPR(R31)(r9)
1086 mfspr r3, SPRN_SPRG0
1087 mfspr r4, SPRN_SPRG1
1088 mfspr r5, SPRN_SPRG2
1089 mfspr r6, SPRN_SPRG3
1090 std r3, VCPU_SPRG0(r9)
1091 std r4, VCPU_SPRG1(r9)
1092 std r5, VCPU_SPRG2(r9)
1093 std r6, VCPU_SPRG3(r9)
1099 /* Increment yield count if they have a VPA */
1100 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1103 lwz r3, LPPACA_YIELDCOUNT(r8)
1105 stw r3, LPPACA_YIELDCOUNT(r8)
1107 stb r3, VCPU_VPA_DIRTY(r9)
1109 /* Save PMU registers if requested */
1110 /* r8 and cr0.eq are live here */
1112 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1113 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1114 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1115 mfspr r6, SPRN_MMCRA
1117 /* On P7, clear MMCRA in order to disable SDAR updates */
1119 mtspr SPRN_MMCRA, r7
1120 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1122 beq 21f /* if no VPA, save PMU stuff anyway */
1123 lbz r7, LPPACA_PMCINUSE(r8)
1124 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1126 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1128 21: mfspr r5, SPRN_MMCR1
1129 std r4, VCPU_MMCR(r9)
1130 std r5, VCPU_MMCR + 8(r9)
1131 std r6, VCPU_MMCR + 16(r9)
1139 mfspr r10, SPRN_PMC7
1140 mfspr r11, SPRN_PMC8
1141 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1142 stw r3, VCPU_PMC(r9)
1143 stw r4, VCPU_PMC + 4(r9)
1144 stw r5, VCPU_PMC + 8(r9)
1145 stw r6, VCPU_PMC + 12(r9)
1146 stw r7, VCPU_PMC + 16(r9)
1147 stw r8, VCPU_PMC + 20(r9)
1149 stw r10, VCPU_PMC + 24(r9)
1150 stw r11, VCPU_PMC + 28(r9)
1151 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1154 /* Secondary threads go off to take a nap on POWER7 */
1156 lwz r0,VCPU_PTID(r9)
1159 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1161 /* Restore host DABR and DABRX */
1162 ld r5,HSTATE_DABR(r13)
1168 ld r3,PACA_SPRG3(r13)
1172 * Reload DEC. HDEC interrupts were disabled when
1173 * we reloaded the host's LPCR value.
1175 ld r3, HSTATE_DECEXP(r13)
1180 /* Reload the host's PMU registers */
1181 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
1182 lbz r4, LPPACA_PMCINUSE(r3)
1184 beq 23f /* skip if not */
1185 lwz r3, HSTATE_PMC(r13)
1186 lwz r4, HSTATE_PMC + 4(r13)
1187 lwz r5, HSTATE_PMC + 8(r13)
1188 lwz r6, HSTATE_PMC + 12(r13)
1189 lwz r8, HSTATE_PMC + 16(r13)
1190 lwz r9, HSTATE_PMC + 20(r13)
1192 lwz r10, HSTATE_PMC + 24(r13)
1193 lwz r11, HSTATE_PMC + 28(r13)
1194 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1202 mtspr SPRN_PMC7, r10
1203 mtspr SPRN_PMC8, r11
1204 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1205 ld r3, HSTATE_MMCR(r13)
1206 ld r4, HSTATE_MMCR + 8(r13)
1207 ld r5, HSTATE_MMCR + 16(r13)
1208 mtspr SPRN_MMCR1, r4
1209 mtspr SPRN_MMCRA, r5
1210 mtspr SPRN_MMCR0, r3
1214 * For external and machine check interrupts, we need
1215 * to call the Linux handler to process the interrupt.
1216 * We do that by jumping to absolute address 0x500 for
1217 * external interrupts, or the machine_check_fwnmi label
1218 * for machine checks (since firmware might have patched
1219 * the vector area at 0x200). The [h]rfid at the end of the
1220 * handler will return to the book3s_hv_interrupts.S code.
1221 * For other interrupts we do the rfid to get back
1222 * to the book3s_hv_interrupts.S code here.
1224 ld r8, HSTATE_VMHANDLER(r13)
1225 ld r7, HSTATE_HOST_MSR(r13)
1227 cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1228 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1231 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1233 /* RFI into the highmem handler, or branch to interrupt handler */
1237 mtmsrd r6, 1 /* Clear RI in MSR */
1240 beqa 0x500 /* external interrupt (PPC970) */
1241 beq cr1, 13f /* machine check */
1244 /* On POWER7, we have external interrupts set to use HSRR0/1 */
1245 11: mtspr SPRN_HSRR0, r8
1246 mtspr SPRN_HSRR1, r7
1249 13: b machine_check_fwnmi
1252 * Check whether an HDSI is an HPTE not found fault or something else.
1253 * If it is an HPTE not found fault that is due to the guest accessing
1254 * a page that they have mapped but which we have paged out, then
1255 * we continue on with the guest exit path. In all other cases,
1256 * reflect the HDSI to the guest as a DSI.
1260 mfspr r6, SPRN_HDSISR
1261 /* HPTE not found fault or protection fault? */
1262 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1263 beq 1f /* if not, send it to the guest */
1264 andi. r0, r11, MSR_DR /* data relocation enabled? */
1267 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1268 bne 1f /* if no SLB entry found */
1269 4: std r4, VCPU_FAULT_DAR(r9)
1270 stw r6, VCPU_FAULT_DSISR(r9)
1272 /* Search the hash table. */
1273 mr r3, r9 /* vcpu pointer */
1274 li r7, 1 /* data fault */
1275 bl .kvmppc_hpte_hv_fault
1276 ld r9, HSTATE_KVM_VCPU(r13)
1278 ld r11, VCPU_MSR(r9)
1279 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1280 cmpdi r3, 0 /* retry the instruction */
1282 cmpdi r3, -1 /* handle in kernel mode */
1284 cmpdi r3, -2 /* MMIO emulation; need instr word */
1287 /* Synthesize a DSI for the guest */
1288 ld r4, VCPU_FAULT_DAR(r9)
1290 1: mtspr SPRN_DAR, r4
1291 mtspr SPRN_DSISR, r6
1292 mtspr SPRN_SRR0, r10
1293 mtspr SPRN_SRR1, r11
1294 li r10, BOOK3S_INTERRUPT_DATA_STORAGE
1295 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1297 fast_interrupt_c_return:
1298 6: ld r7, VCPU_CTR(r9)
1299 lwz r8, VCPU_XER(r9)
1305 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1306 ld r5, KVM_VRMA_SLB_V(r5)
1309 /* If this is for emulated MMIO, load the instruction word */
1310 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1312 /* Set guest mode to 'jump over instruction' so if lwz faults
1313 * we'll just continue at the next IP. */
1314 li r0, KVM_GUEST_MODE_SKIP
1315 stb r0, HSTATE_IN_GUEST(r13)
1317 /* Do the access with MSR:DR enabled */
1319 ori r4, r3, MSR_DR /* Enable paging for data */
1324 /* Store the result */
1325 stw r8, VCPU_LAST_INST(r9)
1327 /* Unset guest mode. */
1328 li r0, KVM_GUEST_MODE_NONE
1329 stb r0, HSTATE_IN_GUEST(r13)
1333 * Similarly for an HISI, reflect it to the guest as an ISI unless
1334 * it is an HPTE not found fault for a page that we have paged out.
1337 andis. r0, r11, SRR1_ISI_NOPT@h
1339 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1342 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1343 bne 1f /* if no SLB entry found */
1345 /* Search the hash table. */
1346 mr r3, r9 /* vcpu pointer */
1349 li r7, 0 /* instruction fault */
1350 bl .kvmppc_hpte_hv_fault
1351 ld r9, HSTATE_KVM_VCPU(r13)
1353 ld r11, VCPU_MSR(r9)
1354 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1355 cmpdi r3, 0 /* retry the instruction */
1356 beq fast_interrupt_c_return
1357 cmpdi r3, -1 /* handle in kernel mode */
1360 /* Synthesize an ISI for the guest */
1362 1: mtspr SPRN_SRR0, r10
1363 mtspr SPRN_SRR1, r11
1364 li r10, BOOK3S_INTERRUPT_INST_STORAGE
1365 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1367 b fast_interrupt_c_return
1369 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1370 ld r5, KVM_VRMA_SLB_V(r6)
1374 * Try to handle an hcall in real mode.
1375 * Returns to the guest if we handle it, or continues on up to
1376 * the kernel if we can't (i.e. if we don't have a handler for
1377 * it, or if the handler returns H_TOO_HARD).
1379 .globl hcall_try_real_mode
1380 hcall_try_real_mode:
1381 ld r3,VCPU_GPR(R3)(r9)
1385 cmpldi r3,hcall_real_table_end - hcall_real_table
1387 LOAD_REG_ADDR(r4, hcall_real_table)
1393 mr r3,r9 /* get vcpu pointer */
1394 ld r4,VCPU_GPR(R4)(r9)
1397 beq hcall_real_fallback
1398 ld r4,HSTATE_KVM_VCPU(r13)
1399 std r3,VCPU_GPR(R3)(r4)
1404 /* We've attempted a real mode hcall, but it's punted it back
1405 * to userspace. We need to restore some clobbered volatiles
1406 * before resuming the pass-it-to-qemu path */
1407 hcall_real_fallback:
1408 li r12,BOOK3S_INTERRUPT_SYSCALL
1409 ld r9, HSTATE_KVM_VCPU(r13)
1413 .globl hcall_real_table
1415 .long 0 /* 0 - unused */
1416 .long .kvmppc_h_remove - hcall_real_table
1417 .long .kvmppc_h_enter - hcall_real_table
1418 .long .kvmppc_h_read - hcall_real_table
1419 .long 0 /* 0x10 - H_CLEAR_MOD */
1420 .long 0 /* 0x14 - H_CLEAR_REF */
1421 .long .kvmppc_h_protect - hcall_real_table
1422 .long 0 /* 0x1c - H_GET_TCE */
1423 .long .kvmppc_h_put_tce - hcall_real_table
1424 .long 0 /* 0x24 - H_SET_SPRG0 */
1425 .long .kvmppc_h_set_dabr - hcall_real_table
1440 #ifdef CONFIG_KVM_XICS
1441 .long .kvmppc_rm_h_eoi - hcall_real_table
1442 .long .kvmppc_rm_h_cppr - hcall_real_table
1443 .long .kvmppc_rm_h_ipi - hcall_real_table
1444 .long 0 /* 0x70 - H_IPOLL */
1445 .long .kvmppc_rm_h_xirr - hcall_real_table
1447 .long 0 /* 0x64 - H_EOI */
1448 .long 0 /* 0x68 - H_CPPR */
1449 .long 0 /* 0x6c - H_IPI */
1450 .long 0 /* 0x70 - H_IPOLL */
1451 .long 0 /* 0x74 - H_XIRR */
1479 .long .kvmppc_h_cede - hcall_real_table
1496 .long .kvmppc_h_bulk_remove - hcall_real_table
1497 hcall_real_table_end:
1503 _GLOBAL(kvmppc_h_set_dabr)
1504 std r4,VCPU_DABR(r3)
1505 /* Work around P7 bug where DABR can get corrupted on mtspr */
1506 1: mtspr SPRN_DABR,r4
1514 _GLOBAL(kvmppc_h_cede)
1516 std r11,VCPU_MSR(r3)
1518 stb r0,VCPU_CEDED(r3)
1519 sync /* order setting ceded vs. testing prodded */
1520 lbz r5,VCPU_PRODDED(r3)
1522 bne kvm_cede_prodded
1523 li r0,0 /* set trap to 0 to say hcall is handled */
1524 stw r0,VCPU_TRAP(r3)
1526 std r0,VCPU_GPR(R3)(r3)
1528 b kvm_cede_exit /* just send it up to host on 970 */
1529 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
1532 * Set our bit in the bitmask of napping threads unless all the
1533 * other threads are already napping, in which case we send this
1536 ld r5,HSTATE_KVM_VCORE(r13)
1537 lwz r6,VCPU_PTID(r3)
1538 lwz r8,VCORE_ENTRY_EXIT(r5)
1542 addi r6,r5,VCORE_NAPPING_THREADS
1551 stb r0,HSTATE_NAPPING(r13)
1552 /* order napping_threads update vs testing entry_exit_count */
1555 lwz r7,VCORE_ENTRY_EXIT(r5)
1557 bge 33f /* another thread already exiting */
1560 * Although not specifically required by the architecture, POWER7
1561 * preserves the following registers in nap mode, even if an SMT mode
1562 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
1563 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
1565 /* Save non-volatile GPRs */
1566 std r14, VCPU_GPR(R14)(r3)
1567 std r15, VCPU_GPR(R15)(r3)
1568 std r16, VCPU_GPR(R16)(r3)
1569 std r17, VCPU_GPR(R17)(r3)
1570 std r18, VCPU_GPR(R18)(r3)
1571 std r19, VCPU_GPR(R19)(r3)
1572 std r20, VCPU_GPR(R20)(r3)
1573 std r21, VCPU_GPR(R21)(r3)
1574 std r22, VCPU_GPR(R22)(r3)
1575 std r23, VCPU_GPR(R23)(r3)
1576 std r24, VCPU_GPR(R24)(r3)
1577 std r25, VCPU_GPR(R25)(r3)
1578 std r26, VCPU_GPR(R26)(r3)
1579 std r27, VCPU_GPR(R27)(r3)
1580 std r28, VCPU_GPR(R28)(r3)
1581 std r29, VCPU_GPR(R29)(r3)
1582 std r30, VCPU_GPR(R30)(r3)
1583 std r31, VCPU_GPR(R31)(r3)
1589 * Take a nap until a decrementer or external interrupt occurs,
1590 * with PECE1 (wake on decr) and PECE0 (wake on external) set in LPCR
1593 stb r0,HSTATE_HWTHREAD_REQ(r13)
1595 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
1599 std r0, HSTATE_SCRATCH0(r13)
1601 ld r0, HSTATE_SCRATCH0(r13)
1608 /* get vcpu pointer */
1609 ld r4, HSTATE_KVM_VCPU(r13)
1611 /* Woken by external or decrementer interrupt */
1612 ld r1, HSTATE_HOST_R1(r13)
1614 /* load up FP state */
1618 ld r14, VCPU_GPR(R14)(r4)
1619 ld r15, VCPU_GPR(R15)(r4)
1620 ld r16, VCPU_GPR(R16)(r4)
1621 ld r17, VCPU_GPR(R17)(r4)
1622 ld r18, VCPU_GPR(R18)(r4)
1623 ld r19, VCPU_GPR(R19)(r4)
1624 ld r20, VCPU_GPR(R20)(r4)
1625 ld r21, VCPU_GPR(R21)(r4)
1626 ld r22, VCPU_GPR(R22)(r4)
1627 ld r23, VCPU_GPR(R23)(r4)
1628 ld r24, VCPU_GPR(R24)(r4)
1629 ld r25, VCPU_GPR(R25)(r4)
1630 ld r26, VCPU_GPR(R26)(r4)
1631 ld r27, VCPU_GPR(R27)(r4)
1632 ld r28, VCPU_GPR(R28)(r4)
1633 ld r29, VCPU_GPR(R29)(r4)
1634 ld r30, VCPU_GPR(R30)(r4)
1635 ld r31, VCPU_GPR(R31)(r4)
1637 /* clear our bit in vcore->napping_threads */
1638 33: ld r5,HSTATE_KVM_VCORE(r13)
1639 lwz r3,VCPU_PTID(r4)
1642 addi r6,r5,VCORE_NAPPING_THREADS
1648 stb r0,HSTATE_NAPPING(r13)
1650 /* Check the wake reason in SRR1 to see why we got here */
1652 rlwinm r3, r3, 44-31, 0x7 /* extract wake reason field */
1653 cmpwi r3, 4 /* was it an external interrupt? */
1654 li r12, BOOK3S_INTERRUPT_EXTERNAL
1657 ld r11, VCPU_MSR(r9)
1658 beq do_ext_interrupt /* if so */
1660 /* see if any other thread is already exiting */
1661 lwz r0,VCORE_ENTRY_EXIT(r5)
1663 blt kvmppc_cede_reentry /* if not go back to guest */
1665 /* some threads are exiting, so go to the guest exit path */
1666 b hcall_real_fallback
1668 /* cede when already previously prodded case */
1671 stb r0,VCPU_PRODDED(r3)
1672 sync /* order testing prodded vs. clearing ceded */
1673 stb r0,VCPU_CEDED(r3)
1677 /* we've ceded but we want to give control to the host */
1679 b hcall_real_fallback
1681 /* Try to handle a machine check in real mode */
1682 machine_check_realmode:
1683 mr r3, r9 /* get vcpu pointer */
1684 bl .kvmppc_realmode_machine_check
1686 cmpdi r3, 0 /* continue exiting from guest? */
1687 ld r9, HSTATE_KVM_VCPU(r13)
1688 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1690 /* If not, deliver a machine check. SRR0/1 are already set */
1691 li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
1692 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1694 b fast_interrupt_c_return
1697 ld r5,HSTATE_KVM_VCORE(r13)
1699 13: lbz r3,VCORE_IN_GUEST(r5)
1703 ld r11,PACA_SLBSHADOWPTR(r13)
1705 .rept SLB_NUM_BOLTED
1706 ld r5,SLBSHADOW_SAVEAREA(r11)
1707 ld r6,SLBSHADOW_SAVEAREA+8(r11)
1708 andis. r7,r5,SLB_ESID_V@h
1715 /* Clear our vcpu pointer so we don't come back in early */
1717 std r0, HSTATE_KVM_VCPU(r13)
1719 /* Clear any pending IPI - assume we're a secondary thread */
1720 ld r5, HSTATE_XICS_PHYS(r13)
1722 lwzcix r3, r5, r7 /* ack any pending interrupt */
1723 rlwinm. r0, r3, 0, 0xffffff /* any pending? */
1728 stbcix r0, r5, r6 /* clear the IPI */
1729 stwcix r3, r5, r7 /* EOI it */
1732 /* increment the nap count and then go to nap mode */
1733 ld r4, HSTATE_KVM_VCORE(r13)
1734 addi r4, r4, VCORE_NAP_COUNT
1735 lwsync /* make previous updates visible */
1742 li r0, KVM_HWTHREAD_IN_NAP
1743 stb r0, HSTATE_HWTHREAD_STATE(r13)
1747 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
1750 std r0, HSTATE_SCRATCH0(r13)
1752 ld r0, HSTATE_SCRATCH0(r13)
1759 * Save away FP, VMX and VSX registers.
1762 _GLOBAL(kvmppc_save_fp)
1765 #ifdef CONFIG_ALTIVEC
1767 oris r8,r8,MSR_VEC@h
1768 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1772 oris r8,r8,MSR_VSX@h
1773 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1781 li r6,reg*16+VCPU_VSRS
1789 stfd reg,reg*8+VCPU_FPRS(r3)
1793 ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
1796 stfd fr0,VCPU_FPSCR(r3)
1798 #ifdef CONFIG_ALTIVEC
1802 li r6,reg*16+VCPU_VRS
1809 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1811 mfspr r6,SPRN_VRSAVE
1812 stw r6,VCPU_VRSAVE(r3)
1818 * Load up FP, VMX and VSX registers
1821 .globl kvmppc_load_fp
1825 #ifdef CONFIG_ALTIVEC
1827 oris r8,r8,MSR_VEC@h
1828 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1832 oris r8,r8,MSR_VSX@h
1833 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1837 lfd fr0,VCPU_FPSCR(r4)
1843 li r7,reg*16+VCPU_VSRS
1851 lfd reg,reg*8+VCPU_FPRS(r4)
1855 ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
1858 #ifdef CONFIG_ALTIVEC
1865 li r7,reg*16+VCPU_VRS
1869 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1871 lwz r7,VCPU_VRSAVE(r4)
1872 mtspr SPRN_VRSAVE,r7