2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/book3s/64/mmu-hash.h>
34 #define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM)
36 /* Values in HSTATE_NAPPING(r13) */
37 #define NAPPING_CEDE 1
38 #define NAPPING_NOVCPU 2
41 * Call kvmppc_hv_entry in real mode.
42 * Must be called with interrupts hard-disabled.
46 * LR = return address to continue at after eventually re-enabling MMU
48 _GLOBAL_TOC(kvmppc_hv_entry_trampoline)
50 std r0, PPC_LR_STKOFF(r1)
53 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
58 mtmsrd r0,1 /* clear RI in MSR */
64 ld r4, HSTATE_KVM_VCPU(r13)
67 /* Back from guest - restore host state and return to caller */
70 /* Restore host DABR and DABRX */
71 ld r5,HSTATE_DABR(r13)
75 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
78 ld r3,PACA_SPRG_VDSO(r13)
79 mtspr SPRN_SPRG_VDSO_WRITE,r3
81 /* Reload the host's PMU registers */
82 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
83 lbz r4, LPPACA_PMCINUSE(r3)
85 beq 23f /* skip if not */
87 ld r3, HSTATE_MMCR0(r13)
88 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
91 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
92 lwz r3, HSTATE_PMC1(r13)
93 lwz r4, HSTATE_PMC2(r13)
94 lwz r5, HSTATE_PMC3(r13)
95 lwz r6, HSTATE_PMC4(r13)
96 lwz r8, HSTATE_PMC5(r13)
97 lwz r9, HSTATE_PMC6(r13)
104 ld r3, HSTATE_MMCR0(r13)
105 ld r4, HSTATE_MMCR1(r13)
106 ld r5, HSTATE_MMCRA(r13)
107 ld r6, HSTATE_SIAR(r13)
108 ld r7, HSTATE_SDAR(r13)
114 ld r8, HSTATE_MMCR2(r13)
115 ld r9, HSTATE_SIER(r13)
118 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
124 * Reload DEC. HDEC interrupts were disabled when
125 * we reloaded the host's LPCR value.
127 ld r3, HSTATE_DECEXP(r13)
132 /* hwthread_req may have got set by cede or no vcpu, so clear it */
134 stb r0, HSTATE_HWTHREAD_REQ(r13)
137 * For external and machine check interrupts, we need
138 * to call the Linux handler to process the interrupt.
139 * We do that by jumping to absolute address 0x500 for
140 * external interrupts, or the machine_check_fwnmi label
141 * for machine checks (since firmware might have patched
142 * the vector area at 0x200). The [h]rfid at the end of the
143 * handler will return to the book3s_hv_interrupts.S code.
144 * For other interrupts we do the rfid to get back
145 * to the book3s_hv_interrupts.S code here.
147 ld r8, 112+PPC_LR_STKOFF(r1)
149 ld r7, HSTATE_HOST_MSR(r13)
151 cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK
152 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
154 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
155 beq 15f /* Invoke the H_DOORBELL handler */
156 cmpwi cr2, r12, BOOK3S_INTERRUPT_HMI
157 beq cr2, 14f /* HMI check */
159 /* RFI into the highmem handler, or branch to interrupt handler */
163 mtmsrd r6, 1 /* Clear RI in MSR */
166 beq cr1, 13f /* machine check */
169 /* On POWER7, we have external interrupts set to use HSRR0/1 */
170 11: mtspr SPRN_HSRR0, r8
174 13: b machine_check_fwnmi
176 14: mtspr SPRN_HSRR0, r8
178 b hmi_exception_after_realmode
180 15: mtspr SPRN_HSRR0, r8
184 kvmppc_primary_no_guest:
185 /* We handle this much like a ceded vcpu */
186 /* put the HDEC into the DEC, since HDEC interrupts don't wake us */
190 * Make sure the primary has finished the MMU switch.
191 * We should never get here on a secondary thread, but
192 * check it for robustness' sake.
194 ld r5, HSTATE_KVM_VCORE(r13)
195 65: lbz r0, VCORE_IN_GUEST(r5)
202 /* set our bit in napping_threads */
203 ld r5, HSTATE_KVM_VCORE(r13)
204 lbz r7, HSTATE_PTID(r13)
207 addi r6, r5, VCORE_NAPPING_THREADS
212 /* order napping_threads update vs testing entry_exit_map */
215 lwz r7, VCORE_ENTRY_EXIT(r5)
217 bge kvm_novcpu_exit /* another thread already exiting */
218 li r3, NAPPING_NOVCPU
219 stb r3, HSTATE_NAPPING(r13)
221 li r3, 0 /* Don't wake on privileged (OS) doorbell */
226 * Entered from kvm_start_guest if kvm_hstate.napping is set
232 ld r1, HSTATE_HOST_R1(r13)
233 ld r5, HSTATE_KVM_VCORE(r13)
235 stb r0, HSTATE_NAPPING(r13)
237 /* check the wake reason */
238 bl kvmppc_check_wake_reason
241 * Restore volatile registers since we could have called
242 * a C routine in kvmppc_check_wake_reason.
245 ld r5, HSTATE_KVM_VCORE(r13)
247 /* see if any other thread is already exiting */
248 lwz r0, VCORE_ENTRY_EXIT(r5)
252 /* clear our bit in napping_threads */
253 lbz r7, HSTATE_PTID(r13)
256 addi r6, r5, VCORE_NAPPING_THREADS
262 /* See if the wake reason means we need to exit */
266 /* See if our timeslice has expired (HDEC is negative) */
268 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
272 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
273 ld r4, HSTATE_KVM_VCPU(r13)
275 beq kvmppc_primary_no_guest
277 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
278 addi r3, r4, VCPU_TB_RMENTRY
279 bl kvmhv_start_timing
284 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
285 ld r4, HSTATE_KVM_VCPU(r13)
288 addi r3, r4, VCPU_TB_RMEXIT
289 bl kvmhv_accumulate_time
293 bl kvmhv_commence_exit
296 b kvmhv_switch_to_host
299 * We come in here when wakened from nap mode.
300 * Relocation is off and most register values are lost.
301 * r13 points to the PACA.
303 .globl kvm_start_guest
306 /* Set runlatch bit the minute you wake up from nap */
313 li r0,KVM_HWTHREAD_IN_KVM
314 stb r0,HSTATE_HWTHREAD_STATE(r13)
316 /* NV GPR values from power7_idle() will no longer be valid */
318 stb r0,PACA_NAPSTATELOST(r13)
320 /* were we napping due to cede? */
321 lbz r0,HSTATE_NAPPING(r13)
322 cmpwi r0,NAPPING_CEDE
324 cmpwi r0,NAPPING_NOVCPU
325 beq kvm_novcpu_wakeup
327 ld r1,PACAEMERGSP(r13)
328 subi r1,r1,STACK_FRAME_OVERHEAD
331 * We weren't napping due to cede, so this must be a secondary
332 * thread being woken up to run a guest, or being woken up due
333 * to a stray IPI. (Or due to some machine check or hypervisor
334 * maintenance interrupt while the core is in KVM.)
337 /* Check the wake reason in SRR1 to see why we got here */
338 bl kvmppc_check_wake_reason
340 * kvmppc_check_wake_reason could invoke a C routine, but we
341 * have no volatile registers to restore when we return.
347 /* get vcore pointer, NULL if we have nothing to run */
348 ld r5,HSTATE_KVM_VCORE(r13)
350 /* if we have no vcore to run, go back to sleep */
353 kvm_secondary_got_guest:
355 /* Set HSTATE_DSCR(r13) to something sensible */
356 ld r6, PACA_DSCR_DEFAULT(r13)
357 std r6, HSTATE_DSCR(r13)
359 /* On thread 0 of a subcore, set HDEC to max */
360 lbz r4, HSTATE_PTID(r13)
366 /* and set per-LPAR registers, if doing dynamic micro-threading */
367 ld r6, HSTATE_SPLIT_MODE(r13)
370 ld r0, KVM_SPLIT_RPR(r6)
372 ld r0, KVM_SPLIT_PMMAR(r6)
374 ld r0, KVM_SPLIT_LDBAR(r6)
378 /* Order load of vcpu after load of vcore */
380 ld r4, HSTATE_KVM_VCPU(r13)
383 /* Back from the guest, go back to nap */
384 /* Clear our vcpu and vcore pointers so we don't come back in early */
386 std r0, HSTATE_KVM_VCPU(r13)
388 * Once we clear HSTATE_KVM_VCORE(r13), the code in
389 * kvmppc_run_core() is going to assume that all our vcpu
390 * state is visible in memory. This lwsync makes sure
394 std r0, HSTATE_KVM_VCORE(r13)
397 * All secondaries exiting guest will fall through this path.
398 * Before proceeding, just check for HMI interrupt and
399 * invoke opal hmi handler. By now we are sure that the
400 * primary thread on this core/subcore has already made partition
401 * switch/TB resync and we are good to call opal hmi handler.
403 cmpwi r12, BOOK3S_INTERRUPT_HMI
406 li r3,0 /* NULL argument */
407 bl hmi_exception_realmode
409 * At this point we have finished executing in the guest.
410 * We need to wait for hwthread_req to become zero, since
411 * we may not turn on the MMU while hwthread_req is non-zero.
412 * While waiting we also need to check if we get given a vcpu to run.
415 lbz r3, HSTATE_HWTHREAD_REQ(r13)
419 li r0, KVM_HWTHREAD_IN_KERNEL
420 stb r0, HSTATE_HWTHREAD_STATE(r13)
421 /* need to recheck hwthread_req after a barrier, to avoid race */
423 lbz r3, HSTATE_HWTHREAD_REQ(r13)
427 * We jump to pnv_wakeup_loss, which will return to the caller
428 * of power7_nap in the powernv cpu offline loop. The value we
429 * put in r3 becomes the return value for power7_nap.
433 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
439 ld r5, HSTATE_KVM_VCORE(r13)
442 ld r3, HSTATE_SPLIT_MODE(r13)
445 lbz r0, KVM_SPLIT_DO_NAP(r3)
451 b kvm_secondary_got_guest
453 54: li r0, KVM_HWTHREAD_IN_KVM
454 stb r0, HSTATE_HWTHREAD_STATE(r13)
458 * Here the primary thread is trying to return the core to
459 * whole-core mode, so we need to nap.
463 * When secondaries are napping in kvm_unsplit_nap() with
464 * hwthread_req = 1, HMI goes ignored even though subcores are
465 * already exited the guest. Hence HMI keeps waking up secondaries
466 * from nap in a loop and secondaries always go back to nap since
467 * no vcore is assigned to them. This makes impossible for primary
468 * thread to get hold of secondary threads resulting into a soft
469 * lockup in KVM path.
471 * Let us check if HMI is pending and handle it before we go to nap.
473 cmpwi r12, BOOK3S_INTERRUPT_HMI
475 li r3, 0 /* NULL argument */
476 bl hmi_exception_realmode
479 * Ensure that secondary doesn't nap when it has
480 * its vcore pointer set.
482 sync /* matches smp_mb() before setting split_info.do_nap */
483 ld r0, HSTATE_KVM_VCORE(r13)
486 /* clear any pending message */
488 lis r6, (PPC_DBELL_SERVER << (63-36))@h
490 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
491 /* Set kvm_split_mode.napped[tid] = 1 */
492 ld r3, HSTATE_SPLIT_MODE(r13)
494 lhz r4, PACAPACAINDEX(r13)
495 clrldi r4, r4, 61 /* micro-threading => P8 => 8 threads/core */
496 addi r4, r4, KVM_SPLIT_NAPPED
498 /* Check the do_nap flag again after setting napped[] */
500 lbz r0, KVM_SPLIT_DO_NAP(r3)
503 li r3, (LPCR_PECEDH | LPCR_PECE0) >> 4
505 rlwimi r5, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1)
512 /******************************************************************************
516 *****************************************************************************/
518 /* Stack frame offsets */
519 #define STACK_SLOT_TID (112-16)
520 #define STACK_SLOT_PSSCR (112-24)
522 .global kvmppc_hv_entry
527 * R4 = vcpu pointer (or NULL)
532 * all other volatile GPRS = free
535 std r0, PPC_LR_STKOFF(r1)
538 /* Save R1 in the PACA */
539 std r1, HSTATE_HOST_R1(r13)
541 li r6, KVM_GUEST_MODE_HOST_HV
542 stb r6, HSTATE_IN_GUEST(r13)
544 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
545 /* Store initial timestamp */
548 addi r3, r4, VCPU_TB_RMENTRY
549 bl kvmhv_start_timing
559 * POWER7/POWER8 host -> guest partition switch code.
560 * We don't have to lock against concurrent tlbies,
561 * but we do have to coordinate across hardware threads.
563 /* Set bit in entry map iff exit map is zero. */
564 ld r5, HSTATE_KVM_VCORE(r13)
566 lbz r6, HSTATE_PTID(r13)
568 addi r9, r5, VCORE_ENTRY_EXIT
570 cmpwi r3, 0x100 /* any threads starting to exit? */
571 bge secondary_too_late /* if so we're too late to the party */
576 /* Primary thread switches to guest partition. */
577 ld r9,VCORE_KVM(r5) /* pointer to struct kvm */
583 li r0,LPID_RSVD /* switch to reserved LPID */
586 mtspr SPRN_SDR1,r6 /* switch to partition page table */
587 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
591 /* See if we need to flush the TLB */
592 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
593 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
594 srdi r6,r6,6 /* doubleword number */
595 sldi r6,r6,3 /* address offset */
597 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
603 23: ldarx r7,0,r6 /* if set, clear the bit */
607 /* Flush the TLB of any entries for this LPID */
608 lwz r6,KVM_TLB_SETS(r9)
609 li r0,0 /* RS for P9 version of tlbiel */
611 li r7,0x800 /* IS field = 0b10 */
618 /* Add timebase offset onto timebase */
619 22: ld r8,VCORE_TB_OFFSET(r5)
622 mftb r6 /* current host timebase */
624 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
625 mftb r7 /* check if lower 24 bits overflowed */
630 addis r8,r8,0x100 /* if so, increment upper 40 bits */
633 /* Load guest PCR value to select appropriate compat mode */
634 37: ld r7, VCORE_PCR(r5)
641 /* DPDES and VTB are shared between threads */
642 ld r8, VCORE_DPDES(r5)
646 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
648 /* Mark the subcore state as inside guest */
649 bl kvmppc_subcore_enter_guest
651 ld r5, HSTATE_KVM_VCORE(r13)
652 ld r4, HSTATE_KVM_VCPU(r13)
654 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
656 /* Do we have a guest vcpu to run? */
658 beq kvmppc_primary_no_guest
661 /* Load up guest SLB entries */
662 lwz r5,VCPU_SLB_MAX(r4)
667 1: ld r8,VCPU_SLB_E(r6)
670 addi r6,r6,VCPU_SLB_SIZE
673 /* Increment yield count if they have a VPA */
677 li r6, LPPACA_YIELDCOUNT
682 stb r6, VCPU_VPA_DIRTY(r4)
685 /* Save purr/spurr */
688 std r5,HSTATE_PURR(r13)
689 std r6,HSTATE_SPURR(r13)
695 /* Save host values of some registers */
699 std r5, STACK_SLOT_TID(r1)
700 std r6, STACK_SLOT_PSSCR(r1)
701 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
704 /* Set partition DABR */
705 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
706 lwz r5,VCPU_DABRX(r4)
711 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
713 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
716 END_FTR_SECTION_IFSET(CPU_FTR_TM)
719 /* Load guest PMU registers */
720 /* R4 is live here (vcpu pointer) */
722 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
723 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
727 andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
730 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
731 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
732 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
733 lwz r6, VCPU_PMC + 8(r4)
734 lwz r7, VCPU_PMC + 12(r4)
735 lwz r8, VCPU_PMC + 16(r4)
736 lwz r9, VCPU_PMC + 20(r4)
744 ld r5, VCPU_MMCR + 8(r4)
745 ld r6, VCPU_MMCR + 16(r4)
753 ld r5, VCPU_MMCR + 24(r4)
757 BEGIN_FTR_SECTION_NESTED(96)
758 lwz r7, VCPU_PMC + 24(r4)
759 lwz r8, VCPU_PMC + 28(r4)
760 ld r9, VCPU_MMCR + 32(r4)
764 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
765 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
769 /* Load up FP, VMX and VSX registers */
772 ld r14, VCPU_GPR(R14)(r4)
773 ld r15, VCPU_GPR(R15)(r4)
774 ld r16, VCPU_GPR(R16)(r4)
775 ld r17, VCPU_GPR(R17)(r4)
776 ld r18, VCPU_GPR(R18)(r4)
777 ld r19, VCPU_GPR(R19)(r4)
778 ld r20, VCPU_GPR(R20)(r4)
779 ld r21, VCPU_GPR(R21)(r4)
780 ld r22, VCPU_GPR(R22)(r4)
781 ld r23, VCPU_GPR(R23)(r4)
782 ld r24, VCPU_GPR(R24)(r4)
783 ld r25, VCPU_GPR(R25)(r4)
784 ld r26, VCPU_GPR(R26)(r4)
785 ld r27, VCPU_GPR(R27)(r4)
786 ld r28, VCPU_GPR(R28)(r4)
787 ld r29, VCPU_GPR(R29)(r4)
788 ld r30, VCPU_GPR(R30)(r4)
789 ld r31, VCPU_GPR(R31)(r4)
791 /* Switch DSCR to guest value */
796 /* Skip next section on POWER7 */
798 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
799 /* Load up POWER8-specific registers */
801 lwz r6, VCPU_PSPB(r4)
807 ld r6, VCPU_DAWRX(r4)
808 ld r7, VCPU_CIABR(r4)
815 ld r8, VCPU_EBBHR(r4)
818 ld r5, VCPU_EBBRR(r4)
819 ld r6, VCPU_BESCR(r4)
820 lwz r7, VCPU_GUEST_PID(r4)
827 /* POWER8-only registers */
828 ld r5, VCPU_TCSCR(r4)
830 ld r7, VCPU_CSIGR(r4)
837 /* POWER9-only registers */
839 ld r6, VCPU_PSSCR(r4)
840 oris r6, r6, PSSCR_EC@h /* This makes stop trap to HV */
843 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
847 * Set the decrementer to the guest decrementer.
849 ld r8,VCPU_DEC_EXPIRES(r4)
850 /* r8 is a host timebase value here, convert to guest TB */
851 ld r5,HSTATE_KVM_VCORE(r13)
852 ld r6,VCORE_TB_OFFSET(r5)
859 ld r5, VCPU_SPRG0(r4)
860 ld r6, VCPU_SPRG1(r4)
861 ld r7, VCPU_SPRG2(r4)
862 ld r8, VCPU_SPRG3(r4)
868 /* Load up DAR and DSISR */
870 lwz r6, VCPU_DSISR(r4)
874 /* Restore AMR and UAMOR, set AMOR to all 1s */
882 /* Restore state of CTRL run bit; assume 1 on entry */
890 /* Secondary threads wait for primary to have done partition switch */
891 ld r5, HSTATE_KVM_VCORE(r13)
892 lbz r6, HSTATE_PTID(r13)
895 lbz r0, VCORE_IN_GUEST(r5)
899 20: lwz r3, VCORE_ENTRY_EXIT(r5)
902 lbz r0, VCORE_IN_GUEST(r5)
912 /* Check if HDEC expires soon */
914 cmpwi r3, 512 /* 1 microsecond */
917 deliver_guest_interrupt:
924 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
932 /* r11 = vcpu->arch.msr & ~MSR_HV */
933 rldicl r11, r11, 63 - MSR_HV_LG, 1
934 rotldi r11, r11, 1 + MSR_HV_LG
937 /* Check if we can deliver an external or decrementer interrupt now */
938 ld r0, VCPU_PENDING_EXC(r4)
939 rldicl r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
941 andi. r8, r11, MSR_EE
943 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
944 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
948 li r0, BOOK3S_INTERRUPT_EXTERNAL
952 li r0, BOOK3S_INTERRUPT_DECREMENTER
955 12: mtspr SPRN_SRR0, r10
959 bl kvmppc_msr_interrupt
965 * R10: value for HSRR0
966 * R11: value for HSRR1
971 stb r0,VCPU_CEDED(r4) /* cancel cede */
975 /* Activate guest mode, so faults get handled by KVM */
976 li r9, KVM_GUEST_MODE_GUEST_HV
977 stb r9, HSTATE_IN_GUEST(r13)
979 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
980 /* Accumulate timing */
981 addi r3, r4, VCPU_TB_GUEST
982 bl kvmhv_accumulate_time
990 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
993 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1000 ld r1, VCPU_GPR(R1)(r4)
1001 ld r2, VCPU_GPR(R2)(r4)
1002 ld r3, VCPU_GPR(R3)(r4)
1003 ld r5, VCPU_GPR(R5)(r4)
1004 ld r6, VCPU_GPR(R6)(r4)
1005 ld r7, VCPU_GPR(R7)(r4)
1006 ld r8, VCPU_GPR(R8)(r4)
1007 ld r9, VCPU_GPR(R9)(r4)
1008 ld r10, VCPU_GPR(R10)(r4)
1009 ld r11, VCPU_GPR(R11)(r4)
1010 ld r12, VCPU_GPR(R12)(r4)
1011 ld r13, VCPU_GPR(R13)(r4)
1015 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1016 ld r0, VCPU_GPR(R0)(r4)
1017 ld r4, VCPU_GPR(R4)(r4)
1026 stw r12, VCPU_TRAP(r4)
1027 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1028 addi r3, r4, VCPU_TB_RMEXIT
1029 bl kvmhv_accumulate_time
1031 11: b kvmhv_switch_to_host
1038 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
1039 12: stw r12, VCPU_TRAP(r4)
1041 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1042 addi r3, r4, VCPU_TB_RMEXIT
1043 bl kvmhv_accumulate_time
1047 /******************************************************************************
1051 *****************************************************************************/
1054 * We come here from the first-level interrupt handlers.
1056 .globl kvmppc_interrupt_hv
1057 kvmppc_interrupt_hv:
1059 * Register contents:
1060 * R12 = (guest CR << 32) | interrupt vector
1062 * guest R12 saved in shadow VCPU SCRATCH0
1063 * guest CTR saved in shadow VCPU SCRATCH1 if RELOCATABLE
1064 * guest R13 saved in SPRN_SCRATCH0
1066 std r9, HSTATE_SCRATCH2(r13)
1067 lbz r9, HSTATE_IN_GUEST(r13)
1068 cmpwi r9, KVM_GUEST_MODE_HOST_HV
1069 beq kvmppc_bad_host_intr
1070 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1071 cmpwi r9, KVM_GUEST_MODE_GUEST
1072 ld r9, HSTATE_SCRATCH2(r13)
1073 beq kvmppc_interrupt_pr
1075 /* We're now back in the host but in guest MMU context */
1076 li r9, KVM_GUEST_MODE_HOST_HV
1077 stb r9, HSTATE_IN_GUEST(r13)
1079 ld r9, HSTATE_KVM_VCPU(r13)
1081 /* Save registers */
1083 std r0, VCPU_GPR(R0)(r9)
1084 std r1, VCPU_GPR(R1)(r9)
1085 std r2, VCPU_GPR(R2)(r9)
1086 std r3, VCPU_GPR(R3)(r9)
1087 std r4, VCPU_GPR(R4)(r9)
1088 std r5, VCPU_GPR(R5)(r9)
1089 std r6, VCPU_GPR(R6)(r9)
1090 std r7, VCPU_GPR(R7)(r9)
1091 std r8, VCPU_GPR(R8)(r9)
1092 ld r0, HSTATE_SCRATCH2(r13)
1093 std r0, VCPU_GPR(R9)(r9)
1094 std r10, VCPU_GPR(R10)(r9)
1095 std r11, VCPU_GPR(R11)(r9)
1096 ld r3, HSTATE_SCRATCH0(r13)
1097 std r3, VCPU_GPR(R12)(r9)
1098 /* CR is in the high half of r12 */
1102 ld r3, HSTATE_CFAR(r13)
1103 std r3, VCPU_CFAR(r9)
1104 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1106 ld r4, HSTATE_PPR(r13)
1107 std r4, VCPU_PPR(r9)
1108 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1110 /* Restore R1/R2 so we can handle faults */
1111 ld r1, HSTATE_HOST_R1(r13)
1114 mfspr r10, SPRN_SRR0
1115 mfspr r11, SPRN_SRR1
1116 std r10, VCPU_SRR0(r9)
1117 std r11, VCPU_SRR1(r9)
1118 /* trap is in the low half of r12, clear CR from the high half */
1120 andi. r0, r12, 2 /* need to read HSRR0/1? */
1122 mfspr r10, SPRN_HSRR0
1123 mfspr r11, SPRN_HSRR1
1125 1: std r10, VCPU_PC(r9)
1126 std r11, VCPU_MSR(r9)
1130 std r3, VCPU_GPR(R13)(r9)
1133 stw r12,VCPU_TRAP(r9)
1135 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1136 addi r3, r9, VCPU_TB_RMINTR
1138 bl kvmhv_accumulate_time
1139 ld r5, VCPU_GPR(R5)(r9)
1140 ld r6, VCPU_GPR(R6)(r9)
1141 ld r7, VCPU_GPR(R7)(r9)
1142 ld r8, VCPU_GPR(R8)(r9)
1145 /* Save HEIR (HV emulation assist reg) in emul_inst
1146 if this is an HEI (HV emulation interrupt, e40) */
1147 li r3,KVM_INST_FETCH_FAILED
1148 stw r3,VCPU_LAST_INST(r9)
1149 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1152 11: stw r3,VCPU_HEIR(r9)
1154 /* these are volatile across C function calls */
1155 #ifdef CONFIG_RELOCATABLE
1156 ld r3, HSTATE_SCRATCH1(r13)
1162 std r3, VCPU_CTR(r9)
1163 std r4, VCPU_XER(r9)
1165 /* If this is a page table miss then see if it's theirs or ours */
1166 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1168 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1171 /* See if this is a leftover HDEC interrupt */
1172 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1177 bge fast_guest_return
1179 /* See if this is an hcall we can handle in real mode */
1180 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1181 beq hcall_try_real_mode
1183 /* Hypervisor doorbell - exit only if host IPI flag set */
1184 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
1186 lbz r0, HSTATE_HOST_IPI(r13)
1191 /* External interrupt ? */
1192 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1193 bne+ guest_exit_cont
1195 /* External interrupt, first check for host_ipi. If this is
1196 * set, we know the host wants us out so let's do it now
1201 * Restore the active volatile registers after returning from
1204 ld r9, HSTATE_KVM_VCPU(r13)
1205 li r12, BOOK3S_INTERRUPT_EXTERNAL
1208 * kvmppc_read_intr return codes:
1210 * Exit to host (r3 > 0)
1211 * 1 An interrupt is pending that needs to be handled by the host
1212 * Exit guest and return to host by branching to guest_exit_cont
1214 * 2 Passthrough that needs completion in the host
1215 * Exit guest and return to host by branching to guest_exit_cont
1216 * However, we also set r12 to BOOK3S_INTERRUPT_HV_RM_HARD
1217 * to indicate to the host to complete handling the interrupt
1219 * Before returning to guest, we check if any CPU is heading out
1220 * to the host and if so, we head out also. If no CPUs are heading
1221 * check return values <= 0.
1223 * Return to guest (r3 <= 0)
1224 * 0 No external interrupt is pending
1225 * -1 A guest wakeup IPI (which has now been cleared)
1226 * In either case, we return to guest to deliver any pending
1229 * -2 A PCI passthrough external interrupt was handled
1230 * (interrupt was delivered directly to guest)
1231 * Return to guest to deliver any pending guest interrupts.
1237 /* Return code = 2 */
1238 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
1239 stw r12, VCPU_TRAP(r9)
1242 1: /* Return code <= 1 */
1246 /* Return code <= 0 */
1247 4: ld r5, HSTATE_KVM_VCORE(r13)
1248 lwz r0, VCORE_ENTRY_EXIT(r5)
1251 blt deliver_guest_interrupt
1253 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1254 /* Save more register state */
1257 std r6, VCPU_DAR(r9)
1258 stw r7, VCPU_DSISR(r9)
1259 /* don't overwrite fault_dar/fault_dsisr if HDSI */
1260 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
1262 std r6, VCPU_FAULT_DAR(r9)
1263 stw r7, VCPU_FAULT_DSISR(r9)
1265 /* See if it is a machine check */
1266 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1267 beq machine_check_realmode
1269 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1270 addi r3, r9, VCPU_TB_RMEXIT
1272 bl kvmhv_accumulate_time
1276 /* Increment exit count, poke other threads to exit */
1277 bl kvmhv_commence_exit
1279 ld r9, HSTATE_KVM_VCPU(r13)
1280 lwz r12, VCPU_TRAP(r9)
1282 /* Stop others sending VCPU interrupts to this physical CPU */
1284 stw r0, VCPU_CPU(r9)
1285 stw r0, VCPU_THREAD_CPU(r9)
1287 /* Save guest CTRL register, set runlatch to 1 */
1289 stw r6,VCPU_CTRL(r9)
1295 /* Read the guest SLB and save it away */
1296 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1302 andis. r0,r8,SLB_ESID_V@h
1304 add r8,r8,r6 /* put index in */
1306 std r8,VCPU_SLB_E(r7)
1307 std r3,VCPU_SLB_V(r7)
1308 addi r7,r7,VCPU_SLB_SIZE
1312 stw r5,VCPU_SLB_MAX(r9)
1315 * Save the guest PURR/SPURR
1320 ld r8,VCPU_SPURR(r9)
1321 std r5,VCPU_PURR(r9)
1322 std r6,VCPU_SPURR(r9)
1327 * Restore host PURR/SPURR and add guest times
1328 * so that the time in the guest gets accounted.
1330 ld r3,HSTATE_PURR(r13)
1331 ld r4,HSTATE_SPURR(r13)
1342 /* r5 is a guest timebase value here, convert to host TB */
1343 ld r3,HSTATE_KVM_VCORE(r13)
1344 ld r4,VCORE_TB_OFFSET(r3)
1346 std r5,VCPU_DEC_EXPIRES(r9)
1350 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1351 /* Save POWER8-specific registers */
1355 std r5, VCPU_IAMR(r9)
1356 stw r6, VCPU_PSPB(r9)
1357 std r7, VCPU_FSCR(r9)
1361 std r7, VCPU_TAR(r9)
1362 mfspr r8, SPRN_EBBHR
1363 std r8, VCPU_EBBHR(r9)
1364 mfspr r5, SPRN_EBBRR
1365 mfspr r6, SPRN_BESCR
1368 std r5, VCPU_EBBRR(r9)
1369 std r6, VCPU_BESCR(r9)
1370 stw r7, VCPU_GUEST_PID(r9)
1371 std r8, VCPU_WORT(r9)
1373 mfspr r5, SPRN_TCSCR
1375 mfspr r7, SPRN_CSIGR
1377 std r5, VCPU_TCSCR(r9)
1378 std r6, VCPU_ACOP(r9)
1379 std r7, VCPU_CSIGR(r9)
1380 std r8, VCPU_TACR(r9)
1383 mfspr r6, SPRN_PSSCR
1384 std r5, VCPU_TID(r9)
1385 rldicl r6, r6, 4, 50 /* r6 &= PSSCR_GUEST_VIS */
1387 std r6, VCPU_PSSCR(r9)
1388 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
1390 * Restore various registers to 0, where non-zero values
1391 * set by the guest could disrupt the host.
1395 mtspr SPRN_CIABR, r0
1396 mtspr SPRN_DAWRX, r0
1399 mtspr SPRN_TCSCR, r0
1400 /* Set MMCRS to 1<<31 to freeze and disable the SPMC counters */
1403 mtspr SPRN_MMCRS, r0
1404 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1407 /* Save and reset AMR and UAMOR before turning on the MMU */
1411 std r6,VCPU_UAMOR(r9)
1415 /* Switch DSCR back to host value */
1417 ld r7, HSTATE_DSCR(r13)
1418 std r8, VCPU_DSCR(r9)
1421 /* Save non-volatile GPRs */
1422 std r14, VCPU_GPR(R14)(r9)
1423 std r15, VCPU_GPR(R15)(r9)
1424 std r16, VCPU_GPR(R16)(r9)
1425 std r17, VCPU_GPR(R17)(r9)
1426 std r18, VCPU_GPR(R18)(r9)
1427 std r19, VCPU_GPR(R19)(r9)
1428 std r20, VCPU_GPR(R20)(r9)
1429 std r21, VCPU_GPR(R21)(r9)
1430 std r22, VCPU_GPR(R22)(r9)
1431 std r23, VCPU_GPR(R23)(r9)
1432 std r24, VCPU_GPR(R24)(r9)
1433 std r25, VCPU_GPR(R25)(r9)
1434 std r26, VCPU_GPR(R26)(r9)
1435 std r27, VCPU_GPR(R27)(r9)
1436 std r28, VCPU_GPR(R28)(r9)
1437 std r29, VCPU_GPR(R29)(r9)
1438 std r30, VCPU_GPR(R30)(r9)
1439 std r31, VCPU_GPR(R31)(r9)
1442 mfspr r3, SPRN_SPRG0
1443 mfspr r4, SPRN_SPRG1
1444 mfspr r5, SPRN_SPRG2
1445 mfspr r6, SPRN_SPRG3
1446 std r3, VCPU_SPRG0(r9)
1447 std r4, VCPU_SPRG1(r9)
1448 std r5, VCPU_SPRG2(r9)
1449 std r6, VCPU_SPRG3(r9)
1455 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1458 END_FTR_SECTION_IFSET(CPU_FTR_TM)
1461 /* Increment yield count if they have a VPA */
1462 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1465 li r4, LPPACA_YIELDCOUNT
1470 stb r3, VCPU_VPA_DIRTY(r9)
1472 /* Save PMU registers if requested */
1473 /* r8 and cr0.eq are live here */
1476 * POWER8 seems to have a hardware bug where setting
1477 * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
1478 * when some counters are already negative doesn't seem
1479 * to cause a performance monitor alert (and hence interrupt).
1480 * The effect of this is that when saving the PMU state,
1481 * if there is no PMU alert pending when we read MMCR0
1482 * before freezing the counters, but one becomes pending
1483 * before we read the counters, we lose it.
1484 * To work around this, we need a way to freeze the counters
1485 * before reading MMCR0. Normally, freezing the counters
1486 * is done by writing MMCR0 (to set MMCR0[FC]) which
1487 * unavoidably writes MMCR0[PMA0] as well. On POWER8,
1488 * we can also freeze the counters using MMCR2, by writing
1489 * 1s to all the counter freeze condition bits (there are
1490 * 9 bits each for 6 counters).
1492 li r3, -1 /* set all freeze bits */
1494 mfspr r10, SPRN_MMCR2
1495 mtspr SPRN_MMCR2, r3
1497 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1499 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1500 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1501 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1502 mfspr r6, SPRN_MMCRA
1503 /* Clear MMCRA in order to disable SDAR updates */
1505 mtspr SPRN_MMCRA, r7
1507 beq 21f /* if no VPA, save PMU stuff anyway */
1508 lbz r7, LPPACA_PMCINUSE(r8)
1509 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1511 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1513 21: mfspr r5, SPRN_MMCR1
1516 std r4, VCPU_MMCR(r9)
1517 std r5, VCPU_MMCR + 8(r9)
1518 std r6, VCPU_MMCR + 16(r9)
1520 std r10, VCPU_MMCR + 24(r9)
1521 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1522 std r7, VCPU_SIAR(r9)
1523 std r8, VCPU_SDAR(r9)
1530 stw r3, VCPU_PMC(r9)
1531 stw r4, VCPU_PMC + 4(r9)
1532 stw r5, VCPU_PMC + 8(r9)
1533 stw r6, VCPU_PMC + 12(r9)
1534 stw r7, VCPU_PMC + 16(r9)
1535 stw r8, VCPU_PMC + 20(r9)
1538 std r5, VCPU_SIER(r9)
1539 BEGIN_FTR_SECTION_NESTED(96)
1540 mfspr r6, SPRN_SPMC1
1541 mfspr r7, SPRN_SPMC2
1542 mfspr r8, SPRN_MMCRS
1543 stw r6, VCPU_PMC + 24(r9)
1544 stw r7, VCPU_PMC + 28(r9)
1545 std r8, VCPU_MMCR + 32(r9)
1547 mtspr SPRN_MMCRS, r4
1548 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
1549 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1557 /* Restore host values of some registers */
1559 ld r5, STACK_SLOT_TID(r1)
1560 ld r6, STACK_SLOT_PSSCR(r1)
1562 mtspr SPRN_PSSCR, r6
1563 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1566 * POWER7/POWER8 guest -> host partition switch code.
1567 * We don't have to lock against tlbies but we do
1568 * have to coordinate the hardware threads.
1570 kvmhv_switch_to_host:
1571 /* Secondary threads wait for primary to do partition switch */
1572 ld r5,HSTATE_KVM_VCORE(r13)
1573 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1574 lbz r3,HSTATE_PTID(r13)
1578 13: lbz r3,VCORE_IN_GUEST(r5)
1584 /* Primary thread waits for all the secondaries to exit guest */
1585 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1586 rlwinm r0,r3,32-8,0xff
1592 /* Did we actually switch to the guest at all? */
1593 lbz r6, VCORE_IN_GUEST(r5)
1597 /* Primary thread switches back to host partition */
1598 lwz r7,KVM_HOST_LPID(r4)
1600 ld r6,KVM_HOST_SDR1(r4)
1601 li r8,LPID_RSVD /* switch to reserved LPID */
1604 mtspr SPRN_SDR1,r6 /* switch to host page table */
1605 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1610 /* DPDES and VTB are shared between threads */
1611 mfspr r7, SPRN_DPDES
1613 std r7, VCORE_DPDES(r5)
1614 std r8, VCORE_VTB(r5)
1615 /* clear DPDES so we don't get guest doorbells in the host */
1617 mtspr SPRN_DPDES, r8
1618 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1620 /* If HMI, call kvmppc_realmode_hmi_handler() */
1621 cmpwi r12, BOOK3S_INTERRUPT_HMI
1623 bl kvmppc_realmode_hmi_handler
1625 li r12, BOOK3S_INTERRUPT_HMI
1627 * At this point kvmppc_realmode_hmi_handler would have resync-ed
1628 * the TB. Hence it is not required to subtract guest timebase
1629 * offset from timebase. So, skip it.
1631 * Also, do not call kvmppc_subcore_exit_guest() because it has
1632 * been invoked as part of kvmppc_realmode_hmi_handler().
1637 /* Subtract timebase offset from timebase */
1638 ld r8,VCORE_TB_OFFSET(r5)
1641 mftb r6 /* current guest timebase */
1643 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1644 mftb r7 /* check if lower 24 bits overflowed */
1649 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1652 17: bl kvmppc_subcore_exit_guest
1654 30: ld r5,HSTATE_KVM_VCORE(r13)
1655 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1658 ld r0, VCORE_PCR(r5)
1664 /* Signal secondary CPUs to continue */
1665 stb r0,VCORE_IN_GUEST(r5)
1666 19: lis r8,0x7fff /* MAX_INT@h */
1669 16: ld r8,KVM_HOST_LPCR(r4)
1673 /* load host SLB entries */
1674 ld r8,PACA_SLBSHADOWPTR(r13)
1676 .rept SLB_NUM_BOLTED
1677 li r3, SLBSHADOW_SAVEAREA
1681 andis. r7,r5,SLB_ESID_V@h
1687 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1688 /* Finish timing, if we have a vcpu */
1689 ld r4, HSTATE_KVM_VCPU(r13)
1693 bl kvmhv_accumulate_time
1696 /* Unset guest mode */
1697 li r0, KVM_GUEST_MODE_NONE
1698 stb r0, HSTATE_IN_GUEST(r13)
1700 ld r0, 112+PPC_LR_STKOFF(r1)
1706 * Check whether an HDSI is an HPTE not found fault or something else.
1707 * If it is an HPTE not found fault that is due to the guest accessing
1708 * a page that they have mapped but which we have paged out, then
1709 * we continue on with the guest exit path. In all other cases,
1710 * reflect the HDSI to the guest as a DSI.
1714 mfspr r6, SPRN_HDSISR
1715 /* HPTE not found fault or protection fault? */
1716 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1717 beq 1f /* if not, send it to the guest */
1718 andi. r0, r11, MSR_DR /* data relocation enabled? */
1721 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1722 li r0, BOOK3S_INTERRUPT_DATA_SEGMENT
1723 bne 7f /* if no SLB entry found */
1724 4: std r4, VCPU_FAULT_DAR(r9)
1725 stw r6, VCPU_FAULT_DSISR(r9)
1727 /* Search the hash table. */
1728 mr r3, r9 /* vcpu pointer */
1729 li r7, 1 /* data fault */
1730 bl kvmppc_hpte_hv_fault
1731 ld r9, HSTATE_KVM_VCPU(r13)
1733 ld r11, VCPU_MSR(r9)
1734 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1735 cmpdi r3, 0 /* retry the instruction */
1737 cmpdi r3, -1 /* handle in kernel mode */
1739 cmpdi r3, -2 /* MMIO emulation; need instr word */
1742 /* Synthesize a DSI (or DSegI) for the guest */
1743 ld r4, VCPU_FAULT_DAR(r9)
1745 1: li r0, BOOK3S_INTERRUPT_DATA_STORAGE
1746 mtspr SPRN_DSISR, r6
1747 7: mtspr SPRN_DAR, r4
1748 mtspr SPRN_SRR0, r10
1749 mtspr SPRN_SRR1, r11
1751 bl kvmppc_msr_interrupt
1752 fast_interrupt_c_return:
1753 6: ld r7, VCPU_CTR(r9)
1760 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1761 ld r5, KVM_VRMA_SLB_V(r5)
1764 /* If this is for emulated MMIO, load the instruction word */
1765 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1767 /* Set guest mode to 'jump over instruction' so if lwz faults
1768 * we'll just continue at the next IP. */
1769 li r0, KVM_GUEST_MODE_SKIP
1770 stb r0, HSTATE_IN_GUEST(r13)
1772 /* Do the access with MSR:DR enabled */
1774 ori r4, r3, MSR_DR /* Enable paging for data */
1779 /* Store the result */
1780 stw r8, VCPU_LAST_INST(r9)
1782 /* Unset guest mode. */
1783 li r0, KVM_GUEST_MODE_HOST_HV
1784 stb r0, HSTATE_IN_GUEST(r13)
1788 * Similarly for an HISI, reflect it to the guest as an ISI unless
1789 * it is an HPTE not found fault for a page that we have paged out.
1792 andis. r0, r11, SRR1_ISI_NOPT@h
1794 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1797 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1798 li r0, BOOK3S_INTERRUPT_INST_SEGMENT
1799 bne 7f /* if no SLB entry found */
1801 /* Search the hash table. */
1802 mr r3, r9 /* vcpu pointer */
1805 li r7, 0 /* instruction fault */
1806 bl kvmppc_hpte_hv_fault
1807 ld r9, HSTATE_KVM_VCPU(r13)
1809 ld r11, VCPU_MSR(r9)
1810 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1811 cmpdi r3, 0 /* retry the instruction */
1812 beq fast_interrupt_c_return
1813 cmpdi r3, -1 /* handle in kernel mode */
1816 /* Synthesize an ISI (or ISegI) for the guest */
1818 1: li r0, BOOK3S_INTERRUPT_INST_STORAGE
1819 7: mtspr SPRN_SRR0, r10
1820 mtspr SPRN_SRR1, r11
1822 bl kvmppc_msr_interrupt
1823 b fast_interrupt_c_return
1825 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1826 ld r5, KVM_VRMA_SLB_V(r6)
1830 * Try to handle an hcall in real mode.
1831 * Returns to the guest if we handle it, or continues on up to
1832 * the kernel if we can't (i.e. if we don't have a handler for
1833 * it, or if the handler returns H_TOO_HARD).
1835 * r5 - r8 contain hcall args,
1836 * r9 = vcpu, r10 = pc, r11 = msr, r12 = trap, r13 = paca
1838 hcall_try_real_mode:
1839 ld r3,VCPU_GPR(R3)(r9)
1841 /* sc 1 from userspace - reflect to guest syscall */
1842 bne sc_1_fast_return
1844 cmpldi r3,hcall_real_table_end - hcall_real_table
1846 /* See if this hcall is enabled for in-kernel handling */
1848 srdi r0, r3, 8 /* r0 = (r3 / 4) >> 6 */
1849 sldi r0, r0, 3 /* index into kvm->arch.enabled_hcalls[] */
1851 ld r0, KVM_ENABLED_HCALLS(r4)
1852 rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */
1856 /* Get pointer to handler, if any, and call it */
1857 LOAD_REG_ADDR(r4, hcall_real_table)
1863 mr r3,r9 /* get vcpu pointer */
1864 ld r4,VCPU_GPR(R4)(r9)
1867 beq hcall_real_fallback
1868 ld r4,HSTATE_KVM_VCPU(r13)
1869 std r3,VCPU_GPR(R3)(r4)
1877 li r10, BOOK3S_INTERRUPT_SYSCALL
1878 bl kvmppc_msr_interrupt
1882 /* We've attempted a real mode hcall, but it's punted it back
1883 * to userspace. We need to restore some clobbered volatiles
1884 * before resuming the pass-it-to-qemu path */
1885 hcall_real_fallback:
1886 li r12,BOOK3S_INTERRUPT_SYSCALL
1887 ld r9, HSTATE_KVM_VCPU(r13)
1891 .globl hcall_real_table
1893 .long 0 /* 0 - unused */
1894 .long DOTSYM(kvmppc_h_remove) - hcall_real_table
1895 .long DOTSYM(kvmppc_h_enter) - hcall_real_table
1896 .long DOTSYM(kvmppc_h_read) - hcall_real_table
1897 .long DOTSYM(kvmppc_h_clear_mod) - hcall_real_table
1898 .long DOTSYM(kvmppc_h_clear_ref) - hcall_real_table
1899 .long DOTSYM(kvmppc_h_protect) - hcall_real_table
1900 .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table
1901 .long DOTSYM(kvmppc_rm_h_put_tce) - hcall_real_table
1902 .long 0 /* 0x24 - H_SET_SPRG0 */
1903 .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
1918 #ifdef CONFIG_KVM_XICS
1919 .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table
1920 .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table
1921 .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table
1922 .long 0 /* 0x70 - H_IPOLL */
1923 .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table
1925 .long 0 /* 0x64 - H_EOI */
1926 .long 0 /* 0x68 - H_CPPR */
1927 .long 0 /* 0x6c - H_IPI */
1928 .long 0 /* 0x70 - H_IPOLL */
1929 .long 0 /* 0x74 - H_XIRR */
1957 .long DOTSYM(kvmppc_h_cede) - hcall_real_table
1958 .long DOTSYM(kvmppc_rm_h_confer) - hcall_real_table
1974 .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table
1978 .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
1979 .long DOTSYM(kvmppc_rm_h_stuff_tce) - hcall_real_table
1980 .long DOTSYM(kvmppc_rm_h_put_tce_indirect) - hcall_real_table
2093 .long DOTSYM(kvmppc_h_random) - hcall_real_table
2094 .globl hcall_real_table_end
2095 hcall_real_table_end:
2097 _GLOBAL(kvmppc_h_set_xdabr)
2098 andi. r0, r5, DABRX_USER | DABRX_KERNEL
2100 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
2103 6: li r3, H_PARAMETER
2106 _GLOBAL(kvmppc_h_set_dabr)
2107 li r5, DABRX_USER | DABRX_KERNEL
2111 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2112 std r4,VCPU_DABR(r3)
2113 stw r5, VCPU_DABRX(r3)
2114 mtspr SPRN_DABRX, r5
2115 /* Work around P7 bug where DABR can get corrupted on mtspr */
2116 1: mtspr SPRN_DABR,r4
2124 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
2125 2: rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
2126 rlwimi r5, r4, 2, DAWRX_WT
2128 std r4, VCPU_DAWR(r3)
2129 std r5, VCPU_DAWRX(r3)
2131 mtspr SPRN_DAWRX, r5
2135 _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */
2137 std r11,VCPU_MSR(r3)
2139 stb r0,VCPU_CEDED(r3)
2140 sync /* order setting ceded vs. testing prodded */
2141 lbz r5,VCPU_PRODDED(r3)
2143 bne kvm_cede_prodded
2144 li r12,0 /* set trap to 0 to say hcall is handled */
2145 stw r12,VCPU_TRAP(r3)
2147 std r0,VCPU_GPR(R3)(r3)
2150 * Set our bit in the bitmask of napping threads unless all the
2151 * other threads are already napping, in which case we send this
2154 ld r5,HSTATE_KVM_VCORE(r13)
2155 lbz r6,HSTATE_PTID(r13)
2156 lwz r8,VCORE_ENTRY_EXIT(r5)
2160 addi r6,r5,VCORE_NAPPING_THREADS
2167 /* order napping_threads update vs testing entry_exit_map */
2170 stb r0,HSTATE_NAPPING(r13)
2171 lwz r7,VCORE_ENTRY_EXIT(r5)
2173 bge 33f /* another thread already exiting */
2176 * Although not specifically required by the architecture, POWER7
2177 * preserves the following registers in nap mode, even if an SMT mode
2178 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2179 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2181 /* Save non-volatile GPRs */
2182 std r14, VCPU_GPR(R14)(r3)
2183 std r15, VCPU_GPR(R15)(r3)
2184 std r16, VCPU_GPR(R16)(r3)
2185 std r17, VCPU_GPR(R17)(r3)
2186 std r18, VCPU_GPR(R18)(r3)
2187 std r19, VCPU_GPR(R19)(r3)
2188 std r20, VCPU_GPR(R20)(r3)
2189 std r21, VCPU_GPR(R21)(r3)
2190 std r22, VCPU_GPR(R22)(r3)
2191 std r23, VCPU_GPR(R23)(r3)
2192 std r24, VCPU_GPR(R24)(r3)
2193 std r25, VCPU_GPR(R25)(r3)
2194 std r26, VCPU_GPR(R26)(r3)
2195 std r27, VCPU_GPR(R27)(r3)
2196 std r28, VCPU_GPR(R28)(r3)
2197 std r29, VCPU_GPR(R29)(r3)
2198 std r30, VCPU_GPR(R30)(r3)
2199 std r31, VCPU_GPR(R31)(r3)
2204 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2206 ld r9, HSTATE_KVM_VCPU(r13)
2208 END_FTR_SECTION_IFSET(CPU_FTR_TM)
2212 * Set DEC to the smaller of DEC and HDEC, so that we wake
2213 * no later than the end of our timeslice (HDEC interrupts
2214 * don't wake us from nap).
2223 /* save expiry time of guest decrementer */
2226 ld r4, HSTATE_KVM_VCPU(r13)
2227 ld r5, HSTATE_KVM_VCORE(r13)
2228 ld r6, VCORE_TB_OFFSET(r5)
2229 subf r3, r6, r3 /* convert to host TB value */
2230 std r3, VCPU_DEC_EXPIRES(r4)
2232 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2233 ld r4, HSTATE_KVM_VCPU(r13)
2234 addi r3, r4, VCPU_TB_CEDE
2235 bl kvmhv_accumulate_time
2238 lis r3, LPCR_PECEDP@h /* Do wake on privileged doorbell */
2241 * Take a nap until a decrementer or external or doobell interrupt
2242 * occurs, with PECE1 and PECE0 set in LPCR.
2243 * On POWER8, set PECEDH, and if we are ceding, also set PECEDP.
2244 * Also clear the runlatch bit before napping.
2247 mfspr r0, SPRN_CTRLF
2249 mtspr SPRN_CTRLT, r0
2252 stb r0,HSTATE_HWTHREAD_REQ(r13)
2254 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2256 ori r5, r5, LPCR_PECEDH
2257 rlwimi r5, r3, 0, LPCR_PECEDP
2258 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2260 kvm_nap_sequence: /* desired LPCR value in r5 */
2263 * PSSCR bits: exit criterion = 1 (wakeup based on LPCR at sreset)
2264 * enable state loss = 1 (allow SMT mode switch)
2265 * requested level = 0 (just stop dispatching)
2267 lis r3, (PSSCR_EC | PSSCR_ESL)@h
2268 mtspr SPRN_PSSCR, r3
2269 /* Set LPCR_PECE_HVEE bit to enable wakeup by HV interrupts */
2270 li r4, LPCR_PECE_HVEE@higher
2273 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2277 std r0, HSTATE_SCRATCH0(r13)
2279 ld r0, HSTATE_SCRATCH0(r13)
2286 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
2295 /* get vcpu pointer */
2296 ld r4, HSTATE_KVM_VCPU(r13)
2298 /* Woken by external or decrementer interrupt */
2299 ld r1, HSTATE_HOST_R1(r13)
2301 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2302 addi r3, r4, VCPU_TB_RMINTR
2303 bl kvmhv_accumulate_time
2306 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2308 bl kvmppc_restore_tm
2309 END_FTR_SECTION_IFSET(CPU_FTR_TM)
2312 /* load up FP state */
2315 /* Restore guest decrementer */
2316 ld r3, VCPU_DEC_EXPIRES(r4)
2317 ld r5, HSTATE_KVM_VCORE(r13)
2318 ld r6, VCORE_TB_OFFSET(r5)
2319 add r3, r3, r6 /* convert host TB to guest TB value */
2325 ld r14, VCPU_GPR(R14)(r4)
2326 ld r15, VCPU_GPR(R15)(r4)
2327 ld r16, VCPU_GPR(R16)(r4)
2328 ld r17, VCPU_GPR(R17)(r4)
2329 ld r18, VCPU_GPR(R18)(r4)
2330 ld r19, VCPU_GPR(R19)(r4)
2331 ld r20, VCPU_GPR(R20)(r4)
2332 ld r21, VCPU_GPR(R21)(r4)
2333 ld r22, VCPU_GPR(R22)(r4)
2334 ld r23, VCPU_GPR(R23)(r4)
2335 ld r24, VCPU_GPR(R24)(r4)
2336 ld r25, VCPU_GPR(R25)(r4)
2337 ld r26, VCPU_GPR(R26)(r4)
2338 ld r27, VCPU_GPR(R27)(r4)
2339 ld r28, VCPU_GPR(R28)(r4)
2340 ld r29, VCPU_GPR(R29)(r4)
2341 ld r30, VCPU_GPR(R30)(r4)
2342 ld r31, VCPU_GPR(R31)(r4)
2344 /* Check the wake reason in SRR1 to see why we got here */
2345 bl kvmppc_check_wake_reason
2348 * Restore volatile registers since we could have called a
2349 * C routine in kvmppc_check_wake_reason
2351 * r3 tells us whether we need to return to host or not
2352 * WARNING: it gets checked further down:
2353 * should not modify r3 until this check is done.
2355 ld r4, HSTATE_KVM_VCPU(r13)
2357 /* clear our bit in vcore->napping_threads */
2358 34: ld r5,HSTATE_KVM_VCORE(r13)
2359 lbz r7,HSTATE_PTID(r13)
2362 addi r6,r5,VCORE_NAPPING_THREADS
2368 stb r0,HSTATE_NAPPING(r13)
2370 /* See if the wake reason saved in r3 means we need to exit */
2371 stw r12, VCPU_TRAP(r4)
2376 /* see if any other thread is already exiting */
2377 lwz r0,VCORE_ENTRY_EXIT(r5)
2381 b kvmppc_cede_reentry /* if not go back to guest */
2383 /* cede when already previously prodded case */
2386 stb r0,VCPU_PRODDED(r3)
2387 sync /* order testing prodded vs. clearing ceded */
2388 stb r0,VCPU_CEDED(r3)
2392 /* we've ceded but we want to give control to the host */
2394 ld r9, HSTATE_KVM_VCPU(r13)
2397 /* Try to handle a machine check in real mode */
2398 machine_check_realmode:
2399 mr r3, r9 /* get vcpu pointer */
2400 bl kvmppc_realmode_machine_check
2402 ld r9, HSTATE_KVM_VCPU(r13)
2403 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2405 * Deliver unhandled/fatal (e.g. UE) MCE errors to guest through
2406 * machine check interrupt (set HSRR0 to 0x200). And for handled
2407 * errors (no-fatal), just go back to guest execution with current
2408 * HSRR0 instead of exiting guest. This new approach will inject
2409 * machine check to guest for fatal error causing guest to crash.
2411 * The old code used to return to host for unhandled errors which
2412 * was causing guest to hang with soft lockups inside guest and
2413 * makes it difficult to recover guest instance.
2415 * if we receive machine check with MSR(RI=0) then deliver it to
2416 * guest as machine check causing guest to crash.
2418 ld r11, VCPU_MSR(r9)
2419 rldicl. r0, r11, 64-MSR_HV_LG, 63 /* check if it happened in HV mode */
2420 bne mc_cont /* if so, exit to host */
2421 andi. r10, r11, MSR_RI /* check for unrecoverable exception */
2422 beq 1f /* Deliver a machine check to guest */
2424 cmpdi r3, 0 /* Did we handle MCE ? */
2425 bne 2f /* Continue guest execution. */
2426 /* If not, deliver a machine check. SRR0/1 are already set */
2427 1: li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
2428 bl kvmppc_msr_interrupt
2429 2: b fast_interrupt_c_return
2432 * Check the reason we woke from nap, and take appropriate action.
2434 * 0 if nothing needs to be done
2435 * 1 if something happened that needs to be handled by the host
2436 * -1 if there was a guest wakeup (IPI or msgsnd)
2437 * -2 if we handled a PCI passthrough interrupt (returned by
2438 * kvmppc_read_intr only)
2440 * Also sets r12 to the interrupt vector for any interrupt that needs
2441 * to be handled now by the host (0x500 for external interrupt), or zero.
2442 * Modifies all volatile registers (since it may call a C function).
2443 * This routine calls kvmppc_read_intr, a C function, if an external
2444 * interrupt is pending.
2446 kvmppc_check_wake_reason:
2449 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2451 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2452 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2453 cmpwi r6, 8 /* was it an external interrupt? */
2454 beq 7f /* if so, see what it was */
2457 cmpwi r6, 6 /* was it the decrementer? */
2460 cmpwi r6, 5 /* privileged doorbell? */
2462 cmpwi r6, 3 /* hypervisor doorbell? */
2464 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2465 cmpwi r6, 0xa /* Hypervisor maintenance ? */
2467 li r3, 1 /* anything else, return 1 */
2470 /* hypervisor doorbell */
2471 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
2474 * Clear the doorbell as we will invoke the handler
2475 * explicitly in the guest exit path.
2477 lis r6, (PPC_DBELL_SERVER << (63-36))@h
2479 /* see if it's a host IPI */
2481 lbz r0, HSTATE_HOST_IPI(r13)
2484 /* if not, return -1 */
2488 /* Woken up due to Hypervisor maintenance interrupt */
2489 4: li r12, BOOK3S_INTERRUPT_HMI
2493 /* external interrupt - create a stack frame so we can call C */
2495 std r0, PPC_LR_STKOFF(r1)
2496 stdu r1, -PPC_MIN_STKFRM(r1)
2499 li r12, BOOK3S_INTERRUPT_EXTERNAL
2504 * Return code of 2 means PCI passthrough interrupt, but
2505 * we need to return back to host to complete handling the
2506 * interrupt. Trap reason is expected in r12 by guest
2509 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
2511 ld r0, PPC_MIN_STKFRM+PPC_LR_STKOFF(r1)
2512 addi r1, r1, PPC_MIN_STKFRM
2517 * Save away FP, VMX and VSX registers.
2519 * N.B. r30 and r31 are volatile across this function,
2520 * thus it is not callable from C.
2527 #ifdef CONFIG_ALTIVEC
2529 oris r8,r8,MSR_VEC@h
2530 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2534 oris r8,r8,MSR_VSX@h
2535 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2538 addi r3,r3,VCPU_FPRS
2540 #ifdef CONFIG_ALTIVEC
2542 addi r3,r31,VCPU_VRS
2544 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2546 mfspr r6,SPRN_VRSAVE
2547 stw r6,VCPU_VRSAVE(r31)
2552 * Load up FP, VMX and VSX registers
2554 * N.B. r30 and r31 are volatile across this function,
2555 * thus it is not callable from C.
2562 #ifdef CONFIG_ALTIVEC
2564 oris r8,r8,MSR_VEC@h
2565 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2569 oris r8,r8,MSR_VSX@h
2570 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2573 addi r3,r4,VCPU_FPRS
2575 #ifdef CONFIG_ALTIVEC
2577 addi r3,r31,VCPU_VRS
2579 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2581 lwz r7,VCPU_VRSAVE(r31)
2582 mtspr SPRN_VRSAVE,r7
2587 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2589 * Save transactional state and TM-related registers.
2590 * Called with r9 pointing to the vcpu struct.
2591 * This can modify all checkpointed registers, but
2592 * restores r1, r2 and r9 (vcpu pointer) before exit.
2596 std r0, PPC_LR_STKOFF(r1)
2601 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
2605 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
2606 beq 1f /* TM not active in guest. */
2608 std r1, HSTATE_HOST_R1(r13)
2609 li r3, TM_CAUSE_KVM_RESCHED
2611 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
2615 /* All GPRs are volatile at this point. */
2618 /* Temporarily store r13 and r9 so we have some regs to play with */
2621 std r9, PACATMSCRATCH(r13)
2622 ld r9, HSTATE_KVM_VCPU(r13)
2624 /* Get a few more GPRs free. */
2625 std r29, VCPU_GPRS_TM(29)(r9)
2626 std r30, VCPU_GPRS_TM(30)(r9)
2627 std r31, VCPU_GPRS_TM(31)(r9)
2629 /* Save away PPR and DSCR soon so don't run with user values. */
2632 mfspr r30, SPRN_DSCR
2633 ld r29, HSTATE_DSCR(r13)
2634 mtspr SPRN_DSCR, r29
2636 /* Save all but r9, r13 & r29-r31 */
2639 .if (reg != 9) && (reg != 13)
2640 std reg, VCPU_GPRS_TM(reg)(r9)
2644 /* ... now save r13 */
2646 std r4, VCPU_GPRS_TM(13)(r9)
2647 /* ... and save r9 */
2648 ld r4, PACATMSCRATCH(r13)
2649 std r4, VCPU_GPRS_TM(9)(r9)
2651 /* Reload stack pointer and TOC. */
2652 ld r1, HSTATE_HOST_R1(r13)
2655 /* Set MSR RI now we have r1 and r13 back. */
2659 /* Save away checkpinted SPRs. */
2660 std r31, VCPU_PPR_TM(r9)
2661 std r30, VCPU_DSCR_TM(r9)
2668 std r5, VCPU_LR_TM(r9)
2669 stw r6, VCPU_CR_TM(r9)
2670 std r7, VCPU_CTR_TM(r9)
2671 std r8, VCPU_AMR_TM(r9)
2672 std r10, VCPU_TAR_TM(r9)
2673 std r11, VCPU_XER_TM(r9)
2675 /* Restore r12 as trap number. */
2676 lwz r12, VCPU_TRAP(r9)
2679 addi r3, r9, VCPU_FPRS_TM
2681 addi r3, r9, VCPU_VRS_TM
2683 mfspr r6, SPRN_VRSAVE
2684 stw r6, VCPU_VRSAVE_TM(r9)
2687 * We need to save these SPRs after the treclaim so that the software
2688 * error code is recorded correctly in the TEXASR. Also the user may
2689 * change these outside of a transaction, so they must always be
2692 mfspr r5, SPRN_TFHAR
2693 mfspr r6, SPRN_TFIAR
2694 mfspr r7, SPRN_TEXASR
2695 std r5, VCPU_TFHAR(r9)
2696 std r6, VCPU_TFIAR(r9)
2697 std r7, VCPU_TEXASR(r9)
2699 ld r0, PPC_LR_STKOFF(r1)
2704 * Restore transactional state and TM-related registers.
2705 * Called with r4 pointing to the vcpu struct.
2706 * This potentially modifies all checkpointed registers.
2707 * It restores r1, r2, r4 from the PACA.
2711 std r0, PPC_LR_STKOFF(r1)
2713 /* Turn on TM/FP/VSX/VMX so we can restore them. */
2719 oris r5, r5, (MSR_VEC | MSR_VSX)@h
2723 * The user may change these outside of a transaction, so they must
2724 * always be context switched.
2726 ld r5, VCPU_TFHAR(r4)
2727 ld r6, VCPU_TFIAR(r4)
2728 ld r7, VCPU_TEXASR(r4)
2729 mtspr SPRN_TFHAR, r5
2730 mtspr SPRN_TFIAR, r6
2731 mtspr SPRN_TEXASR, r7
2734 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
2735 beqlr /* TM not active in guest */
2736 std r1, HSTATE_HOST_R1(r13)
2738 /* Make sure the failure summary is set, otherwise we'll program check
2739 * when we trechkpt. It's possible that this might have been not set
2740 * on a kvmppc_set_one_reg() call but we shouldn't let this crash the
2743 oris r7, r7, (TEXASR_FS)@h
2744 mtspr SPRN_TEXASR, r7
2747 * We need to load up the checkpointed state for the guest.
2748 * We need to do this early as it will blow away any GPRs, VSRs and
2753 addi r3, r31, VCPU_FPRS_TM
2755 addi r3, r31, VCPU_VRS_TM
2758 lwz r7, VCPU_VRSAVE_TM(r4)
2759 mtspr SPRN_VRSAVE, r7
2761 ld r5, VCPU_LR_TM(r4)
2762 lwz r6, VCPU_CR_TM(r4)
2763 ld r7, VCPU_CTR_TM(r4)
2764 ld r8, VCPU_AMR_TM(r4)
2765 ld r9, VCPU_TAR_TM(r4)
2766 ld r10, VCPU_XER_TM(r4)
2775 * Load up PPR and DSCR values but don't put them in the actual SPRs
2776 * till the last moment to avoid running with userspace PPR and DSCR for
2779 ld r29, VCPU_DSCR_TM(r4)
2780 ld r30, VCPU_PPR_TM(r4)
2782 std r2, PACATMSCRATCH(r13) /* Save TOC */
2784 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
2788 /* Load GPRs r0-r28 */
2791 ld reg, VCPU_GPRS_TM(reg)(r31)
2795 mtspr SPRN_DSCR, r29
2798 /* Load final GPRs */
2799 ld 29, VCPU_GPRS_TM(29)(r31)
2800 ld 30, VCPU_GPRS_TM(30)(r31)
2801 ld 31, VCPU_GPRS_TM(31)(r31)
2803 /* TM checkpointed state is now setup. All GPRs are now volatile. */
2806 /* Now let's get back the state we need. */
2809 ld r29, HSTATE_DSCR(r13)
2810 mtspr SPRN_DSCR, r29
2811 ld r4, HSTATE_KVM_VCPU(r13)
2812 ld r1, HSTATE_HOST_R1(r13)
2813 ld r2, PACATMSCRATCH(r13)
2815 /* Set the MSR RI since we have our registers back. */
2819 ld r0, PPC_LR_STKOFF(r1)
2825 * We come here if we get any exception or interrupt while we are
2826 * executing host real mode code while in guest MMU context.
2827 * For now just spin, but we should do something better.
2829 kvmppc_bad_host_intr:
2833 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
2834 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
2835 * r11 has the guest MSR value (in/out)
2836 * r9 has a vcpu pointer (in)
2837 * r0 is used as a scratch register
2839 kvmppc_msr_interrupt:
2840 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
2841 cmpwi r0, 2 /* Check if we are in transactional state.. */
2842 ld r11, VCPU_INTR_MSR(r9)
2844 /* ... if transactional, change to suspended */
2846 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
2850 * This works around a hardware bug on POWER8E processors, where
2851 * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
2852 * performance monitor interrupt. Instead, when we need to have
2853 * an interrupt pending, we have to arrange for a counter to overflow.
2857 mtspr SPRN_MMCR2, r3
2858 lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
2859 ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
2860 mtspr SPRN_MMCR0, r3
2867 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2869 * Start timing an activity
2870 * r3 = pointer to time accumulation struct, r4 = vcpu
2873 ld r5, HSTATE_KVM_VCORE(r13)
2874 lbz r6, VCORE_IN_GUEST(r5)
2876 beq 5f /* if in guest, need to */
2877 ld r6, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
2880 std r3, VCPU_CUR_ACTIVITY(r4)
2881 std r5, VCPU_ACTIVITY_START(r4)
2885 * Accumulate time to one activity and start another.
2886 * r3 = pointer to new time accumulation struct, r4 = vcpu
2888 kvmhv_accumulate_time:
2889 ld r5, HSTATE_KVM_VCORE(r13)
2890 lbz r8, VCORE_IN_GUEST(r5)
2892 beq 4f /* if in guest, need to */
2893 ld r8, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
2894 4: ld r5, VCPU_CUR_ACTIVITY(r4)
2895 ld r6, VCPU_ACTIVITY_START(r4)
2896 std r3, VCPU_CUR_ACTIVITY(r4)
2899 std r7, VCPU_ACTIVITY_START(r4)
2903 ld r8, TAS_SEQCOUNT(r5)
2906 std r8, TAS_SEQCOUNT(r5)
2908 ld r7, TAS_TOTAL(r5)
2910 std r7, TAS_TOTAL(r5)
2916 3: std r3, TAS_MIN(r5)
2922 std r8, TAS_SEQCOUNT(r5)