2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
30 /*****************************************************************************
32 * Real Mode handlers that need to be in the linear mapping *
34 ****************************************************************************/
36 .globl kvmppc_skip_interrupt
37 kvmppc_skip_interrupt:
45 .globl kvmppc_skip_Hinterrupt
46 kvmppc_skip_Hinterrupt:
55 * Call kvmppc_handler_trampoline_enter in real mode.
56 * Must be called with interrupts hard-disabled.
60 * LR = return address to continue at after eventually re-enabling MMU
62 _GLOBAL(kvmppc_hv_entry_trampoline)
64 LOAD_REG_ADDR(r5, kvmppc_hv_entry)
69 mtmsrd r0,1 /* clear RI in MSR */
75 #define VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE))
77 /******************************************************************************
81 *****************************************************************************/
87 * We come in here when wakened from nap mode on a secondary hw thread.
88 * Relocation is off and most register values are lost.
89 * r13 points to the PACA.
91 .globl kvm_start_guest
93 ld r1,PACAEMERGSP(r13)
94 subi r1,r1,STACK_FRAME_OVERHEAD
96 /* get vcpu pointer */
97 ld r4, HSTATE_KVM_VCPU(r13)
99 /* We got here with an IPI; clear it */
100 ld r5, HSTATE_XICS_PHYS(r13)
104 lwzcix r8, r5, r7 /* ack the interrupt */
106 stbcix r0, r5, r6 /* clear it */
107 stwcix r8, r5, r7 /* EOI it */
109 .global kvmppc_hv_entry
118 * all other volatile GPRS = free
121 std r0, HSTATE_VMHANDLER(r13)
123 ld r14, VCPU_GPR(r14)(r4)
124 ld r15, VCPU_GPR(r15)(r4)
125 ld r16, VCPU_GPR(r16)(r4)
126 ld r17, VCPU_GPR(r17)(r4)
127 ld r18, VCPU_GPR(r18)(r4)
128 ld r19, VCPU_GPR(r19)(r4)
129 ld r20, VCPU_GPR(r20)(r4)
130 ld r21, VCPU_GPR(r21)(r4)
131 ld r22, VCPU_GPR(r22)(r4)
132 ld r23, VCPU_GPR(r23)(r4)
133 ld r24, VCPU_GPR(r24)(r4)
134 ld r25, VCPU_GPR(r25)(r4)
135 ld r26, VCPU_GPR(r26)(r4)
136 ld r27, VCPU_GPR(r27)(r4)
137 ld r28, VCPU_GPR(r28)(r4)
138 ld r29, VCPU_GPR(r29)(r4)
139 ld r30, VCPU_GPR(r30)(r4)
140 ld r31, VCPU_GPR(r31)(r4)
142 /* Load guest PMU registers */
143 /* R4 is live here (vcpu pointer) */
145 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
146 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
148 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
149 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
150 lwz r6, VCPU_PMC + 8(r4)
151 lwz r7, VCPU_PMC + 12(r4)
152 lwz r8, VCPU_PMC + 16(r4)
153 lwz r9, VCPU_PMC + 20(r4)
155 lwz r10, VCPU_PMC + 24(r4)
156 lwz r11, VCPU_PMC + 28(r4)
157 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
167 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
169 ld r5, VCPU_MMCR + 8(r4)
170 ld r6, VCPU_MMCR + 16(r4)
176 /* Load up FP, VMX and VSX registers */
180 /* Switch DSCR to guest value */
183 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
186 * Set the decrementer to the guest decrementer.
188 ld r8,VCPU_DEC_EXPIRES(r4)
194 ld r5, VCPU_SPRG0(r4)
195 ld r6, VCPU_SPRG1(r4)
196 ld r7, VCPU_SPRG2(r4)
197 ld r8, VCPU_SPRG3(r4)
203 /* Save R1 in the PACA */
204 std r1, HSTATE_HOST_R1(r13)
206 /* Increment yield count if they have a VPA */
210 lwz r5, LPPACA_YIELDCOUNT(r3)
212 stw r5, LPPACA_YIELDCOUNT(r3)
214 /* Load up DAR and DSISR */
216 lwz r6, VCPU_DSISR(r4)
220 /* Set partition DABR */
227 /* Restore AMR and UAMOR, set AMOR to all 1s */
234 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
244 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
246 * POWER7 host -> guest partition switch code.
247 * We don't have to lock against concurrent tlbies,
248 * but we do have to coordinate across hardware threads.
250 /* Increment entry count iff exit count is zero. */
251 ld r5,HSTATE_KVM_VCORE(r13)
252 addi r9,r5,VCORE_ENTRY_EXIT
254 cmpwi r3,0x100 /* any threads starting to exit? */
255 bge secondary_too_late /* if so we're too late to the party */
260 /* Primary thread switches to guest partition. */
261 ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
267 li r0,LPID_RSVD /* switch to reserved LPID */
270 mtspr SPRN_SDR1,r6 /* switch to partition page table */
274 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
277 /* Secondary threads wait for primary to have done partition switch */
278 20: lbz r0,VCORE_IN_GUEST(r5)
282 /* Set LPCR. Set the MER bit if there is a pending external irq. */
283 10: ld r8,KVM_LPCR(r9)
284 ld r0,VCPU_PENDING_EXC(r4)
285 li r7,(1 << BOOK3S_IRQPRIO_EXTERNAL)
286 oris r7,r7,(1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h
290 11: mtspr SPRN_LPCR,r8
295 /* Check if HDEC expires soon */
298 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
303 * Invalidate the TLB if we could possibly have stale TLB
304 * entries for this partition on this core due to the use
306 * XXX maybe only need this on primary thread?
308 ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
309 lwz r5,VCPU_VCPUID(r4)
310 lhz r6,PACAPACAINDEX(r13)
311 rldimi r6,r5,0,62 /* XXX map as if threads 1:1 p:v */
312 lhz r8,VCPU_LAST_CPU(r4)
313 sldi r7,r6,1 /* see if this is the same vcpu */
314 add r7,r7,r9 /* as last ran on this pcpu */
315 lhz r0,KVM_LAST_VCPU(r7)
316 cmpw r6,r8 /* on the same cpu core as last time? */
318 cmpw r0,r5 /* same vcpu as this core last ran? */
320 3: sth r6,VCPU_LAST_CPU(r4) /* if not, invalidate partition TLB */
321 sth r5,KVM_LAST_VCPU(r7)
324 li r7,0x800 /* IS field = 0b10 */
332 /* Save purr/spurr */
335 std r5,HSTATE_PURR(r13)
336 std r6,HSTATE_SPURR(r13)
344 * PPC970 host -> guest partition switch code.
345 * We have to lock against concurrent tlbies,
346 * using native_tlbie_lock to lock against host tlbies
347 * and kvm->arch.tlbie_lock to lock against guest tlbies.
348 * We also have to invalidate the TLB since its
349 * entries aren't tagged with the LPID.
351 30: ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
353 /* first take native_tlbie_lock */
356 .tc native_tlbie_lock[TC],native_tlbie_lock
358 ld r3,toc_tlbie_lock@toc(2)
359 lwz r8,PACA_LOCK_TOKEN(r13)
367 ld r7,KVM_LPCR(r9) /* use kvm->arch.lpcr to store HID4 */
369 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
373 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
376 stw r0,0(r3) /* drop native_tlbie_lock */
378 /* invalidate the whole TLB */
387 /* Take the guest's tlbie_lock */
388 addi r3,r9,KVM_TLBIE_LOCK
396 mtspr SPRN_SDR1,r6 /* switch to partition page table */
398 /* Set up HID4 with the guest's LPID etc. */
403 /* drop the guest's tlbie_lock */
407 /* Check if HDEC expires soon */
410 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
414 /* Enable HDEC interrupts */
417 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
427 /* Load up guest SLB entries */
428 31: lwz r5,VCPU_SLB_MAX(r4)
433 1: ld r8,VCPU_SLB_E(r6)
436 addi r6,r6,VCPU_SLB_SIZE
440 /* Restore state of CTRL run bit; assume 1 on entry */
454 /* Move SRR0 and SRR1 into the respective regs */
462 ld r11, VCPU_MSR(r4) /* r10 = vcpu->arch.msr & ~MSR_HV */
463 rldicl r11, r11, 63 - MSR_HV_LG, 1
464 rotldi r11, r11, 1 + MSR_HV_LG
471 /* Activate guest mode, so faults get handled by KVM */
472 li r9, KVM_GUEST_MODE_GUEST
473 stb r9, HSTATE_IN_GUEST(r13)
482 ld r0, VCPU_GPR(r0)(r4)
483 ld r1, VCPU_GPR(r1)(r4)
484 ld r2, VCPU_GPR(r2)(r4)
485 ld r3, VCPU_GPR(r3)(r4)
486 ld r5, VCPU_GPR(r5)(r4)
487 ld r6, VCPU_GPR(r6)(r4)
488 ld r7, VCPU_GPR(r7)(r4)
489 ld r8, VCPU_GPR(r8)(r4)
490 ld r9, VCPU_GPR(r9)(r4)
491 ld r10, VCPU_GPR(r10)(r4)
492 ld r11, VCPU_GPR(r11)(r4)
493 ld r12, VCPU_GPR(r12)(r4)
494 ld r13, VCPU_GPR(r13)(r4)
496 ld r4, VCPU_GPR(r4)(r4)
501 /******************************************************************************
505 *****************************************************************************/
508 * We come here from the first-level interrupt handlers.
510 .globl kvmppc_interrupt
514 * R12 = interrupt vector
516 * guest CR, R12 saved in shadow VCPU SCRATCH1/0
517 * guest R13 saved in SPRN_SCRATCH0
519 /* abuse host_r2 as third scratch area; we get r2 from PACATOC(r13) */
520 std r9, HSTATE_HOST_R2(r13)
521 ld r9, HSTATE_KVM_VCPU(r13)
525 std r0, VCPU_GPR(r0)(r9)
526 std r1, VCPU_GPR(r1)(r9)
527 std r2, VCPU_GPR(r2)(r9)
528 std r3, VCPU_GPR(r3)(r9)
529 std r4, VCPU_GPR(r4)(r9)
530 std r5, VCPU_GPR(r5)(r9)
531 std r6, VCPU_GPR(r6)(r9)
532 std r7, VCPU_GPR(r7)(r9)
533 std r8, VCPU_GPR(r8)(r9)
534 ld r0, HSTATE_HOST_R2(r13)
535 std r0, VCPU_GPR(r9)(r9)
536 std r10, VCPU_GPR(r10)(r9)
537 std r11, VCPU_GPR(r11)(r9)
538 ld r3, HSTATE_SCRATCH0(r13)
539 lwz r4, HSTATE_SCRATCH1(r13)
540 std r3, VCPU_GPR(r12)(r9)
543 /* Restore R1/R2 so we can handle faults */
544 ld r1, HSTATE_HOST_R1(r13)
549 std r10, VCPU_SRR0(r9)
550 std r11, VCPU_SRR1(r9)
551 andi. r0, r12, 2 /* need to read HSRR0/1? */
553 mfspr r10, SPRN_HSRR0
554 mfspr r11, SPRN_HSRR1
556 1: std r10, VCPU_PC(r9)
557 std r11, VCPU_MSR(r9)
561 std r3, VCPU_GPR(r13)(r9)
564 /* Unset guest mode */
565 li r0, KVM_GUEST_MODE_NONE
566 stb r0, HSTATE_IN_GUEST(r13)
568 stw r12,VCPU_TRAP(r9)
570 /* See if this is a leftover HDEC interrupt */
571 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
577 /* See if this is something we can handle in real mode */
578 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
579 beq hcall_try_real_mode
582 /* Check for mediated interrupts (could be done earlier really ...) */
584 cmpwi r12,BOOK3S_INTERRUPT_EXTERNAL
591 bne bounce_ext_interrupt
593 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
600 std r5,VCPU_DEC_EXPIRES(r9)
602 /* Save HEIR (HV emulation assist reg) in last_inst
603 if this is an HEI (HV emulation interrupt, e40) */
606 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
609 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
610 11: stw r3,VCPU_LAST_INST(r9)
612 /* Save more register state */
620 stw r7, VCPU_DSISR(r9)
622 /* grab HDAR & HDSISR if HV data storage interrupt (HDSI) */
624 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
626 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
627 7: std r6, VCPU_FAULT_DAR(r9)
628 stw r7, VCPU_FAULT_DSISR(r9)
630 /* Save guest CTRL register, set runlatch to 1 */
638 /* Read the guest SLB and save it away */
639 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
645 andis. r0,r8,SLB_ESID_V@h
647 add r8,r8,r6 /* put index in */
649 std r8,VCPU_SLB_E(r7)
650 std r3,VCPU_SLB_V(r7)
651 addi r7,r7,VCPU_SLB_SIZE
655 stw r5,VCPU_SLB_MAX(r9)
658 * Save the guest PURR/SPURR
666 std r6,VCPU_SPURR(r9)
671 * Restore host PURR/SPURR and add guest times
672 * so that the time in the guest gets accounted.
674 ld r3,HSTATE_PURR(r13)
675 ld r4,HSTATE_SPURR(r13)
680 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
691 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
693 * POWER7 guest -> host partition switch code.
694 * We don't have to lock against tlbies but we do
695 * have to coordinate the hardware threads.
697 /* Increment the threads-exiting-guest count in the 0xff00
698 bits of vcore->entry_exit_count */
700 ld r5,HSTATE_KVM_VCORE(r13)
701 addi r6,r5,VCORE_ENTRY_EXIT
708 * At this point we have an interrupt that we have to pass
709 * up to the kernel or qemu; we can't handle it in real mode.
710 * Thus we have to do a partition switch, so we have to
711 * collect the other threads, if we are the first thread
712 * to take an interrupt. To do this, we set the HDEC to 0,
713 * which causes an HDEC interrupt in all threads within 2ns
714 * because the HDEC register is shared between all 4 threads.
715 * However, we don't need to bother if this is an HDEC
716 * interrupt, since the other threads will already be on their
717 * way here in that case.
719 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
721 cmpwi r3,0x100 /* Are we the first here? */
729 /* Secondary threads wait for primary to do partition switch */
730 ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
731 ld r5,HSTATE_KVM_VCORE(r13)
736 13: lbz r3,VCORE_IN_GUEST(r5)
742 /* Primary thread waits for all the secondaries to exit guest */
743 15: lwz r3,VCORE_ENTRY_EXIT(r5)
750 /* Primary thread switches back to host partition */
751 ld r6,KVM_HOST_SDR1(r4)
752 lwz r7,KVM_HOST_LPID(r4)
753 li r8,LPID_RSVD /* switch to reserved LPID */
756 mtspr SPRN_SDR1,r6 /* switch to partition page table */
760 stb r0,VCORE_IN_GUEST(r5)
761 lis r8,0x7fff /* MAX_INT@h */
764 16: ld r8,KVM_HOST_LPCR(r4)
770 * PPC970 guest -> host partition switch code.
771 * We have to lock against concurrent tlbies, and
772 * we have to flush the whole TLB.
774 32: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
776 /* Take the guest's tlbie_lock */
777 lwz r8,PACA_LOCK_TOKEN(r13)
778 addi r3,r4,KVM_TLBIE_LOCK
786 ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */
788 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
792 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
795 stw r0,0(r3) /* drop guest tlbie_lock */
797 /* invalidate the whole TLB */
806 /* take native_tlbie_lock */
807 ld r3,toc_tlbie_lock@toc(2)
815 ld r6,KVM_HOST_SDR1(r4)
816 mtspr SPRN_SDR1,r6 /* switch to host page table */
818 /* Set up host HID4 value */
823 stw r0,0(r3) /* drop native_tlbie_lock */
825 lis r8,0x7fff /* MAX_INT@h */
828 /* Disable HDEC interrupts */
831 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
841 /* load host SLB entries */
842 33: ld r8,PACA_SLBSHADOWPTR(r13)
845 ld r5,SLBSHADOW_SAVEAREA(r8)
846 ld r6,SLBSHADOW_SAVEAREA+8(r8)
847 andis. r7,r5,SLB_ESID_V@h
853 /* Save and reset AMR and UAMOR before turning on the MMU */
858 std r6,VCPU_UAMOR(r9)
861 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
863 /* Restore host DABR and DABRX */
864 ld r5,HSTATE_DABR(r13)
869 /* Switch DSCR back to host value */
872 ld r7, HSTATE_DSCR(r13)
873 std r8, VCPU_DSCR(r7)
875 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
877 /* Save non-volatile GPRs */
878 std r14, VCPU_GPR(r14)(r9)
879 std r15, VCPU_GPR(r15)(r9)
880 std r16, VCPU_GPR(r16)(r9)
881 std r17, VCPU_GPR(r17)(r9)
882 std r18, VCPU_GPR(r18)(r9)
883 std r19, VCPU_GPR(r19)(r9)
884 std r20, VCPU_GPR(r20)(r9)
885 std r21, VCPU_GPR(r21)(r9)
886 std r22, VCPU_GPR(r22)(r9)
887 std r23, VCPU_GPR(r23)(r9)
888 std r24, VCPU_GPR(r24)(r9)
889 std r25, VCPU_GPR(r25)(r9)
890 std r26, VCPU_GPR(r26)(r9)
891 std r27, VCPU_GPR(r27)(r9)
892 std r28, VCPU_GPR(r28)(r9)
893 std r29, VCPU_GPR(r29)(r9)
894 std r30, VCPU_GPR(r30)(r9)
895 std r31, VCPU_GPR(r31)(r9)
902 std r3, VCPU_SPRG0(r9)
903 std r4, VCPU_SPRG1(r9)
904 std r5, VCPU_SPRG2(r9)
905 std r6, VCPU_SPRG3(r9)
907 /* Increment yield count if they have a VPA */
908 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
911 lwz r3, LPPACA_YIELDCOUNT(r8)
913 stw r3, LPPACA_YIELDCOUNT(r8)
915 /* Save PMU registers if requested */
916 /* r8 and cr0.eq are live here */
918 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
919 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
920 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
922 beq 21f /* if no VPA, save PMU stuff anyway */
923 lbz r7, LPPACA_PMCINUSE(r8)
924 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
926 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
928 21: mfspr r5, SPRN_MMCR1
930 std r4, VCPU_MMCR(r9)
931 std r5, VCPU_MMCR + 8(r9)
932 std r6, VCPU_MMCR + 16(r9)
942 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
944 stw r4, VCPU_PMC + 4(r9)
945 stw r5, VCPU_PMC + 8(r9)
946 stw r6, VCPU_PMC + 12(r9)
947 stw r7, VCPU_PMC + 16(r9)
948 stw r8, VCPU_PMC + 20(r9)
950 stw r10, VCPU_PMC + 24(r9)
951 stw r11, VCPU_PMC + 28(r9)
952 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
958 /* Secondary threads go off to take a nap on POWER7 */
963 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
966 * Reload DEC. HDEC interrupts were disabled when
967 * we reloaded the host's LPCR value.
969 ld r3, HSTATE_DECEXP(r13)
974 /* Reload the host's PMU registers */
975 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
976 lbz r4, LPPACA_PMCINUSE(r3)
978 beq 23f /* skip if not */
979 lwz r3, HSTATE_PMC(r13)
980 lwz r4, HSTATE_PMC + 4(r13)
981 lwz r5, HSTATE_PMC + 8(r13)
982 lwz r6, HSTATE_PMC + 12(r13)
983 lwz r8, HSTATE_PMC + 16(r13)
984 lwz r9, HSTATE_PMC + 20(r13)
986 lwz r10, HSTATE_PMC + 24(r13)
987 lwz r11, HSTATE_PMC + 28(r13)
988 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
998 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
999 ld r3, HSTATE_MMCR(r13)
1000 ld r4, HSTATE_MMCR + 8(r13)
1001 ld r5, HSTATE_MMCR + 16(r13)
1002 mtspr SPRN_MMCR1, r4
1003 mtspr SPRN_MMCRA, r5
1004 mtspr SPRN_MMCR0, r3
1008 * For external and machine check interrupts, we need
1009 * to call the Linux handler to process the interrupt.
1010 * We do that by jumping to the interrupt vector address
1011 * which we have in r12. The [h]rfid at the end of the
1012 * handler will return to the book3s_hv_interrupts.S code.
1013 * For other interrupts we do the rfid to get back
1014 * to the book3s_interrupts.S code here.
1016 ld r8, HSTATE_VMHANDLER(r13)
1017 ld r7, HSTATE_HOST_MSR(r13)
1019 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1021 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1023 /* RFI into the highmem handler, or branch to interrupt handler */
1028 mtmsrd r6, 1 /* Clear RI in MSR */
1037 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1038 mtspr SPRN_HSRR0, r8
1039 mtspr SPRN_HSRR1, r7
1042 6: mfspr r6,SPRN_HDAR
1043 mfspr r7,SPRN_HDSISR
1047 * Try to handle an hcall in real mode.
1048 * Returns to the guest if we handle it, or continues on up to
1049 * the kernel if we can't (i.e. if we don't have a handler for
1050 * it, or if the handler returns H_TOO_HARD).
1052 .globl hcall_try_real_mode
1053 hcall_try_real_mode:
1054 ld r3,VCPU_GPR(r3)(r9)
1058 cmpldi r3,hcall_real_table_end - hcall_real_table
1060 LOAD_REG_ADDR(r4, hcall_real_table)
1066 mr r3,r9 /* get vcpu pointer */
1067 ld r4,VCPU_GPR(r4)(r9)
1070 beq hcall_real_fallback
1071 ld r4,HSTATE_KVM_VCPU(r13)
1072 std r3,VCPU_GPR(r3)(r4)
1077 /* We've attempted a real mode hcall, but it's punted it back
1078 * to userspace. We need to restore some clobbered volatiles
1079 * before resuming the pass-it-to-qemu path */
1080 hcall_real_fallback:
1081 li r12,BOOK3S_INTERRUPT_SYSCALL
1082 ld r9, HSTATE_KVM_VCPU(r13)
1083 ld r11, VCPU_MSR(r9)
1087 .globl hcall_real_table
1089 .long 0 /* 0 - unused */
1090 .long .kvmppc_h_remove - hcall_real_table
1091 .long .kvmppc_h_enter - hcall_real_table
1092 .long .kvmppc_h_read - hcall_real_table
1093 .long 0 /* 0x10 - H_CLEAR_MOD */
1094 .long 0 /* 0x14 - H_CLEAR_REF */
1095 .long .kvmppc_h_protect - hcall_real_table
1096 .long 0 /* 0x1c - H_GET_TCE */
1097 .long .kvmppc_h_put_tce - hcall_real_table
1098 .long 0 /* 0x24 - H_SET_SPRG0 */
1099 .long .kvmppc_h_set_dabr - hcall_real_table
1162 .long .kvmppc_h_bulk_remove - hcall_real_table
1163 hcall_real_table_end:
1169 bounce_ext_interrupt:
1173 li r10,BOOK3S_INTERRUPT_EXTERNAL
1174 LOAD_REG_IMMEDIATE(r11,MSR_SF | MSR_ME);
1177 _GLOBAL(kvmppc_h_set_dabr)
1178 std r4,VCPU_DABR(r3)
1184 ld r5,HSTATE_KVM_VCORE(r13)
1186 13: lbz r3,VCORE_IN_GUEST(r5)
1190 ld r11,PACA_SLBSHADOWPTR(r13)
1192 .rept SLB_NUM_BOLTED
1193 ld r5,SLBSHADOW_SAVEAREA(r11)
1194 ld r6,SLBSHADOW_SAVEAREA+8(r11)
1195 andis. r7,r5,SLB_ESID_V@h
1203 /* Clear any pending IPI */
1204 50: ld r5, HSTATE_XICS_PHYS(r13)
1209 /* increment the nap count and then go to nap mode */
1210 ld r4, HSTATE_KVM_VCORE(r13)
1211 addi r4, r4, VCORE_NAP_COUNT
1212 lwsync /* make previous updates visible */
1222 ori r4, r4, LPCR_PECE0 /* exit nap on interrupt */
1225 std r0, HSTATE_SCRATCH0(r13)
1227 ld r0, HSTATE_SCRATCH0(r13)
1234 * Save away FP, VMX and VSX registers.
1237 _GLOBAL(kvmppc_save_fp)
1240 #ifdef CONFIG_ALTIVEC
1242 oris r8,r8,MSR_VEC@h
1243 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1247 oris r8,r8,MSR_VSX@h
1248 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1256 li r6,reg*16+VCPU_VSRS
1264 stfd reg,reg*8+VCPU_FPRS(r3)
1268 ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
1271 stfd fr0,VCPU_FPSCR(r3)
1273 #ifdef CONFIG_ALTIVEC
1277 li r6,reg*16+VCPU_VRS
1284 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1286 mfspr r6,SPRN_VRSAVE
1287 stw r6,VCPU_VRSAVE(r3)
1293 * Load up FP, VMX and VSX registers
1296 .globl kvmppc_load_fp
1300 #ifdef CONFIG_ALTIVEC
1302 oris r8,r8,MSR_VEC@h
1303 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1307 oris r8,r8,MSR_VSX@h
1308 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1312 lfd fr0,VCPU_FPSCR(r4)
1318 li r7,reg*16+VCPU_VSRS
1326 lfd reg,reg*8+VCPU_FPRS(r4)
1330 ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
1333 #ifdef CONFIG_ALTIVEC
1340 li r7,reg*16+VCPU_VRS
1344 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1346 lwz r7,VCPU_VRSAVE(r4)
1347 mtspr SPRN_VRSAVE,r7