2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/mmu-hash64.h>
32 #ifdef __LITTLE_ENDIAN__
33 #error Need to fix lppaca and SLB shadow accesses in little endian mode
37 * Call kvmppc_hv_entry in real mode.
38 * Must be called with interrupts hard-disabled.
42 * LR = return address to continue at after eventually re-enabling MMU
44 _GLOBAL(kvmppc_hv_entry_trampoline)
46 std r0, PPC_LR_STKOFF(r1)
49 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
54 mtmsrd r0,1 /* clear RI in MSR */
62 /* Back from guest - restore host state and return to caller */
64 /* Restore host DABR and DABRX */
65 ld r5,HSTATE_DABR(r13)
75 * Reload DEC. HDEC interrupts were disabled when
76 * we reloaded the host's LPCR value.
78 ld r3, HSTATE_DECEXP(r13)
83 /* Reload the host's PMU registers */
84 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
85 lbz r4, LPPACA_PMCINUSE(r3)
87 beq 23f /* skip if not */
88 lwz r3, HSTATE_PMC(r13)
89 lwz r4, HSTATE_PMC + 4(r13)
90 lwz r5, HSTATE_PMC + 8(r13)
91 lwz r6, HSTATE_PMC + 12(r13)
92 lwz r8, HSTATE_PMC + 16(r13)
93 lwz r9, HSTATE_PMC + 20(r13)
95 lwz r10, HSTATE_PMC + 24(r13)
96 lwz r11, HSTATE_PMC + 28(r13)
97 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
107 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
108 ld r3, HSTATE_MMCR(r13)
109 ld r4, HSTATE_MMCR + 8(r13)
110 ld r5, HSTATE_MMCR + 16(r13)
118 * For external and machine check interrupts, we need
119 * to call the Linux handler to process the interrupt.
120 * We do that by jumping to absolute address 0x500 for
121 * external interrupts, or the machine_check_fwnmi label
122 * for machine checks (since firmware might have patched
123 * the vector area at 0x200). The [h]rfid at the end of the
124 * handler will return to the book3s_hv_interrupts.S code.
125 * For other interrupts we do the rfid to get back
126 * to the book3s_hv_interrupts.S code here.
128 ld r8, 112+PPC_LR_STKOFF(r1)
130 ld r7, HSTATE_HOST_MSR(r13)
132 cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK
133 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
136 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
138 /* RFI into the highmem handler, or branch to interrupt handler */
142 mtmsrd r6, 1 /* Clear RI in MSR */
145 beqa 0x500 /* external interrupt (PPC970) */
146 beq cr1, 13f /* machine check */
149 /* On POWER7, we have external interrupts set to use HSRR0/1 */
150 11: mtspr SPRN_HSRR0, r8
154 13: b machine_check_fwnmi
157 * We come in here when wakened from nap mode on a secondary hw thread.
158 * Relocation is off and most register values are lost.
159 * r13 points to the PACA.
161 .globl kvm_start_guest
163 ld r1,PACAEMERGSP(r13)
164 subi r1,r1,STACK_FRAME_OVERHEAD
167 li r0,KVM_HWTHREAD_IN_KVM
168 stb r0,HSTATE_HWTHREAD_STATE(r13)
170 /* NV GPR values from power7_idle() will no longer be valid */
172 stb r0,PACA_NAPSTATELOST(r13)
174 /* were we napping due to cede? */
175 lbz r0,HSTATE_NAPPING(r13)
180 * We weren't napping due to cede, so this must be a secondary
181 * thread being woken up to run a guest, or being woken up due
182 * to a stray IPI. (Or due to some machine check or hypervisor
183 * maintenance interrupt while the core is in KVM.)
186 /* Check the wake reason in SRR1 to see why we got here */
188 rlwinm r3,r3,44-31,0x7 /* extract wake reason field */
189 cmpwi r3,4 /* was it an external interrupt? */
191 ld r5,HSTATE_XICS_PHYS(r13)
192 li r7,XICS_XIRR /* if it was an external interrupt, */
193 lwzcix r8,r5,r7 /* get and ack the interrupt */
195 clrldi. r9,r8,40 /* get interrupt source ID. */
196 beq 28f /* none there? */
197 cmpwi r9,XICS_IPI /* was it an IPI? */
201 stbcix r0,r5,r6 /* clear IPI */
202 stwcix r8,r5,r7 /* EOI the interrupt */
203 sync /* order loading of vcpu after that */
205 /* get vcpu pointer, NULL if we have no vcpu to run */
206 ld r4,HSTATE_KVM_VCPU(r13)
208 /* if we have no vcpu to run, go back to sleep */
212 27: /* XXX should handle hypervisor maintenance interrupts etc. here */
214 28: /* SRR1 said external but ICP said nope?? */
216 29: /* External non-IPI interrupt to offline secondary thread? help?? */
217 stw r8,HSTATE_SAVED_XIRR(r13)
220 30: bl kvmppc_hv_entry
222 /* Back from the guest, go back to nap */
223 /* Clear our vcpu pointer so we don't come back in early */
225 std r0, HSTATE_KVM_VCPU(r13)
227 * Make sure we clear HSTATE_KVM_VCPU(r13) before incrementing
228 * the nap_count, because once the increment to nap_count is
229 * visible we could be given another vcpu.
232 /* Clear any pending IPI - we're an offline thread */
233 ld r5, HSTATE_XICS_PHYS(r13)
235 lwzcix r3, r5, r7 /* ack any pending interrupt */
236 rlwinm. r0, r3, 0, 0xffffff /* any pending? */
241 stbcix r0, r5, r6 /* clear the IPI */
242 stwcix r3, r5, r7 /* EOI it */
245 /* increment the nap count and then go to nap mode */
246 ld r4, HSTATE_KVM_VCORE(r13)
247 addi r4, r4, VCORE_NAP_COUNT
254 li r0, KVM_HWTHREAD_IN_NAP
255 stb r0, HSTATE_HWTHREAD_STATE(r13)
258 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
261 std r0, HSTATE_SCRATCH0(r13)
263 ld r0, HSTATE_SCRATCH0(r13)
269 /******************************************************************************
273 *****************************************************************************/
275 .global kvmppc_hv_entry
284 * all other volatile GPRS = free
287 std r0, PPC_LR_STKOFF(r1)
290 /* Set partition DABR */
291 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
298 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
300 /* Load guest PMU registers */
301 /* R4 is live here (vcpu pointer) */
303 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
304 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
306 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
307 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
308 lwz r6, VCPU_PMC + 8(r4)
309 lwz r7, VCPU_PMC + 12(r4)
310 lwz r8, VCPU_PMC + 16(r4)
311 lwz r9, VCPU_PMC + 20(r4)
313 lwz r10, VCPU_PMC + 24(r4)
314 lwz r11, VCPU_PMC + 28(r4)
315 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
325 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
327 ld r5, VCPU_MMCR + 8(r4)
328 ld r6, VCPU_MMCR + 16(r4)
338 /* Load up FP, VMX and VSX registers */
341 ld r14, VCPU_GPR(R14)(r4)
342 ld r15, VCPU_GPR(R15)(r4)
343 ld r16, VCPU_GPR(R16)(r4)
344 ld r17, VCPU_GPR(R17)(r4)
345 ld r18, VCPU_GPR(R18)(r4)
346 ld r19, VCPU_GPR(R19)(r4)
347 ld r20, VCPU_GPR(R20)(r4)
348 ld r21, VCPU_GPR(R21)(r4)
349 ld r22, VCPU_GPR(R22)(r4)
350 ld r23, VCPU_GPR(R23)(r4)
351 ld r24, VCPU_GPR(R24)(r4)
352 ld r25, VCPU_GPR(R25)(r4)
353 ld r26, VCPU_GPR(R26)(r4)
354 ld r27, VCPU_GPR(R27)(r4)
355 ld r28, VCPU_GPR(R28)(r4)
356 ld r29, VCPU_GPR(R29)(r4)
357 ld r30, VCPU_GPR(R30)(r4)
358 ld r31, VCPU_GPR(R31)(r4)
361 /* Switch DSCR to guest value */
364 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
367 * Set the decrementer to the guest decrementer.
369 ld r8,VCPU_DEC_EXPIRES(r4)
375 ld r5, VCPU_SPRG0(r4)
376 ld r6, VCPU_SPRG1(r4)
377 ld r7, VCPU_SPRG2(r4)
378 ld r8, VCPU_SPRG3(r4)
384 /* Save R1 in the PACA */
385 std r1, HSTATE_HOST_R1(r13)
387 /* Load up DAR and DSISR */
389 lwz r6, VCPU_DSISR(r4)
393 li r6, KVM_GUEST_MODE_HOST_HV
394 stb r6, HSTATE_IN_GUEST(r13)
397 /* Restore AMR and UAMOR, set AMOR to all 1s */
404 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
414 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
416 * POWER7 host -> guest partition switch code.
417 * We don't have to lock against concurrent tlbies,
418 * but we do have to coordinate across hardware threads.
420 /* Increment entry count iff exit count is zero. */
421 ld r5,HSTATE_KVM_VCORE(r13)
422 addi r9,r5,VCORE_ENTRY_EXIT
424 cmpwi r3,0x100 /* any threads starting to exit? */
425 bge secondary_too_late /* if so we're too late to the party */
430 /* Primary thread switches to guest partition. */
431 ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
437 li r0,LPID_RSVD /* switch to reserved LPID */
440 mtspr SPRN_SDR1,r6 /* switch to partition page table */
444 /* See if we need to flush the TLB */
445 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
446 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
447 srdi r6,r6,6 /* doubleword number */
448 sldi r6,r6,3 /* address offset */
450 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
456 23: ldarx r7,0,r6 /* if set, clear the bit */
460 li r6,128 /* and flush the TLB */
462 li r7,0x800 /* IS field = 0b10 */
469 /* Add timebase offset onto timebase */
470 22: ld r8,VCORE_TB_OFFSET(r5)
473 mftb r6 /* current host timebase */
475 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
476 mftb r7 /* check if lower 24 bits overflowed */
481 addis r8,r8,0x100 /* if so, increment upper 40 bits */
484 /* Load guest PCR value to select appropriate compat mode */
485 37: ld r7, VCORE_PCR(r5)
491 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
494 /* Secondary threads wait for primary to have done partition switch */
495 20: lbz r0,VCORE_IN_GUEST(r5)
499 /* Set LPCR and RMOR. */
500 10: ld r8,VCORE_LPCR(r5)
506 /* Increment yield count if they have a VPA */
510 lwz r5, LPPACA_YIELDCOUNT(r3)
512 stw r5, LPPACA_YIELDCOUNT(r3)
514 stb r6, VCPU_VPA_DIRTY(r4)
516 /* Check if HDEC expires soon */
519 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
523 /* Save purr/spurr */
526 std r5,HSTATE_PURR(r13)
527 std r6,HSTATE_SPURR(r13)
535 * PPC970 host -> guest partition switch code.
536 * We have to lock against concurrent tlbies,
537 * using native_tlbie_lock to lock against host tlbies
538 * and kvm->arch.tlbie_lock to lock against guest tlbies.
539 * We also have to invalidate the TLB since its
540 * entries aren't tagged with the LPID.
542 30: ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
544 /* first take native_tlbie_lock */
547 .tc native_tlbie_lock[TC],native_tlbie_lock
549 ld r3,toc_tlbie_lock@toc(2)
550 #ifdef __BIG_ENDIAN__
551 lwz r8,PACA_LOCK_TOKEN(r13)
553 lwz r8,PACAPACAINDEX(r13)
562 ld r5,HSTATE_KVM_VCORE(r13)
563 ld r7,VCORE_LPCR(r5) /* use vcore->lpcr to store HID4 */
565 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
569 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
572 stw r0,0(r3) /* drop native_tlbie_lock */
574 /* invalidate the whole TLB */
583 /* Take the guest's tlbie_lock */
584 addi r3,r9,KVM_TLBIE_LOCK
592 mtspr SPRN_SDR1,r6 /* switch to partition page table */
594 /* Set up HID4 with the guest's LPID etc. */
599 /* drop the guest's tlbie_lock */
603 /* Check if HDEC expires soon */
606 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
610 /* Enable HDEC interrupts */
613 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
623 /* Load up guest SLB entries */
624 31: lwz r5,VCPU_SLB_MAX(r4)
629 1: ld r8,VCPU_SLB_E(r6)
632 addi r6,r6,VCPU_SLB_SIZE
636 /* Restore state of CTRL run bit; assume 1 on entry */
652 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
656 /* r11 = vcpu->arch.msr & ~MSR_HV */
657 rldicl r11, r11, 63 - MSR_HV_LG, 1
658 rotldi r11, r11, 1 + MSR_HV_LG
661 /* Check if we can deliver an external or decrementer interrupt now */
662 ld r0,VCPU_PENDING_EXC(r4)
663 lis r8,(1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h
673 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
675 li r0,BOOK3S_INTERRUPT_EXTERNAL
679 li r11,(MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
685 li r0,BOOK3S_INTERRUPT_DECREMENTER
688 /* Move SRR0 and SRR1 into the respective regs */
689 5: mtspr SPRN_SRR0, r6
694 stb r0,VCPU_CEDED(r4) /* cancel cede */
698 /* Activate guest mode, so faults get handled by KVM */
699 li r9, KVM_GUEST_MODE_GUEST_HV
700 stb r9, HSTATE_IN_GUEST(r13)
707 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
710 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
717 ld r1, VCPU_GPR(R1)(r4)
718 ld r2, VCPU_GPR(R2)(r4)
719 ld r3, VCPU_GPR(R3)(r4)
720 ld r5, VCPU_GPR(R5)(r4)
721 ld r6, VCPU_GPR(R6)(r4)
722 ld r7, VCPU_GPR(R7)(r4)
723 ld r8, VCPU_GPR(R8)(r4)
724 ld r9, VCPU_GPR(R9)(r4)
725 ld r10, VCPU_GPR(R10)(r4)
726 ld r11, VCPU_GPR(R11)(r4)
727 ld r12, VCPU_GPR(R12)(r4)
728 ld r13, VCPU_GPR(R13)(r4)
732 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
733 ld r0, VCPU_GPR(R0)(r4)
734 ld r4, VCPU_GPR(R4)(r4)
739 /******************************************************************************
743 *****************************************************************************/
746 * We come here from the first-level interrupt handlers.
748 .globl kvmppc_interrupt_hv
752 * R12 = interrupt vector
754 * guest CR, R12 saved in shadow VCPU SCRATCH1/0
755 * guest R13 saved in SPRN_SCRATCH0
757 std r9, HSTATE_SCRATCH2(r13)
759 lbz r9, HSTATE_IN_GUEST(r13)
760 cmpwi r9, KVM_GUEST_MODE_HOST_HV
761 beq kvmppc_bad_host_intr
762 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
763 cmpwi r9, KVM_GUEST_MODE_GUEST
764 ld r9, HSTATE_SCRATCH2(r13)
765 beq kvmppc_interrupt_pr
767 /* We're now back in the host but in guest MMU context */
768 li r9, KVM_GUEST_MODE_HOST_HV
769 stb r9, HSTATE_IN_GUEST(r13)
771 ld r9, HSTATE_KVM_VCPU(r13)
775 std r0, VCPU_GPR(R0)(r9)
776 std r1, VCPU_GPR(R1)(r9)
777 std r2, VCPU_GPR(R2)(r9)
778 std r3, VCPU_GPR(R3)(r9)
779 std r4, VCPU_GPR(R4)(r9)
780 std r5, VCPU_GPR(R5)(r9)
781 std r6, VCPU_GPR(R6)(r9)
782 std r7, VCPU_GPR(R7)(r9)
783 std r8, VCPU_GPR(R8)(r9)
784 ld r0, HSTATE_SCRATCH2(r13)
785 std r0, VCPU_GPR(R9)(r9)
786 std r10, VCPU_GPR(R10)(r9)
787 std r11, VCPU_GPR(R11)(r9)
788 ld r3, HSTATE_SCRATCH0(r13)
789 lwz r4, HSTATE_SCRATCH1(r13)
790 std r3, VCPU_GPR(R12)(r9)
793 ld r3, HSTATE_CFAR(r13)
794 std r3, VCPU_CFAR(r9)
795 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
797 ld r4, HSTATE_PPR(r13)
799 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
801 /* Restore R1/R2 so we can handle faults */
802 ld r1, HSTATE_HOST_R1(r13)
807 std r10, VCPU_SRR0(r9)
808 std r11, VCPU_SRR1(r9)
809 andi. r0, r12, 2 /* need to read HSRR0/1? */
811 mfspr r10, SPRN_HSRR0
812 mfspr r11, SPRN_HSRR1
814 1: std r10, VCPU_PC(r9)
815 std r11, VCPU_MSR(r9)
819 std r3, VCPU_GPR(R13)(r9)
822 stw r12,VCPU_TRAP(r9)
824 /* Save HEIR (HV emulation assist reg) in last_inst
825 if this is an HEI (HV emulation interrupt, e40) */
826 li r3,KVM_INST_FETCH_FAILED
828 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
831 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
832 11: stw r3,VCPU_LAST_INST(r9)
834 /* these are volatile across C function calls */
841 /* If this is a page table miss then see if it's theirs or ours */
842 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
844 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
846 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
848 /* See if this is a leftover HDEC interrupt */
849 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
855 /* See if this is an hcall we can handle in real mode */
856 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
857 beq hcall_try_real_mode
859 /* Only handle external interrupts here on arch 206 and later */
861 b ext_interrupt_to_host
862 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
864 /* External interrupt ? */
865 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
866 bne+ ext_interrupt_to_host
868 /* External interrupt, first check for host_ipi. If this is
869 * set, we know the host wants us out so let's do it now
874 bgt ext_interrupt_to_host
876 /* Allright, looks like an IPI for the guest, we need to set MER */
877 /* Check if any CPU is heading out to the host, if so head out too */
878 ld r5, HSTATE_KVM_VCORE(r13)
879 lwz r0, VCORE_ENTRY_EXIT(r5)
881 bge ext_interrupt_to_host
883 /* See if there is a pending interrupt for the guest */
885 ld r0, VCPU_PENDING_EXC(r9)
886 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
887 rldicl. r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
888 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
891 /* And if the guest EE is set, we can deliver immediately, else
892 * we return to the guest with MER set
894 andi. r0, r11, MSR_EE
898 li r10, BOOK3S_INTERRUPT_EXTERNAL
899 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
905 ext_interrupt_to_host:
907 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
908 /* Save more register state */
912 stw r7, VCPU_DSISR(r9)
914 /* don't overwrite fault_dar/fault_dsisr if HDSI */
915 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
917 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
918 std r6, VCPU_FAULT_DAR(r9)
919 stw r7, VCPU_FAULT_DSISR(r9)
921 /* See if it is a machine check */
922 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
923 beq machine_check_realmode
926 /* Save guest CTRL register, set runlatch to 1 */
927 6: mfspr r6,SPRN_CTRLF
934 /* Read the guest SLB and save it away */
935 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
941 andis. r0,r8,SLB_ESID_V@h
943 add r8,r8,r6 /* put index in */
945 std r8,VCPU_SLB_E(r7)
946 std r3,VCPU_SLB_V(r7)
947 addi r7,r7,VCPU_SLB_SIZE
951 stw r5,VCPU_SLB_MAX(r9)
954 * Save the guest PURR/SPURR
962 std r6,VCPU_SPURR(r9)
967 * Restore host PURR/SPURR and add guest times
968 * so that the time in the guest gets accounted.
970 ld r3,HSTATE_PURR(r13)
971 ld r4,HSTATE_SPURR(r13)
976 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
984 hdec_soon: /* r9 = vcpu, r12 = trap, r13 = paca */
987 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
989 * POWER7 guest -> host partition switch code.
990 * We don't have to lock against tlbies but we do
991 * have to coordinate the hardware threads.
993 /* Increment the threads-exiting-guest count in the 0xff00
994 bits of vcore->entry_exit_count */
995 ld r5,HSTATE_KVM_VCORE(r13)
996 addi r6,r5,VCORE_ENTRY_EXIT
1001 isync /* order stwcx. vs. reading napping_threads */
1004 * At this point we have an interrupt that we have to pass
1005 * up to the kernel or qemu; we can't handle it in real mode.
1006 * Thus we have to do a partition switch, so we have to
1007 * collect the other threads, if we are the first thread
1008 * to take an interrupt. To do this, we set the HDEC to 0,
1009 * which causes an HDEC interrupt in all threads within 2ns
1010 * because the HDEC register is shared between all 4 threads.
1011 * However, we don't need to bother if this is an HDEC
1012 * interrupt, since the other threads will already be on their
1013 * way here in that case.
1015 cmpwi r3,0x100 /* Are we the first here? */
1017 cmpwi r3,1 /* Are any other threads in the guest? */
1019 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1025 * Send an IPI to any napping threads, since an HDEC interrupt
1026 * doesn't wake CPUs up from nap.
1028 lwz r3,VCORE_NAPPING_THREADS(r5)
1029 lwz r4,VCPU_PTID(r9)
1032 andc. r3,r3,r0 /* no sense IPI'ing ourselves */
1034 /* Order entry/exit update vs. IPIs */
1036 mulli r4,r4,PACA_SIZE /* get paca for thread 0 */
1040 ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */
1043 stbcix r0,r7,r8 /* trigger the IPI */
1045 addi r6,r6,PACA_SIZE
1048 /* Secondary threads wait for primary to do partition switch */
1049 43: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
1050 ld r5,HSTATE_KVM_VCORE(r13)
1051 lwz r3,VCPU_PTID(r9)
1055 13: lbz r3,VCORE_IN_GUEST(r5)
1061 /* Primary thread waits for all the secondaries to exit guest */
1062 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1069 /* Primary thread switches back to host partition */
1070 ld r6,KVM_HOST_SDR1(r4)
1071 lwz r7,KVM_HOST_LPID(r4)
1072 li r8,LPID_RSVD /* switch to reserved LPID */
1075 mtspr SPRN_SDR1,r6 /* switch to partition page table */
1079 /* Subtract timebase offset from timebase */
1080 ld r8,VCORE_TB_OFFSET(r5)
1083 mftb r6 /* current host timebase */
1085 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1086 mftb r7 /* check if lower 24 bits overflowed */
1091 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1095 17: ld r0, VCORE_PCR(r5)
1101 /* Signal secondary CPUs to continue */
1102 stb r0,VCORE_IN_GUEST(r5)
1103 lis r8,0x7fff /* MAX_INT@h */
1106 16: ld r8,KVM_HOST_LPCR(r4)
1112 * PPC970 guest -> host partition switch code.
1113 * We have to lock against concurrent tlbies, and
1114 * we have to flush the whole TLB.
1116 32: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
1118 /* Take the guest's tlbie_lock */
1119 #ifdef __BIG_ENDIAN__
1120 lwz r8,PACA_LOCK_TOKEN(r13)
1122 lwz r8,PACAPACAINDEX(r13)
1124 addi r3,r4,KVM_TLBIE_LOCK
1132 ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */
1134 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
1138 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
1141 stw r0,0(r3) /* drop guest tlbie_lock */
1143 /* invalidate the whole TLB */
1152 /* take native_tlbie_lock */
1153 ld r3,toc_tlbie_lock@toc(2)
1161 ld r6,KVM_HOST_SDR1(r4)
1162 mtspr SPRN_SDR1,r6 /* switch to host page table */
1164 /* Set up host HID4 value */
1169 stw r0,0(r3) /* drop native_tlbie_lock */
1171 lis r8,0x7fff /* MAX_INT@h */
1174 /* Disable HDEC interrupts */
1177 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
1187 /* load host SLB entries */
1188 33: ld r8,PACA_SLBSHADOWPTR(r13)
1190 .rept SLB_NUM_BOLTED
1191 ld r5,SLBSHADOW_SAVEAREA(r8)
1192 ld r6,SLBSHADOW_SAVEAREA+8(r8)
1193 andis. r7,r5,SLB_ESID_V@h
1204 std r5,VCPU_DEC_EXPIRES(r9)
1206 /* Save and reset AMR and UAMOR before turning on the MMU */
1211 std r6,VCPU_UAMOR(r9)
1214 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1216 /* Unset guest mode */
1217 li r0, KVM_GUEST_MODE_NONE
1218 stb r0, HSTATE_IN_GUEST(r13)
1220 /* Switch DSCR back to host value */
1223 ld r7, HSTATE_DSCR(r13)
1224 std r8, VCPU_DSCR(r9)
1226 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1228 /* Save non-volatile GPRs */
1229 std r14, VCPU_GPR(R14)(r9)
1230 std r15, VCPU_GPR(R15)(r9)
1231 std r16, VCPU_GPR(R16)(r9)
1232 std r17, VCPU_GPR(R17)(r9)
1233 std r18, VCPU_GPR(R18)(r9)
1234 std r19, VCPU_GPR(R19)(r9)
1235 std r20, VCPU_GPR(R20)(r9)
1236 std r21, VCPU_GPR(R21)(r9)
1237 std r22, VCPU_GPR(R22)(r9)
1238 std r23, VCPU_GPR(R23)(r9)
1239 std r24, VCPU_GPR(R24)(r9)
1240 std r25, VCPU_GPR(R25)(r9)
1241 std r26, VCPU_GPR(R26)(r9)
1242 std r27, VCPU_GPR(R27)(r9)
1243 std r28, VCPU_GPR(R28)(r9)
1244 std r29, VCPU_GPR(R29)(r9)
1245 std r30, VCPU_GPR(R30)(r9)
1246 std r31, VCPU_GPR(R31)(r9)
1249 mfspr r3, SPRN_SPRG0
1250 mfspr r4, SPRN_SPRG1
1251 mfspr r5, SPRN_SPRG2
1252 mfspr r6, SPRN_SPRG3
1253 std r3, VCPU_SPRG0(r9)
1254 std r4, VCPU_SPRG1(r9)
1255 std r5, VCPU_SPRG2(r9)
1256 std r6, VCPU_SPRG3(r9)
1262 /* Increment yield count if they have a VPA */
1263 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1266 lwz r3, LPPACA_YIELDCOUNT(r8)
1268 stw r3, LPPACA_YIELDCOUNT(r8)
1270 stb r3, VCPU_VPA_DIRTY(r9)
1272 /* Save PMU registers if requested */
1273 /* r8 and cr0.eq are live here */
1275 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1276 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1277 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1278 mfspr r6, SPRN_MMCRA
1280 /* On P7, clear MMCRA in order to disable SDAR updates */
1282 mtspr SPRN_MMCRA, r7
1283 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1285 beq 21f /* if no VPA, save PMU stuff anyway */
1286 lbz r7, LPPACA_PMCINUSE(r8)
1287 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1289 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1291 21: mfspr r5, SPRN_MMCR1
1294 std r4, VCPU_MMCR(r9)
1295 std r5, VCPU_MMCR + 8(r9)
1296 std r6, VCPU_MMCR + 16(r9)
1297 std r7, VCPU_SIAR(r9)
1298 std r8, VCPU_SDAR(r9)
1306 mfspr r10, SPRN_PMC7
1307 mfspr r11, SPRN_PMC8
1308 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1309 stw r3, VCPU_PMC(r9)
1310 stw r4, VCPU_PMC + 4(r9)
1311 stw r5, VCPU_PMC + 8(r9)
1312 stw r6, VCPU_PMC + 12(r9)
1313 stw r7, VCPU_PMC + 16(r9)
1314 stw r8, VCPU_PMC + 20(r9)
1316 stw r10, VCPU_PMC + 24(r9)
1317 stw r11, VCPU_PMC + 28(r9)
1318 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1320 ld r0, 112+PPC_LR_STKOFF(r1)
1325 ld r5,HSTATE_KVM_VCORE(r13)
1327 13: lbz r3,VCORE_IN_GUEST(r5)
1331 li r0, KVM_GUEST_MODE_NONE
1332 stb r0, HSTATE_IN_GUEST(r13)
1333 ld r11,PACA_SLBSHADOWPTR(r13)
1335 .rept SLB_NUM_BOLTED
1336 ld r5,SLBSHADOW_SAVEAREA(r11)
1337 ld r6,SLBSHADOW_SAVEAREA+8(r11)
1338 andis. r7,r5,SLB_ESID_V@h
1346 * Check whether an HDSI is an HPTE not found fault or something else.
1347 * If it is an HPTE not found fault that is due to the guest accessing
1348 * a page that they have mapped but which we have paged out, then
1349 * we continue on with the guest exit path. In all other cases,
1350 * reflect the HDSI to the guest as a DSI.
1354 mfspr r6, SPRN_HDSISR
1355 /* HPTE not found fault or protection fault? */
1356 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1357 beq 1f /* if not, send it to the guest */
1358 andi. r0, r11, MSR_DR /* data relocation enabled? */
1361 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1362 bne 1f /* if no SLB entry found */
1363 4: std r4, VCPU_FAULT_DAR(r9)
1364 stw r6, VCPU_FAULT_DSISR(r9)
1366 /* Search the hash table. */
1367 mr r3, r9 /* vcpu pointer */
1368 li r7, 1 /* data fault */
1369 bl .kvmppc_hpte_hv_fault
1370 ld r9, HSTATE_KVM_VCPU(r13)
1372 ld r11, VCPU_MSR(r9)
1373 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1374 cmpdi r3, 0 /* retry the instruction */
1376 cmpdi r3, -1 /* handle in kernel mode */
1378 cmpdi r3, -2 /* MMIO emulation; need instr word */
1381 /* Synthesize a DSI for the guest */
1382 ld r4, VCPU_FAULT_DAR(r9)
1384 1: mtspr SPRN_DAR, r4
1385 mtspr SPRN_DSISR, r6
1386 mtspr SPRN_SRR0, r10
1387 mtspr SPRN_SRR1, r11
1388 li r10, BOOK3S_INTERRUPT_DATA_STORAGE
1389 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1391 fast_interrupt_c_return:
1392 6: ld r7, VCPU_CTR(r9)
1393 lwz r8, VCPU_XER(r9)
1399 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1400 ld r5, KVM_VRMA_SLB_V(r5)
1403 /* If this is for emulated MMIO, load the instruction word */
1404 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1406 /* Set guest mode to 'jump over instruction' so if lwz faults
1407 * we'll just continue at the next IP. */
1408 li r0, KVM_GUEST_MODE_SKIP
1409 stb r0, HSTATE_IN_GUEST(r13)
1411 /* Do the access with MSR:DR enabled */
1413 ori r4, r3, MSR_DR /* Enable paging for data */
1418 /* Store the result */
1419 stw r8, VCPU_LAST_INST(r9)
1421 /* Unset guest mode. */
1422 li r0, KVM_GUEST_MODE_HOST_HV
1423 stb r0, HSTATE_IN_GUEST(r13)
1427 * Similarly for an HISI, reflect it to the guest as an ISI unless
1428 * it is an HPTE not found fault for a page that we have paged out.
1431 andis. r0, r11, SRR1_ISI_NOPT@h
1433 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1436 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1437 bne 1f /* if no SLB entry found */
1439 /* Search the hash table. */
1440 mr r3, r9 /* vcpu pointer */
1443 li r7, 0 /* instruction fault */
1444 bl .kvmppc_hpte_hv_fault
1445 ld r9, HSTATE_KVM_VCPU(r13)
1447 ld r11, VCPU_MSR(r9)
1448 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1449 cmpdi r3, 0 /* retry the instruction */
1450 beq fast_interrupt_c_return
1451 cmpdi r3, -1 /* handle in kernel mode */
1454 /* Synthesize an ISI for the guest */
1456 1: mtspr SPRN_SRR0, r10
1457 mtspr SPRN_SRR1, r11
1458 li r10, BOOK3S_INTERRUPT_INST_STORAGE
1459 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1461 b fast_interrupt_c_return
1463 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1464 ld r5, KVM_VRMA_SLB_V(r6)
1468 * Try to handle an hcall in real mode.
1469 * Returns to the guest if we handle it, or continues on up to
1470 * the kernel if we can't (i.e. if we don't have a handler for
1471 * it, or if the handler returns H_TOO_HARD).
1473 .globl hcall_try_real_mode
1474 hcall_try_real_mode:
1475 ld r3,VCPU_GPR(R3)(r9)
1479 cmpldi r3,hcall_real_table_end - hcall_real_table
1481 LOAD_REG_ADDR(r4, hcall_real_table)
1487 mr r3,r9 /* get vcpu pointer */
1488 ld r4,VCPU_GPR(R4)(r9)
1491 beq hcall_real_fallback
1492 ld r4,HSTATE_KVM_VCPU(r13)
1493 std r3,VCPU_GPR(R3)(r4)
1498 /* We've attempted a real mode hcall, but it's punted it back
1499 * to userspace. We need to restore some clobbered volatiles
1500 * before resuming the pass-it-to-qemu path */
1501 hcall_real_fallback:
1502 li r12,BOOK3S_INTERRUPT_SYSCALL
1503 ld r9, HSTATE_KVM_VCPU(r13)
1507 .globl hcall_real_table
1509 .long 0 /* 0 - unused */
1510 .long .kvmppc_h_remove - hcall_real_table
1511 .long .kvmppc_h_enter - hcall_real_table
1512 .long .kvmppc_h_read - hcall_real_table
1513 .long 0 /* 0x10 - H_CLEAR_MOD */
1514 .long 0 /* 0x14 - H_CLEAR_REF */
1515 .long .kvmppc_h_protect - hcall_real_table
1516 .long 0 /* 0x1c - H_GET_TCE */
1517 .long .kvmppc_h_put_tce - hcall_real_table
1518 .long 0 /* 0x24 - H_SET_SPRG0 */
1519 .long .kvmppc_h_set_dabr - hcall_real_table
1534 #ifdef CONFIG_KVM_XICS
1535 .long .kvmppc_rm_h_eoi - hcall_real_table
1536 .long .kvmppc_rm_h_cppr - hcall_real_table
1537 .long .kvmppc_rm_h_ipi - hcall_real_table
1538 .long 0 /* 0x70 - H_IPOLL */
1539 .long .kvmppc_rm_h_xirr - hcall_real_table
1541 .long 0 /* 0x64 - H_EOI */
1542 .long 0 /* 0x68 - H_CPPR */
1543 .long 0 /* 0x6c - H_IPI */
1544 .long 0 /* 0x70 - H_IPOLL */
1545 .long 0 /* 0x74 - H_XIRR */
1573 .long .kvmppc_h_cede - hcall_real_table
1590 .long .kvmppc_h_bulk_remove - hcall_real_table
1591 hcall_real_table_end:
1597 _GLOBAL(kvmppc_h_set_dabr)
1598 std r4,VCPU_DABR(r3)
1599 /* Work around P7 bug where DABR can get corrupted on mtspr */
1600 1: mtspr SPRN_DABR,r4
1608 _GLOBAL(kvmppc_h_cede)
1610 std r11,VCPU_MSR(r3)
1612 stb r0,VCPU_CEDED(r3)
1613 sync /* order setting ceded vs. testing prodded */
1614 lbz r5,VCPU_PRODDED(r3)
1616 bne kvm_cede_prodded
1617 li r0,0 /* set trap to 0 to say hcall is handled */
1618 stw r0,VCPU_TRAP(r3)
1620 std r0,VCPU_GPR(R3)(r3)
1622 b kvm_cede_exit /* just send it up to host on 970 */
1623 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
1626 * Set our bit in the bitmask of napping threads unless all the
1627 * other threads are already napping, in which case we send this
1630 ld r5,HSTATE_KVM_VCORE(r13)
1631 lwz r6,VCPU_PTID(r3)
1632 lwz r8,VCORE_ENTRY_EXIT(r5)
1636 addi r6,r5,VCORE_NAPPING_THREADS
1644 /* order napping_threads update vs testing entry_exit_count */
1647 stb r0,HSTATE_NAPPING(r13)
1649 lwz r7,VCORE_ENTRY_EXIT(r5)
1651 bge 33f /* another thread already exiting */
1654 * Although not specifically required by the architecture, POWER7
1655 * preserves the following registers in nap mode, even if an SMT mode
1656 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
1657 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
1659 /* Save non-volatile GPRs */
1660 std r14, VCPU_GPR(R14)(r3)
1661 std r15, VCPU_GPR(R15)(r3)
1662 std r16, VCPU_GPR(R16)(r3)
1663 std r17, VCPU_GPR(R17)(r3)
1664 std r18, VCPU_GPR(R18)(r3)
1665 std r19, VCPU_GPR(R19)(r3)
1666 std r20, VCPU_GPR(R20)(r3)
1667 std r21, VCPU_GPR(R21)(r3)
1668 std r22, VCPU_GPR(R22)(r3)
1669 std r23, VCPU_GPR(R23)(r3)
1670 std r24, VCPU_GPR(R24)(r3)
1671 std r25, VCPU_GPR(R25)(r3)
1672 std r26, VCPU_GPR(R26)(r3)
1673 std r27, VCPU_GPR(R27)(r3)
1674 std r28, VCPU_GPR(R28)(r3)
1675 std r29, VCPU_GPR(R29)(r3)
1676 std r30, VCPU_GPR(R30)(r3)
1677 std r31, VCPU_GPR(R31)(r3)
1683 * Take a nap until a decrementer or external interrupt occurs,
1684 * with PECE1 (wake on decr) and PECE0 (wake on external) set in LPCR
1687 stb r0,HSTATE_HWTHREAD_REQ(r13)
1689 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
1693 std r0, HSTATE_SCRATCH0(r13)
1695 ld r0, HSTATE_SCRATCH0(r13)
1702 /* get vcpu pointer */
1703 ld r4, HSTATE_KVM_VCPU(r13)
1705 /* Woken by external or decrementer interrupt */
1706 ld r1, HSTATE_HOST_R1(r13)
1708 /* load up FP state */
1712 ld r14, VCPU_GPR(R14)(r4)
1713 ld r15, VCPU_GPR(R15)(r4)
1714 ld r16, VCPU_GPR(R16)(r4)
1715 ld r17, VCPU_GPR(R17)(r4)
1716 ld r18, VCPU_GPR(R18)(r4)
1717 ld r19, VCPU_GPR(R19)(r4)
1718 ld r20, VCPU_GPR(R20)(r4)
1719 ld r21, VCPU_GPR(R21)(r4)
1720 ld r22, VCPU_GPR(R22)(r4)
1721 ld r23, VCPU_GPR(R23)(r4)
1722 ld r24, VCPU_GPR(R24)(r4)
1723 ld r25, VCPU_GPR(R25)(r4)
1724 ld r26, VCPU_GPR(R26)(r4)
1725 ld r27, VCPU_GPR(R27)(r4)
1726 ld r28, VCPU_GPR(R28)(r4)
1727 ld r29, VCPU_GPR(R29)(r4)
1728 ld r30, VCPU_GPR(R30)(r4)
1729 ld r31, VCPU_GPR(R31)(r4)
1731 /* clear our bit in vcore->napping_threads */
1732 33: ld r5,HSTATE_KVM_VCORE(r13)
1733 lwz r3,VCPU_PTID(r4)
1736 addi r6,r5,VCORE_NAPPING_THREADS
1742 stb r0,HSTATE_NAPPING(r13)
1744 /* Check the wake reason in SRR1 to see why we got here */
1746 rlwinm r3, r3, 44-31, 0x7 /* extract wake reason field */
1747 cmpwi r3, 4 /* was it an external interrupt? */
1748 li r12, BOOK3S_INTERRUPT_EXTERNAL
1751 ld r11, VCPU_MSR(r9)
1752 beq do_ext_interrupt /* if so */
1754 /* see if any other thread is already exiting */
1755 lwz r0,VCORE_ENTRY_EXIT(r5)
1757 blt kvmppc_cede_reentry /* if not go back to guest */
1759 /* some threads are exiting, so go to the guest exit path */
1760 b hcall_real_fallback
1762 /* cede when already previously prodded case */
1765 stb r0,VCPU_PRODDED(r3)
1766 sync /* order testing prodded vs. clearing ceded */
1767 stb r0,VCPU_CEDED(r3)
1771 /* we've ceded but we want to give control to the host */
1773 b hcall_real_fallback
1775 /* Try to handle a machine check in real mode */
1776 machine_check_realmode:
1777 mr r3, r9 /* get vcpu pointer */
1778 bl .kvmppc_realmode_machine_check
1780 cmpdi r3, 0 /* continue exiting from guest? */
1781 ld r9, HSTATE_KVM_VCPU(r13)
1782 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1784 /* If not, deliver a machine check. SRR0/1 are already set */
1785 li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
1786 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1788 b fast_interrupt_c_return
1791 * Determine what sort of external interrupt is pending (if any).
1793 * 0 if no interrupt is pending
1794 * 1 if an interrupt is pending that needs to be handled by the host
1795 * -1 if there was a guest wakeup IPI (which has now been cleared)
1798 /* see if a host IPI is pending */
1800 lbz r0, HSTATE_HOST_IPI(r13)
1804 /* Now read the interrupt from the ICP */
1805 ld r6, HSTATE_XICS_PHYS(r13)
1810 rlwinm. r3, r0, 0, 0xffffff
1812 beq 1f /* if nothing pending in the ICP */
1814 /* We found something in the ICP...
1816 * If it's not an IPI, stash it in the PACA and return to
1817 * the host, we don't (yet) handle directing real external
1818 * interrupts directly to the guest
1820 cmpwi r3, XICS_IPI /* if there is, is it an IPI? */
1824 /* It's an IPI, clear the MFRR and EOI it */
1827 stbcix r3, r6, r8 /* clear the IPI */
1828 stwcix r0, r6, r7 /* EOI it */
1831 /* We need to re-check host IPI now in case it got set in the
1832 * meantime. If it's clear, we bounce the interrupt to the
1835 lbz r0, HSTATE_HOST_IPI(r13)
1839 /* OK, it's an IPI for us */
1843 42: /* It's not an IPI and it's for the host, stash it in the PACA
1844 * before exit, it will be picked up by the host ICP driver
1846 stw r0, HSTATE_SAVED_XIRR(r13)
1849 43: /* We raced with the host, we need to resend that IPI, bummer */
1851 stbcix r0, r6, r8 /* set the IPI */
1856 * Save away FP, VMX and VSX registers.
1859 _GLOBAL(kvmppc_save_fp)
1862 #ifdef CONFIG_ALTIVEC
1864 oris r8,r8,MSR_VEC@h
1865 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1869 oris r8,r8,MSR_VSX@h
1870 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1878 li r6,reg*16+VCPU_VSRS
1886 stfd reg,reg*8+VCPU_FPRS(r3)
1890 ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
1893 stfd fr0,VCPU_FPSCR(r3)
1895 #ifdef CONFIG_ALTIVEC
1899 li r6,reg*16+VCPU_VRS
1906 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1908 mfspr r6,SPRN_VRSAVE
1909 stw r6,VCPU_VRSAVE(r3)
1915 * Load up FP, VMX and VSX registers
1918 .globl kvmppc_load_fp
1922 #ifdef CONFIG_ALTIVEC
1924 oris r8,r8,MSR_VEC@h
1925 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1929 oris r8,r8,MSR_VSX@h
1930 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1934 lfd fr0,VCPU_FPSCR(r4)
1940 li r7,reg*16+VCPU_VSRS
1948 lfd reg,reg*8+VCPU_FPRS(r4)
1952 ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
1955 #ifdef CONFIG_ALTIVEC
1962 li r7,reg*16+VCPU_VRS
1966 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1968 lwz r7,VCPU_VRSAVE(r4)
1969 mtspr SPRN_VRSAVE,r7
1973 * We come here if we get any exception or interrupt while we are
1974 * executing host real mode code while in guest MMU context.
1975 * For now just spin, but we should do something better.
1977 kvmppc_bad_host_intr: