2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/mmu-hash64.h>
33 #define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM)
35 /* Values in HSTATE_NAPPING(r13) */
36 #define NAPPING_CEDE 1
37 #define NAPPING_NOVCPU 2
40 * Call kvmppc_hv_entry in real mode.
41 * Must be called with interrupts hard-disabled.
45 * LR = return address to continue at after eventually re-enabling MMU
47 _GLOBAL_TOC(kvmppc_hv_entry_trampoline)
49 std r0, PPC_LR_STKOFF(r1)
52 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
57 mtmsrd r0,1 /* clear RI in MSR */
63 ld r4, HSTATE_KVM_VCPU(r13)
66 /* Back from guest - restore host state and return to caller */
69 /* Restore host DABR and DABRX */
70 ld r5,HSTATE_DABR(r13)
74 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
77 ld r3,PACA_SPRG_VDSO(r13)
78 mtspr SPRN_SPRG_VDSO_WRITE,r3
80 /* Reload the host's PMU registers */
81 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
82 lbz r4, LPPACA_PMCINUSE(r3)
84 beq 23f /* skip if not */
86 ld r3, HSTATE_MMCR(r13)
87 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
90 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
91 lwz r3, HSTATE_PMC(r13)
92 lwz r4, HSTATE_PMC + 4(r13)
93 lwz r5, HSTATE_PMC + 8(r13)
94 lwz r6, HSTATE_PMC + 12(r13)
95 lwz r8, HSTATE_PMC + 16(r13)
96 lwz r9, HSTATE_PMC + 20(r13)
98 lwz r10, HSTATE_PMC + 24(r13)
99 lwz r11, HSTATE_PMC + 28(r13)
100 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
110 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
111 ld r3, HSTATE_MMCR(r13)
112 ld r4, HSTATE_MMCR + 8(r13)
113 ld r5, HSTATE_MMCR + 16(r13)
114 ld r6, HSTATE_MMCR + 24(r13)
115 ld r7, HSTATE_MMCR + 32(r13)
121 ld r8, HSTATE_MMCR + 40(r13)
122 ld r9, HSTATE_MMCR + 48(r13)
125 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
131 * Reload DEC. HDEC interrupts were disabled when
132 * we reloaded the host's LPCR value.
134 ld r3, HSTATE_DECEXP(r13)
140 * For external and machine check interrupts, we need
141 * to call the Linux handler to process the interrupt.
142 * We do that by jumping to absolute address 0x500 for
143 * external interrupts, or the machine_check_fwnmi label
144 * for machine checks (since firmware might have patched
145 * the vector area at 0x200). The [h]rfid at the end of the
146 * handler will return to the book3s_hv_interrupts.S code.
147 * For other interrupts we do the rfid to get back
148 * to the book3s_hv_interrupts.S code here.
150 ld r8, 112+PPC_LR_STKOFF(r1)
152 ld r7, HSTATE_HOST_MSR(r13)
154 cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK
155 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
158 cmpwi cr2, r12, BOOK3S_INTERRUPT_HMI
159 beq cr2, 14f /* HMI check */
160 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
162 /* RFI into the highmem handler, or branch to interrupt handler */
166 mtmsrd r6, 1 /* Clear RI in MSR */
169 beqa 0x500 /* external interrupt (PPC970) */
170 beq cr1, 13f /* machine check */
173 /* On POWER7, we have external interrupts set to use HSRR0/1 */
174 11: mtspr SPRN_HSRR0, r8
178 13: b machine_check_fwnmi
180 14: mtspr SPRN_HSRR0, r8
182 b hmi_exception_after_realmode
184 kvmppc_primary_no_guest:
185 /* We handle this much like a ceded vcpu */
186 /* set our bit in napping_threads */
187 ld r5, HSTATE_KVM_VCORE(r13)
188 lbz r7, HSTATE_PTID(r13)
191 addi r6, r5, VCORE_NAPPING_THREADS
196 /* order napping_threads update vs testing entry_exit_count */
199 lwz r7, VCORE_ENTRY_EXIT(r5)
201 bge kvm_novcpu_exit /* another thread already exiting */
202 li r3, NAPPING_NOVCPU
203 stb r3, HSTATE_NAPPING(r13)
208 ld r1, HSTATE_HOST_R1(r13)
209 ld r5, HSTATE_KVM_VCORE(r13)
211 stb r0, HSTATE_NAPPING(r13)
212 stb r0, HSTATE_HWTHREAD_REQ(r13)
214 /* check the wake reason */
215 bl kvmppc_check_wake_reason
217 /* see if any other thread is already exiting */
218 lwz r0, VCORE_ENTRY_EXIT(r5)
222 /* clear our bit in napping_threads */
223 lbz r7, HSTATE_PTID(r13)
226 addi r6, r5, VCORE_NAPPING_THREADS
232 /* See if the wake reason means we need to exit */
236 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
237 ld r4, HSTATE_KVM_VCPU(r13)
245 * We come in here when wakened from nap mode.
246 * Relocation is off and most register values are lost.
247 * r13 points to the PACA.
249 .globl kvm_start_guest
252 /* Set runlatch bit the minute you wake up from nap */
259 li r0,KVM_HWTHREAD_IN_KVM
260 stb r0,HSTATE_HWTHREAD_STATE(r13)
262 /* NV GPR values from power7_idle() will no longer be valid */
264 stb r0,PACA_NAPSTATELOST(r13)
266 /* were we napping due to cede? */
267 lbz r0,HSTATE_NAPPING(r13)
268 cmpwi r0,NAPPING_CEDE
270 cmpwi r0,NAPPING_NOVCPU
271 beq kvm_novcpu_wakeup
273 ld r1,PACAEMERGSP(r13)
274 subi r1,r1,STACK_FRAME_OVERHEAD
277 * We weren't napping due to cede, so this must be a secondary
278 * thread being woken up to run a guest, or being woken up due
279 * to a stray IPI. (Or due to some machine check or hypervisor
280 * maintenance interrupt while the core is in KVM.)
283 /* Check the wake reason in SRR1 to see why we got here */
284 bl kvmppc_check_wake_reason
288 /* get vcpu pointer, NULL if we have no vcpu to run */
289 ld r4,HSTATE_KVM_VCPU(r13)
291 /* if we have no vcpu to run, go back to sleep */
294 kvm_secondary_got_guest:
296 /* Set HSTATE_DSCR(r13) to something sensible */
297 ld r6, PACA_DSCR(r13)
298 std r6, HSTATE_DSCR(r13)
302 /* Back from the guest, go back to nap */
303 /* Clear our vcpu pointer so we don't come back in early */
305 std r0, HSTATE_KVM_VCPU(r13)
307 * Make sure we clear HSTATE_KVM_VCPU(r13) before incrementing
308 * the nap_count, because once the increment to nap_count is
309 * visible we could be given another vcpu.
313 /* increment the nap count and then go to nap mode */
314 ld r4, HSTATE_KVM_VCORE(r13)
315 addi r4, r4, VCORE_NAP_COUNT
322 * At this point we have finished executing in the guest.
323 * We need to wait for hwthread_req to become zero, since
324 * we may not turn on the MMU while hwthread_req is non-zero.
325 * While waiting we also need to check if we get given a vcpu to run.
328 lbz r3, HSTATE_HWTHREAD_REQ(r13)
332 li r0, KVM_HWTHREAD_IN_KERNEL
333 stb r0, HSTATE_HWTHREAD_STATE(r13)
334 /* need to recheck hwthread_req after a barrier, to avoid race */
336 lbz r3, HSTATE_HWTHREAD_REQ(r13)
340 * We jump to power7_wakeup_loss, which will return to the caller
341 * of power7_nap in the powernv cpu offline loop. The value we
342 * put in r3 becomes the return value for power7_nap.
346 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
352 ld r4, HSTATE_KVM_VCPU(r13)
356 b kvm_secondary_got_guest
358 54: li r0, KVM_HWTHREAD_IN_KVM
359 stb r0, HSTATE_HWTHREAD_STATE(r13)
362 /******************************************************************************
366 *****************************************************************************/
368 .global kvmppc_hv_entry
373 * R4 = vcpu pointer (or NULL)
378 * all other volatile GPRS = free
381 std r0, PPC_LR_STKOFF(r1)
384 /* Save R1 in the PACA */
385 std r1, HSTATE_HOST_R1(r13)
387 li r6, KVM_GUEST_MODE_HOST_HV
388 stb r6, HSTATE_IN_GUEST(r13)
398 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
400 * POWER7 host -> guest partition switch code.
401 * We don't have to lock against concurrent tlbies,
402 * but we do have to coordinate across hardware threads.
404 /* Increment entry count iff exit count is zero. */
405 ld r5,HSTATE_KVM_VCORE(r13)
406 addi r9,r5,VCORE_ENTRY_EXIT
408 cmpwi r3,0x100 /* any threads starting to exit? */
409 bge secondary_too_late /* if so we're too late to the party */
414 /* Primary thread switches to guest partition. */
415 ld r9,VCORE_KVM(r5) /* pointer to struct kvm */
416 lbz r6,HSTATE_PTID(r13)
421 li r0,LPID_RSVD /* switch to reserved LPID */
424 mtspr SPRN_SDR1,r6 /* switch to partition page table */
428 /* See if we need to flush the TLB */
429 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
430 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
431 srdi r6,r6,6 /* doubleword number */
432 sldi r6,r6,3 /* address offset */
434 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
440 23: ldarx r7,0,r6 /* if set, clear the bit */
444 /* Flush the TLB of any entries for this LPID */
445 /* use arch 2.07S as a proxy for POWER8 */
447 li r6,512 /* POWER8 has 512 sets */
449 li r6,128 /* POWER7 has 128 sets */
450 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
452 li r7,0x800 /* IS field = 0b10 */
459 /* Add timebase offset onto timebase */
460 22: ld r8,VCORE_TB_OFFSET(r5)
463 mftb r6 /* current host timebase */
465 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
466 mftb r7 /* check if lower 24 bits overflowed */
471 addis r8,r8,0x100 /* if so, increment upper 40 bits */
474 /* Load guest PCR value to select appropriate compat mode */
475 37: ld r7, VCORE_PCR(r5)
482 /* DPDES is shared between threads */
483 ld r8, VCORE_DPDES(r5)
485 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
488 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
491 /* Secondary threads wait for primary to have done partition switch */
492 20: lbz r0,VCORE_IN_GUEST(r5)
496 /* Set LPCR and RMOR. */
497 10: ld r8,VCORE_LPCR(r5)
503 /* Check if HDEC expires soon */
505 cmpwi r3,512 /* 1 microsecond */
506 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
511 * PPC970 host -> guest partition switch code.
512 * We have to lock against concurrent tlbies,
513 * using native_tlbie_lock to lock against host tlbies
514 * and kvm->arch.tlbie_lock to lock against guest tlbies.
515 * We also have to invalidate the TLB since its
516 * entries aren't tagged with the LPID.
518 30: ld r5,HSTATE_KVM_VCORE(r13)
519 ld r9,VCORE_KVM(r5) /* pointer to struct kvm */
521 /* first take native_tlbie_lock */
524 .tc native_tlbie_lock[TC],native_tlbie_lock
526 ld r3,toc_tlbie_lock@toc(r2)
527 #ifdef __BIG_ENDIAN__
528 lwz r8,PACA_LOCK_TOKEN(r13)
530 lwz r8,PACAPACAINDEX(r13)
539 ld r5,HSTATE_KVM_VCORE(r13)
540 ld r7,VCORE_LPCR(r5) /* use vcore->lpcr to store HID4 */
542 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
546 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
549 stw r0,0(r3) /* drop native_tlbie_lock */
551 /* invalidate the whole TLB */
560 /* Take the guest's tlbie_lock */
561 addi r3,r9,KVM_TLBIE_LOCK
569 mtspr SPRN_SDR1,r6 /* switch to partition page table */
571 /* Set up HID4 with the guest's LPID etc. */
576 /* drop the guest's tlbie_lock */
580 /* Check if HDEC expires soon */
583 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
586 /* Enable HDEC interrupts */
589 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
599 /* Do we have a guest vcpu to run? */
601 beq kvmppc_primary_no_guest
604 /* Load up guest SLB entries */
605 lwz r5,VCPU_SLB_MAX(r4)
610 1: ld r8,VCPU_SLB_E(r6)
613 addi r6,r6,VCPU_SLB_SIZE
616 /* Increment yield count if they have a VPA */
620 li r6, LPPACA_YIELDCOUNT
625 stb r6, VCPU_VPA_DIRTY(r4)
629 /* Save purr/spurr */
632 std r5,HSTATE_PURR(r13)
633 std r6,HSTATE_SPURR(r13)
638 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
641 /* Set partition DABR */
642 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
643 lwz r5,VCPU_DABRX(r4)
647 BEGIN_FTR_SECTION_NESTED(89)
649 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_206, CPU_FTR_ARCH_206, 89)
650 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
652 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
655 END_FTR_SECTION_IFCLR(CPU_FTR_TM)
657 /* Turn on TM/FP/VSX/VMX so we can restore them. */
663 oris r5, r5, (MSR_VEC | MSR_VSX)@h
667 * The user may change these outside of a transaction, so they must
668 * always be context switched.
670 ld r5, VCPU_TFHAR(r4)
671 ld r6, VCPU_TFIAR(r4)
672 ld r7, VCPU_TEXASR(r4)
675 mtspr SPRN_TEXASR, r7
678 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
679 beq skip_tm /* TM not active in guest */
681 /* Make sure the failure summary is set, otherwise we'll program check
682 * when we trechkpt. It's possible that this might have been not set
683 * on a kvmppc_set_one_reg() call but we shouldn't let this crash the
686 oris r7, r7, (TEXASR_FS)@h
687 mtspr SPRN_TEXASR, r7
690 * We need to load up the checkpointed state for the guest.
691 * We need to do this early as it will blow away any GPRs, VSRs and
696 addi r3, r31, VCPU_FPRS_TM
698 addi r3, r31, VCPU_VRS_TM
701 lwz r7, VCPU_VRSAVE_TM(r4)
702 mtspr SPRN_VRSAVE, r7
704 ld r5, VCPU_LR_TM(r4)
705 lwz r6, VCPU_CR_TM(r4)
706 ld r7, VCPU_CTR_TM(r4)
707 ld r8, VCPU_AMR_TM(r4)
708 ld r9, VCPU_TAR_TM(r4)
716 * Load up PPR and DSCR values but don't put them in the actual SPRs
717 * till the last moment to avoid running with userspace PPR and DSCR for
720 ld r29, VCPU_DSCR_TM(r4)
721 ld r30, VCPU_PPR_TM(r4)
723 std r2, PACATMSCRATCH(r13) /* Save TOC */
725 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
729 /* Load GPRs r0-r28 */
732 ld reg, VCPU_GPRS_TM(reg)(r31)
739 /* Load final GPRs */
740 ld 29, VCPU_GPRS_TM(29)(r31)
741 ld 30, VCPU_GPRS_TM(30)(r31)
742 ld 31, VCPU_GPRS_TM(31)(r31)
744 /* TM checkpointed state is now setup. All GPRs are now volatile. */
747 /* Now let's get back the state we need. */
750 ld r29, HSTATE_DSCR(r13)
752 ld r4, HSTATE_KVM_VCPU(r13)
753 ld r1, HSTATE_HOST_R1(r13)
754 ld r2, PACATMSCRATCH(r13)
756 /* Set the MSR RI since we have our registers back. */
762 /* Load guest PMU registers */
763 /* R4 is live here (vcpu pointer) */
765 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
766 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
770 andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
773 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
774 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
775 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
776 lwz r6, VCPU_PMC + 8(r4)
777 lwz r7, VCPU_PMC + 12(r4)
778 lwz r8, VCPU_PMC + 16(r4)
779 lwz r9, VCPU_PMC + 20(r4)
781 lwz r10, VCPU_PMC + 24(r4)
782 lwz r11, VCPU_PMC + 28(r4)
783 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
793 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
795 ld r5, VCPU_MMCR + 8(r4)
796 ld r6, VCPU_MMCR + 16(r4)
804 ld r5, VCPU_MMCR + 24(r4)
806 lwz r7, VCPU_PMC + 24(r4)
807 lwz r8, VCPU_PMC + 28(r4)
808 ld r9, VCPU_MMCR + 32(r4)
814 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
818 /* Load up FP, VMX and VSX registers */
821 ld r14, VCPU_GPR(R14)(r4)
822 ld r15, VCPU_GPR(R15)(r4)
823 ld r16, VCPU_GPR(R16)(r4)
824 ld r17, VCPU_GPR(R17)(r4)
825 ld r18, VCPU_GPR(R18)(r4)
826 ld r19, VCPU_GPR(R19)(r4)
827 ld r20, VCPU_GPR(R20)(r4)
828 ld r21, VCPU_GPR(R21)(r4)
829 ld r22, VCPU_GPR(R22)(r4)
830 ld r23, VCPU_GPR(R23)(r4)
831 ld r24, VCPU_GPR(R24)(r4)
832 ld r25, VCPU_GPR(R25)(r4)
833 ld r26, VCPU_GPR(R26)(r4)
834 ld r27, VCPU_GPR(R27)(r4)
835 ld r28, VCPU_GPR(R28)(r4)
836 ld r29, VCPU_GPR(R29)(r4)
837 ld r30, VCPU_GPR(R30)(r4)
838 ld r31, VCPU_GPR(R31)(r4)
841 /* Switch DSCR to guest value */
844 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
847 /* Skip next section on POWER7 or PPC970 */
849 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
850 /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */
853 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
856 /* Load up POWER8-specific registers */
858 lwz r6, VCPU_PSPB(r4)
864 ld r6, VCPU_DAWRX(r4)
865 ld r7, VCPU_CIABR(r4)
875 ld r8, VCPU_EBBHR(r4)
877 ld r5, VCPU_EBBRR(r4)
878 ld r6, VCPU_BESCR(r4)
879 ld r7, VCPU_CSIGR(r4)
885 ld r5, VCPU_TCSCR(r4)
887 lwz r7, VCPU_GUEST_PID(r4)
896 * Set the decrementer to the guest decrementer.
898 ld r8,VCPU_DEC_EXPIRES(r4)
899 /* r8 is a host timebase value here, convert to guest TB */
900 ld r5,HSTATE_KVM_VCORE(r13)
901 ld r6,VCORE_TB_OFFSET(r5)
908 ld r5, VCPU_SPRG0(r4)
909 ld r6, VCPU_SPRG1(r4)
910 ld r7, VCPU_SPRG2(r4)
911 ld r8, VCPU_SPRG3(r4)
917 /* Load up DAR and DSISR */
919 lwz r6, VCPU_DSISR(r4)
924 /* Restore AMR and UAMOR, set AMOR to all 1s */
931 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
933 /* Restore state of CTRL run bit; assume 1 on entry */
947 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
955 deliver_guest_interrupt:
956 /* r11 = vcpu->arch.msr & ~MSR_HV */
957 rldicl r11, r11, 63 - MSR_HV_LG, 1
958 rotldi r11, r11, 1 + MSR_HV_LG
961 /* Check if we can deliver an external or decrementer interrupt now */
962 ld r0, VCPU_PENDING_EXC(r4)
963 rldicl r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
965 andi. r8, r11, MSR_EE
968 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
969 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
972 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
974 li r0, BOOK3S_INTERRUPT_EXTERNAL
978 li r0, BOOK3S_INTERRUPT_DECREMENTER
981 12: mtspr SPRN_SRR0, r10
985 bl kvmppc_msr_interrupt
991 * R10: value for HSRR0
992 * R11: value for HSRR1
997 stb r0,VCPU_CEDED(r4) /* cancel cede */
1001 /* Activate guest mode, so faults get handled by KVM */
1002 li r9, KVM_GUEST_MODE_GUEST_HV
1003 stb r9, HSTATE_IN_GUEST(r13)
1008 ld r5, VCPU_CFAR(r4)
1010 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1013 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1020 ld r1, VCPU_GPR(R1)(r4)
1021 ld r2, VCPU_GPR(R2)(r4)
1022 ld r3, VCPU_GPR(R3)(r4)
1023 ld r5, VCPU_GPR(R5)(r4)
1024 ld r6, VCPU_GPR(R6)(r4)
1025 ld r7, VCPU_GPR(R7)(r4)
1026 ld r8, VCPU_GPR(R8)(r4)
1027 ld r9, VCPU_GPR(R9)(r4)
1028 ld r10, VCPU_GPR(R10)(r4)
1029 ld r11, VCPU_GPR(R11)(r4)
1030 ld r12, VCPU_GPR(R12)(r4)
1031 ld r13, VCPU_GPR(R13)(r4)
1035 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1036 ld r0, VCPU_GPR(R0)(r4)
1037 ld r4, VCPU_GPR(R4)(r4)
1042 /******************************************************************************
1046 *****************************************************************************/
1049 * We come here from the first-level interrupt handlers.
1051 .globl kvmppc_interrupt_hv
1052 kvmppc_interrupt_hv:
1054 * Register contents:
1055 * R12 = interrupt vector
1057 * guest CR, R12 saved in shadow VCPU SCRATCH1/0
1058 * guest R13 saved in SPRN_SCRATCH0
1060 std r9, HSTATE_SCRATCH2(r13)
1062 lbz r9, HSTATE_IN_GUEST(r13)
1063 cmpwi r9, KVM_GUEST_MODE_HOST_HV
1064 beq kvmppc_bad_host_intr
1065 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1066 cmpwi r9, KVM_GUEST_MODE_GUEST
1067 ld r9, HSTATE_SCRATCH2(r13)
1068 beq kvmppc_interrupt_pr
1070 /* We're now back in the host but in guest MMU context */
1071 li r9, KVM_GUEST_MODE_HOST_HV
1072 stb r9, HSTATE_IN_GUEST(r13)
1074 ld r9, HSTATE_KVM_VCPU(r13)
1076 /* Save registers */
1078 std r0, VCPU_GPR(R0)(r9)
1079 std r1, VCPU_GPR(R1)(r9)
1080 std r2, VCPU_GPR(R2)(r9)
1081 std r3, VCPU_GPR(R3)(r9)
1082 std r4, VCPU_GPR(R4)(r9)
1083 std r5, VCPU_GPR(R5)(r9)
1084 std r6, VCPU_GPR(R6)(r9)
1085 std r7, VCPU_GPR(R7)(r9)
1086 std r8, VCPU_GPR(R8)(r9)
1087 ld r0, HSTATE_SCRATCH2(r13)
1088 std r0, VCPU_GPR(R9)(r9)
1089 std r10, VCPU_GPR(R10)(r9)
1090 std r11, VCPU_GPR(R11)(r9)
1091 ld r3, HSTATE_SCRATCH0(r13)
1092 lwz r4, HSTATE_SCRATCH1(r13)
1093 std r3, VCPU_GPR(R12)(r9)
1096 ld r3, HSTATE_CFAR(r13)
1097 std r3, VCPU_CFAR(r9)
1098 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1100 ld r4, HSTATE_PPR(r13)
1101 std r4, VCPU_PPR(r9)
1102 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1104 /* Restore R1/R2 so we can handle faults */
1105 ld r1, HSTATE_HOST_R1(r13)
1108 mfspr r10, SPRN_SRR0
1109 mfspr r11, SPRN_SRR1
1110 std r10, VCPU_SRR0(r9)
1111 std r11, VCPU_SRR1(r9)
1112 andi. r0, r12, 2 /* need to read HSRR0/1? */
1114 mfspr r10, SPRN_HSRR0
1115 mfspr r11, SPRN_HSRR1
1117 1: std r10, VCPU_PC(r9)
1118 std r11, VCPU_MSR(r9)
1122 std r3, VCPU_GPR(R13)(r9)
1125 stw r12,VCPU_TRAP(r9)
1127 /* Save HEIR (HV emulation assist reg) in last_inst
1128 if this is an HEI (HV emulation interrupt, e40) */
1129 li r3,KVM_INST_FETCH_FAILED
1131 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1134 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1135 11: stw r3,VCPU_LAST_INST(r9)
1137 /* these are volatile across C function calls */
1140 std r3, VCPU_CTR(r9)
1141 stw r4, VCPU_XER(r9)
1144 /* If this is a page table miss then see if it's theirs or ours */
1145 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1147 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1149 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1151 /* See if this is a leftover HDEC interrupt */
1152 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1158 /* See if this is an hcall we can handle in real mode */
1159 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1160 beq hcall_try_real_mode
1162 /* Only handle external interrupts here on arch 206 and later */
1164 b ext_interrupt_to_host
1165 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
1167 /* External interrupt ? */
1168 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1169 bne+ ext_interrupt_to_host
1171 /* External interrupt, first check for host_ipi. If this is
1172 * set, we know the host wants us out so let's do it now
1176 bgt ext_interrupt_to_host
1178 /* Check if any CPU is heading out to the host, if so head out too */
1179 ld r5, HSTATE_KVM_VCORE(r13)
1180 lwz r0, VCORE_ENTRY_EXIT(r5)
1182 bge ext_interrupt_to_host
1184 /* Return to guest after delivering any pending interrupt */
1186 b deliver_guest_interrupt
1188 ext_interrupt_to_host:
1190 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1191 /* Save more register state */
1194 std r6, VCPU_DAR(r9)
1195 stw r7, VCPU_DSISR(r9)
1197 /* don't overwrite fault_dar/fault_dsisr if HDSI */
1198 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
1200 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1201 std r6, VCPU_FAULT_DAR(r9)
1202 stw r7, VCPU_FAULT_DSISR(r9)
1204 /* See if it is a machine check */
1205 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1206 beq machine_check_realmode
1209 /* Save guest CTRL register, set runlatch to 1 */
1210 6: mfspr r6,SPRN_CTRLF
1211 stw r6,VCPU_CTRL(r9)
1217 /* Read the guest SLB and save it away */
1218 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1224 andis. r0,r8,SLB_ESID_V@h
1226 add r8,r8,r6 /* put index in */
1228 std r8,VCPU_SLB_E(r7)
1229 std r3,VCPU_SLB_V(r7)
1230 addi r7,r7,VCPU_SLB_SIZE
1234 stw r5,VCPU_SLB_MAX(r9)
1237 * Save the guest PURR/SPURR
1243 ld r8,VCPU_SPURR(r9)
1244 std r5,VCPU_PURR(r9)
1245 std r6,VCPU_SPURR(r9)
1250 * Restore host PURR/SPURR and add guest times
1251 * so that the time in the guest gets accounted.
1253 ld r3,HSTATE_PURR(r13)
1254 ld r4,HSTATE_SPURR(r13)
1259 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
1266 /* r5 is a guest timebase value here, convert to host TB */
1267 ld r3,HSTATE_KVM_VCORE(r13)
1268 ld r4,VCORE_TB_OFFSET(r3)
1270 std r5,VCPU_DEC_EXPIRES(r9)
1274 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1275 /* Save POWER8-specific registers */
1279 std r5, VCPU_IAMR(r9)
1280 stw r6, VCPU_PSPB(r9)
1281 std r7, VCPU_FSCR(r9)
1286 std r6, VCPU_VTB(r9)
1287 std r7, VCPU_TAR(r9)
1288 mfspr r8, SPRN_EBBHR
1289 std r8, VCPU_EBBHR(r9)
1290 mfspr r5, SPRN_EBBRR
1291 mfspr r6, SPRN_BESCR
1292 mfspr r7, SPRN_CSIGR
1294 std r5, VCPU_EBBRR(r9)
1295 std r6, VCPU_BESCR(r9)
1296 std r7, VCPU_CSIGR(r9)
1297 std r8, VCPU_TACR(r9)
1298 mfspr r5, SPRN_TCSCR
1302 std r5, VCPU_TCSCR(r9)
1303 std r6, VCPU_ACOP(r9)
1304 stw r7, VCPU_GUEST_PID(r9)
1305 std r8, VCPU_WORT(r9)
1308 /* Save and reset AMR and UAMOR before turning on the MMU */
1313 std r6,VCPU_UAMOR(r9)
1316 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1318 /* Switch DSCR back to host value */
1321 ld r7, HSTATE_DSCR(r13)
1322 std r8, VCPU_DSCR(r9)
1324 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1326 /* Save non-volatile GPRs */
1327 std r14, VCPU_GPR(R14)(r9)
1328 std r15, VCPU_GPR(R15)(r9)
1329 std r16, VCPU_GPR(R16)(r9)
1330 std r17, VCPU_GPR(R17)(r9)
1331 std r18, VCPU_GPR(R18)(r9)
1332 std r19, VCPU_GPR(R19)(r9)
1333 std r20, VCPU_GPR(R20)(r9)
1334 std r21, VCPU_GPR(R21)(r9)
1335 std r22, VCPU_GPR(R22)(r9)
1336 std r23, VCPU_GPR(R23)(r9)
1337 std r24, VCPU_GPR(R24)(r9)
1338 std r25, VCPU_GPR(R25)(r9)
1339 std r26, VCPU_GPR(R26)(r9)
1340 std r27, VCPU_GPR(R27)(r9)
1341 std r28, VCPU_GPR(R28)(r9)
1342 std r29, VCPU_GPR(R29)(r9)
1343 std r30, VCPU_GPR(R30)(r9)
1344 std r31, VCPU_GPR(R31)(r9)
1347 mfspr r3, SPRN_SPRG0
1348 mfspr r4, SPRN_SPRG1
1349 mfspr r5, SPRN_SPRG2
1350 mfspr r6, SPRN_SPRG3
1351 std r3, VCPU_SPRG0(r9)
1352 std r4, VCPU_SPRG1(r9)
1353 std r5, VCPU_SPRG2(r9)
1354 std r6, VCPU_SPRG3(r9)
1360 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1363 END_FTR_SECTION_IFCLR(CPU_FTR_TM)
1367 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
1371 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
1372 beq 1f /* TM not active in guest. */
1374 li r3, TM_CAUSE_KVM_RESCHED
1376 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
1380 /* All GPRs are volatile at this point. */
1383 /* Temporarily store r13 and r9 so we have some regs to play with */
1386 std r9, PACATMSCRATCH(r13)
1387 ld r9, HSTATE_KVM_VCPU(r13)
1389 /* Get a few more GPRs free. */
1390 std r29, VCPU_GPRS_TM(29)(r9)
1391 std r30, VCPU_GPRS_TM(30)(r9)
1392 std r31, VCPU_GPRS_TM(31)(r9)
1394 /* Save away PPR and DSCR soon so don't run with user values. */
1397 mfspr r30, SPRN_DSCR
1398 ld r29, HSTATE_DSCR(r13)
1399 mtspr SPRN_DSCR, r29
1401 /* Save all but r9, r13 & r29-r31 */
1404 .if (reg != 9) && (reg != 13)
1405 std reg, VCPU_GPRS_TM(reg)(r9)
1409 /* ... now save r13 */
1411 std r4, VCPU_GPRS_TM(13)(r9)
1412 /* ... and save r9 */
1413 ld r4, PACATMSCRATCH(r13)
1414 std r4, VCPU_GPRS_TM(9)(r9)
1416 /* Reload stack pointer and TOC. */
1417 ld r1, HSTATE_HOST_R1(r13)
1420 /* Set MSR RI now we have r1 and r13 back. */
1424 /* Save away checkpinted SPRs. */
1425 std r31, VCPU_PPR_TM(r9)
1426 std r30, VCPU_DSCR_TM(r9)
1432 std r5, VCPU_LR_TM(r9)
1433 stw r6, VCPU_CR_TM(r9)
1434 std r7, VCPU_CTR_TM(r9)
1435 std r8, VCPU_AMR_TM(r9)
1436 std r10, VCPU_TAR_TM(r9)
1438 /* Restore r12 as trap number. */
1439 lwz r12, VCPU_TRAP(r9)
1442 addi r3, r9, VCPU_FPRS_TM
1444 addi r3, r9, VCPU_VRS_TM
1446 mfspr r6, SPRN_VRSAVE
1447 stw r6, VCPU_VRSAVE_TM(r9)
1450 * We need to save these SPRs after the treclaim so that the software
1451 * error code is recorded correctly in the TEXASR. Also the user may
1452 * change these outside of a transaction, so they must always be
1455 mfspr r5, SPRN_TFHAR
1456 mfspr r6, SPRN_TFIAR
1457 mfspr r7, SPRN_TEXASR
1458 std r5, VCPU_TFHAR(r9)
1459 std r6, VCPU_TFIAR(r9)
1460 std r7, VCPU_TEXASR(r9)
1464 /* Increment yield count if they have a VPA */
1465 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1468 li r4, LPPACA_YIELDCOUNT
1473 stb r3, VCPU_VPA_DIRTY(r9)
1475 /* Save PMU registers if requested */
1476 /* r8 and cr0.eq are live here */
1479 * POWER8 seems to have a hardware bug where setting
1480 * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
1481 * when some counters are already negative doesn't seem
1482 * to cause a performance monitor alert (and hence interrupt).
1483 * The effect of this is that when saving the PMU state,
1484 * if there is no PMU alert pending when we read MMCR0
1485 * before freezing the counters, but one becomes pending
1486 * before we read the counters, we lose it.
1487 * To work around this, we need a way to freeze the counters
1488 * before reading MMCR0. Normally, freezing the counters
1489 * is done by writing MMCR0 (to set MMCR0[FC]) which
1490 * unavoidably writes MMCR0[PMA0] as well. On POWER8,
1491 * we can also freeze the counters using MMCR2, by writing
1492 * 1s to all the counter freeze condition bits (there are
1493 * 9 bits each for 6 counters).
1495 li r3, -1 /* set all freeze bits */
1497 mfspr r10, SPRN_MMCR2
1498 mtspr SPRN_MMCR2, r3
1500 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1502 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1503 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1504 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1505 mfspr r6, SPRN_MMCRA
1507 /* On P7, clear MMCRA in order to disable SDAR updates */
1509 mtspr SPRN_MMCRA, r7
1510 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1512 beq 21f /* if no VPA, save PMU stuff anyway */
1513 lbz r7, LPPACA_PMCINUSE(r8)
1514 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1516 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1518 21: mfspr r5, SPRN_MMCR1
1521 std r4, VCPU_MMCR(r9)
1522 std r5, VCPU_MMCR + 8(r9)
1523 std r6, VCPU_MMCR + 16(r9)
1525 std r10, VCPU_MMCR + 24(r9)
1526 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1527 std r7, VCPU_SIAR(r9)
1528 std r8, VCPU_SDAR(r9)
1536 mfspr r10, SPRN_PMC7
1537 mfspr r11, SPRN_PMC8
1538 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1539 stw r3, VCPU_PMC(r9)
1540 stw r4, VCPU_PMC + 4(r9)
1541 stw r5, VCPU_PMC + 8(r9)
1542 stw r6, VCPU_PMC + 12(r9)
1543 stw r7, VCPU_PMC + 16(r9)
1544 stw r8, VCPU_PMC + 20(r9)
1546 stw r10, VCPU_PMC + 24(r9)
1547 stw r11, VCPU_PMC + 28(r9)
1548 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1551 mfspr r6, SPRN_SPMC1
1552 mfspr r7, SPRN_SPMC2
1553 mfspr r8, SPRN_MMCRS
1554 std r5, VCPU_SIER(r9)
1555 stw r6, VCPU_PMC + 24(r9)
1556 stw r7, VCPU_PMC + 28(r9)
1557 std r8, VCPU_MMCR + 32(r9)
1559 mtspr SPRN_MMCRS, r4
1560 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1568 hdec_soon: /* r12 = trap, r13 = paca */
1571 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1573 * POWER7 guest -> host partition switch code.
1574 * We don't have to lock against tlbies but we do
1575 * have to coordinate the hardware threads.
1577 /* Increment the threads-exiting-guest count in the 0xff00
1578 bits of vcore->entry_exit_count */
1579 ld r5,HSTATE_KVM_VCORE(r13)
1580 addi r6,r5,VCORE_ENTRY_EXIT
1585 isync /* order stwcx. vs. reading napping_threads */
1588 * At this point we have an interrupt that we have to pass
1589 * up to the kernel or qemu; we can't handle it in real mode.
1590 * Thus we have to do a partition switch, so we have to
1591 * collect the other threads, if we are the first thread
1592 * to take an interrupt. To do this, we set the HDEC to 0,
1593 * which causes an HDEC interrupt in all threads within 2ns
1594 * because the HDEC register is shared between all 4 threads.
1595 * However, we don't need to bother if this is an HDEC
1596 * interrupt, since the other threads will already be on their
1597 * way here in that case.
1599 cmpwi r3,0x100 /* Are we the first here? */
1601 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1607 * Send an IPI to any napping threads, since an HDEC interrupt
1608 * doesn't wake CPUs up from nap.
1610 lwz r3,VCORE_NAPPING_THREADS(r5)
1611 lbz r4,HSTATE_PTID(r13)
1614 andc. r3,r3,r0 /* no sense IPI'ing ourselves */
1616 /* Order entry/exit update vs. IPIs */
1618 mulli r4,r4,PACA_SIZE /* get paca for thread 0 */
1622 ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */
1625 stbcix r0,r7,r8 /* trigger the IPI */
1627 addi r6,r6,PACA_SIZE
1631 /* Secondary threads wait for primary to do partition switch */
1632 43: ld r5,HSTATE_KVM_VCORE(r13)
1633 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1634 lbz r3,HSTATE_PTID(r13)
1638 13: lbz r3,VCORE_IN_GUEST(r5)
1644 /* Primary thread waits for all the secondaries to exit guest */
1645 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1652 /* Primary thread switches back to host partition */
1653 ld r6,KVM_HOST_SDR1(r4)
1654 lwz r7,KVM_HOST_LPID(r4)
1655 li r8,LPID_RSVD /* switch to reserved LPID */
1658 mtspr SPRN_SDR1,r6 /* switch to partition page table */
1663 /* DPDES is shared between threads */
1664 mfspr r7, SPRN_DPDES
1665 std r7, VCORE_DPDES(r5)
1666 /* clear DPDES so we don't get guest doorbells in the host */
1668 mtspr SPRN_DPDES, r8
1669 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1671 /* Subtract timebase offset from timebase */
1672 ld r8,VCORE_TB_OFFSET(r5)
1675 mftb r6 /* current guest timebase */
1677 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1678 mftb r7 /* check if lower 24 bits overflowed */
1683 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1687 17: ld r0, VCORE_PCR(r5)
1693 /* Signal secondary CPUs to continue */
1694 stb r0,VCORE_IN_GUEST(r5)
1695 lis r8,0x7fff /* MAX_INT@h */
1698 16: ld r8,KVM_HOST_LPCR(r4)
1704 * PPC970 guest -> host partition switch code.
1705 * We have to lock against concurrent tlbies, and
1706 * we have to flush the whole TLB.
1708 32: ld r5,HSTATE_KVM_VCORE(r13)
1709 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1711 /* Take the guest's tlbie_lock */
1712 #ifdef __BIG_ENDIAN__
1713 lwz r8,PACA_LOCK_TOKEN(r13)
1715 lwz r8,PACAPACAINDEX(r13)
1717 addi r3,r4,KVM_TLBIE_LOCK
1725 ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */
1727 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
1731 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
1734 stw r0,0(r3) /* drop guest tlbie_lock */
1736 /* invalidate the whole TLB */
1745 /* take native_tlbie_lock */
1746 ld r3,toc_tlbie_lock@toc(2)
1754 ld r6,KVM_HOST_SDR1(r4)
1755 mtspr SPRN_SDR1,r6 /* switch to host page table */
1757 /* Set up host HID4 value */
1762 stw r0,0(r3) /* drop native_tlbie_lock */
1764 lis r8,0x7fff /* MAX_INT@h */
1767 /* Disable HDEC interrupts */
1770 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
1780 /* load host SLB entries */
1781 33: ld r8,PACA_SLBSHADOWPTR(r13)
1783 .rept SLB_NUM_BOLTED
1784 li r3, SLBSHADOW_SAVEAREA
1788 andis. r7,r5,SLB_ESID_V@h
1794 /* Unset guest mode */
1795 li r0, KVM_GUEST_MODE_NONE
1796 stb r0, HSTATE_IN_GUEST(r13)
1798 ld r0, 112+PPC_LR_STKOFF(r1)
1804 * Check whether an HDSI is an HPTE not found fault or something else.
1805 * If it is an HPTE not found fault that is due to the guest accessing
1806 * a page that they have mapped but which we have paged out, then
1807 * we continue on with the guest exit path. In all other cases,
1808 * reflect the HDSI to the guest as a DSI.
1812 mfspr r6, SPRN_HDSISR
1813 /* HPTE not found fault or protection fault? */
1814 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1815 beq 1f /* if not, send it to the guest */
1816 andi. r0, r11, MSR_DR /* data relocation enabled? */
1819 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1820 bne 1f /* if no SLB entry found */
1821 4: std r4, VCPU_FAULT_DAR(r9)
1822 stw r6, VCPU_FAULT_DSISR(r9)
1824 /* Search the hash table. */
1825 mr r3, r9 /* vcpu pointer */
1826 li r7, 1 /* data fault */
1827 bl kvmppc_hpte_hv_fault
1828 ld r9, HSTATE_KVM_VCPU(r13)
1830 ld r11, VCPU_MSR(r9)
1831 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1832 cmpdi r3, 0 /* retry the instruction */
1834 cmpdi r3, -1 /* handle in kernel mode */
1836 cmpdi r3, -2 /* MMIO emulation; need instr word */
1839 /* Synthesize a DSI for the guest */
1840 ld r4, VCPU_FAULT_DAR(r9)
1842 1: mtspr SPRN_DAR, r4
1843 mtspr SPRN_DSISR, r6
1844 mtspr SPRN_SRR0, r10
1845 mtspr SPRN_SRR1, r11
1846 li r10, BOOK3S_INTERRUPT_DATA_STORAGE
1847 bl kvmppc_msr_interrupt
1848 fast_interrupt_c_return:
1849 6: ld r7, VCPU_CTR(r9)
1850 lwz r8, VCPU_XER(r9)
1856 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1857 ld r5, KVM_VRMA_SLB_V(r5)
1860 /* If this is for emulated MMIO, load the instruction word */
1861 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1863 /* Set guest mode to 'jump over instruction' so if lwz faults
1864 * we'll just continue at the next IP. */
1865 li r0, KVM_GUEST_MODE_SKIP
1866 stb r0, HSTATE_IN_GUEST(r13)
1868 /* Do the access with MSR:DR enabled */
1870 ori r4, r3, MSR_DR /* Enable paging for data */
1875 /* Store the result */
1876 stw r8, VCPU_LAST_INST(r9)
1878 /* Unset guest mode. */
1879 li r0, KVM_GUEST_MODE_HOST_HV
1880 stb r0, HSTATE_IN_GUEST(r13)
1884 * Similarly for an HISI, reflect it to the guest as an ISI unless
1885 * it is an HPTE not found fault for a page that we have paged out.
1888 andis. r0, r11, SRR1_ISI_NOPT@h
1890 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1893 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1894 bne 1f /* if no SLB entry found */
1896 /* Search the hash table. */
1897 mr r3, r9 /* vcpu pointer */
1900 li r7, 0 /* instruction fault */
1901 bl kvmppc_hpte_hv_fault
1902 ld r9, HSTATE_KVM_VCPU(r13)
1904 ld r11, VCPU_MSR(r9)
1905 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1906 cmpdi r3, 0 /* retry the instruction */
1907 beq fast_interrupt_c_return
1908 cmpdi r3, -1 /* handle in kernel mode */
1911 /* Synthesize an ISI for the guest */
1913 1: mtspr SPRN_SRR0, r10
1914 mtspr SPRN_SRR1, r11
1915 li r10, BOOK3S_INTERRUPT_INST_STORAGE
1916 bl kvmppc_msr_interrupt
1917 b fast_interrupt_c_return
1919 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1920 ld r5, KVM_VRMA_SLB_V(r6)
1924 * Try to handle an hcall in real mode.
1925 * Returns to the guest if we handle it, or continues on up to
1926 * the kernel if we can't (i.e. if we don't have a handler for
1927 * it, or if the handler returns H_TOO_HARD).
1929 .globl hcall_try_real_mode
1930 hcall_try_real_mode:
1931 ld r3,VCPU_GPR(R3)(r9)
1933 /* sc 1 from userspace - reflect to guest syscall */
1934 bne sc_1_fast_return
1936 cmpldi r3,hcall_real_table_end - hcall_real_table
1938 /* See if this hcall is enabled for in-kernel handling */
1940 srdi r0, r3, 8 /* r0 = (r3 / 4) >> 6 */
1941 sldi r0, r0, 3 /* index into kvm->arch.enabled_hcalls[] */
1943 ld r0, KVM_ENABLED_HCALLS(r4)
1944 rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */
1948 /* Get pointer to handler, if any, and call it */
1949 LOAD_REG_ADDR(r4, hcall_real_table)
1955 mr r3,r9 /* get vcpu pointer */
1956 ld r4,VCPU_GPR(R4)(r9)
1959 beq hcall_real_fallback
1960 ld r4,HSTATE_KVM_VCPU(r13)
1961 std r3,VCPU_GPR(R3)(r4)
1969 li r10, BOOK3S_INTERRUPT_SYSCALL
1970 bl kvmppc_msr_interrupt
1974 /* We've attempted a real mode hcall, but it's punted it back
1975 * to userspace. We need to restore some clobbered volatiles
1976 * before resuming the pass-it-to-qemu path */
1977 hcall_real_fallback:
1978 li r12,BOOK3S_INTERRUPT_SYSCALL
1979 ld r9, HSTATE_KVM_VCPU(r13)
1983 .globl hcall_real_table
1985 .long 0 /* 0 - unused */
1986 .long DOTSYM(kvmppc_h_remove) - hcall_real_table
1987 .long DOTSYM(kvmppc_h_enter) - hcall_real_table
1988 .long DOTSYM(kvmppc_h_read) - hcall_real_table
1989 .long 0 /* 0x10 - H_CLEAR_MOD */
1990 .long 0 /* 0x14 - H_CLEAR_REF */
1991 .long DOTSYM(kvmppc_h_protect) - hcall_real_table
1992 .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table
1993 .long DOTSYM(kvmppc_h_put_tce) - hcall_real_table
1994 .long 0 /* 0x24 - H_SET_SPRG0 */
1995 .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
2010 #ifdef CONFIG_KVM_XICS
2011 .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table
2012 .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table
2013 .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table
2014 .long 0 /* 0x70 - H_IPOLL */
2015 .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table
2017 .long 0 /* 0x64 - H_EOI */
2018 .long 0 /* 0x68 - H_CPPR */
2019 .long 0 /* 0x6c - H_IPI */
2020 .long 0 /* 0x70 - H_IPOLL */
2021 .long 0 /* 0x74 - H_XIRR */
2049 .long DOTSYM(kvmppc_h_cede) - hcall_real_table
2066 .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table
2070 .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
2071 .globl hcall_real_table_end
2072 hcall_real_table_end:
2078 _GLOBAL(kvmppc_h_set_xdabr)
2079 andi. r0, r5, DABRX_USER | DABRX_KERNEL
2081 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
2084 6: li r3, H_PARAMETER
2087 _GLOBAL(kvmppc_h_set_dabr)
2088 li r5, DABRX_USER | DABRX_KERNEL
2092 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2093 std r4,VCPU_DABR(r3)
2094 stw r5, VCPU_DABRX(r3)
2095 mtspr SPRN_DABRX, r5
2096 /* Work around P7 bug where DABR can get corrupted on mtspr */
2097 1: mtspr SPRN_DABR,r4
2105 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
2106 2: rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
2107 rlwimi r5, r4, 1, DAWRX_WT
2109 std r4, VCPU_DAWR(r3)
2110 std r5, VCPU_DAWRX(r3)
2112 mtspr SPRN_DAWRX, r5
2116 _GLOBAL(kvmppc_h_cede)
2118 std r11,VCPU_MSR(r3)
2120 stb r0,VCPU_CEDED(r3)
2121 sync /* order setting ceded vs. testing prodded */
2122 lbz r5,VCPU_PRODDED(r3)
2124 bne kvm_cede_prodded
2125 li r0,0 /* set trap to 0 to say hcall is handled */
2126 stw r0,VCPU_TRAP(r3)
2128 std r0,VCPU_GPR(R3)(r3)
2130 b kvm_cede_exit /* just send it up to host on 970 */
2131 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
2134 * Set our bit in the bitmask of napping threads unless all the
2135 * other threads are already napping, in which case we send this
2138 ld r5,HSTATE_KVM_VCORE(r13)
2139 lbz r6,HSTATE_PTID(r13)
2140 lwz r8,VCORE_ENTRY_EXIT(r5)
2144 addi r6,r5,VCORE_NAPPING_THREADS
2152 /* order napping_threads update vs testing entry_exit_count */
2155 stb r0,HSTATE_NAPPING(r13)
2156 lwz r7,VCORE_ENTRY_EXIT(r5)
2158 bge 33f /* another thread already exiting */
2161 * Although not specifically required by the architecture, POWER7
2162 * preserves the following registers in nap mode, even if an SMT mode
2163 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2164 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2166 /* Save non-volatile GPRs */
2167 std r14, VCPU_GPR(R14)(r3)
2168 std r15, VCPU_GPR(R15)(r3)
2169 std r16, VCPU_GPR(R16)(r3)
2170 std r17, VCPU_GPR(R17)(r3)
2171 std r18, VCPU_GPR(R18)(r3)
2172 std r19, VCPU_GPR(R19)(r3)
2173 std r20, VCPU_GPR(R20)(r3)
2174 std r21, VCPU_GPR(R21)(r3)
2175 std r22, VCPU_GPR(R22)(r3)
2176 std r23, VCPU_GPR(R23)(r3)
2177 std r24, VCPU_GPR(R24)(r3)
2178 std r25, VCPU_GPR(R25)(r3)
2179 std r26, VCPU_GPR(R26)(r3)
2180 std r27, VCPU_GPR(R27)(r3)
2181 std r28, VCPU_GPR(R28)(r3)
2182 std r29, VCPU_GPR(R29)(r3)
2183 std r30, VCPU_GPR(R30)(r3)
2184 std r31, VCPU_GPR(R31)(r3)
2190 * Take a nap until a decrementer or external or doobell interrupt
2191 * occurs, with PECE1, PECE0 and PECEDP set in LPCR. Also clear the
2192 * runlatch bit before napping.
2195 mfspr r2, SPRN_CTRLF
2197 mtspr SPRN_CTRLT, r2
2200 stb r0,HSTATE_HWTHREAD_REQ(r13)
2202 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2204 oris r5,r5,LPCR_PECEDP@h
2205 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2209 std r0, HSTATE_SCRATCH0(r13)
2211 ld r0, HSTATE_SCRATCH0(r13)
2223 /* get vcpu pointer */
2224 ld r4, HSTATE_KVM_VCPU(r13)
2226 /* Woken by external or decrementer interrupt */
2227 ld r1, HSTATE_HOST_R1(r13)
2229 /* load up FP state */
2233 ld r14, VCPU_GPR(R14)(r4)
2234 ld r15, VCPU_GPR(R15)(r4)
2235 ld r16, VCPU_GPR(R16)(r4)
2236 ld r17, VCPU_GPR(R17)(r4)
2237 ld r18, VCPU_GPR(R18)(r4)
2238 ld r19, VCPU_GPR(R19)(r4)
2239 ld r20, VCPU_GPR(R20)(r4)
2240 ld r21, VCPU_GPR(R21)(r4)
2241 ld r22, VCPU_GPR(R22)(r4)
2242 ld r23, VCPU_GPR(R23)(r4)
2243 ld r24, VCPU_GPR(R24)(r4)
2244 ld r25, VCPU_GPR(R25)(r4)
2245 ld r26, VCPU_GPR(R26)(r4)
2246 ld r27, VCPU_GPR(R27)(r4)
2247 ld r28, VCPU_GPR(R28)(r4)
2248 ld r29, VCPU_GPR(R29)(r4)
2249 ld r30, VCPU_GPR(R30)(r4)
2250 ld r31, VCPU_GPR(R31)(r4)
2252 /* Check the wake reason in SRR1 to see why we got here */
2253 bl kvmppc_check_wake_reason
2255 /* clear our bit in vcore->napping_threads */
2256 34: ld r5,HSTATE_KVM_VCORE(r13)
2257 lbz r7,HSTATE_PTID(r13)
2260 addi r6,r5,VCORE_NAPPING_THREADS
2266 stb r0,HSTATE_NAPPING(r13)
2268 /* See if the wake reason means we need to exit */
2269 stw r12, VCPU_TRAP(r4)
2274 /* see if any other thread is already exiting */
2275 lwz r0,VCORE_ENTRY_EXIT(r5)
2279 b kvmppc_cede_reentry /* if not go back to guest */
2281 /* cede when already previously prodded case */
2284 stb r0,VCPU_PRODDED(r3)
2285 sync /* order testing prodded vs. clearing ceded */
2286 stb r0,VCPU_CEDED(r3)
2290 /* we've ceded but we want to give control to the host */
2292 b hcall_real_fallback
2294 /* Try to handle a machine check in real mode */
2295 machine_check_realmode:
2296 mr r3, r9 /* get vcpu pointer */
2297 bl kvmppc_realmode_machine_check
2299 cmpdi r3, 0 /* Did we handle MCE ? */
2300 ld r9, HSTATE_KVM_VCPU(r13)
2301 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2303 * Deliver unhandled/fatal (e.g. UE) MCE errors to guest through
2304 * machine check interrupt (set HSRR0 to 0x200). And for handled
2305 * errors (no-fatal), just go back to guest execution with current
2306 * HSRR0 instead of exiting guest. This new approach will inject
2307 * machine check to guest for fatal error causing guest to crash.
2309 * The old code used to return to host for unhandled errors which
2310 * was causing guest to hang with soft lockups inside guest and
2311 * makes it difficult to recover guest instance.
2314 ld r11, VCPU_MSR(r9)
2315 bne 2f /* Continue guest execution. */
2316 /* If not, deliver a machine check. SRR0/1 are already set */
2317 li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
2318 ld r11, VCPU_MSR(r9)
2319 bl kvmppc_msr_interrupt
2320 2: b fast_interrupt_c_return
2323 * Check the reason we woke from nap, and take appropriate action.
2325 * 0 if nothing needs to be done
2326 * 1 if something happened that needs to be handled by the host
2327 * -1 if there was a guest wakeup (IPI)
2329 * Also sets r12 to the interrupt vector for any interrupt that needs
2330 * to be handled now by the host (0x500 for external interrupt), or zero.
2332 kvmppc_check_wake_reason:
2335 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2337 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2338 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2339 cmpwi r6, 8 /* was it an external interrupt? */
2340 li r12, BOOK3S_INTERRUPT_EXTERNAL
2341 beq kvmppc_read_intr /* if so, see what it was */
2344 cmpwi r6, 6 /* was it the decrementer? */
2347 cmpwi r6, 5 /* privileged doorbell? */
2349 cmpwi r6, 3 /* hypervisor doorbell? */
2351 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2352 li r3, 1 /* anything else, return 1 */
2355 /* hypervisor doorbell */
2356 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
2361 * Determine what sort of external interrupt is pending (if any).
2363 * 0 if no interrupt is pending
2364 * 1 if an interrupt is pending that needs to be handled by the host
2365 * -1 if there was a guest wakeup IPI (which has now been cleared)
2368 /* see if a host IPI is pending */
2370 lbz r0, HSTATE_HOST_IPI(r13)
2374 /* Now read the interrupt from the ICP */
2375 ld r6, HSTATE_XICS_PHYS(r13)
2381 * Save XIRR for later. Since we get in in reverse endian on LE
2382 * systems, save it byte reversed and fetch it back in host endian.
2384 li r3, HSTATE_SAVED_XIRR
2386 #ifdef __LITTLE_ENDIAN__
2387 lwz r3, HSTATE_SAVED_XIRR(r13)
2391 rlwinm. r3, r3, 0, 0xffffff
2393 beq 1f /* if nothing pending in the ICP */
2395 /* We found something in the ICP...
2397 * If it's not an IPI, stash it in the PACA and return to
2398 * the host, we don't (yet) handle directing real external
2399 * interrupts directly to the guest
2401 cmpwi r3, XICS_IPI /* if there is, is it an IPI? */
2404 /* It's an IPI, clear the MFRR and EOI it */
2407 stbcix r3, r6, r8 /* clear the IPI */
2408 stwcix r0, r6, r7 /* EOI it */
2411 /* We need to re-check host IPI now in case it got set in the
2412 * meantime. If it's clear, we bounce the interrupt to the
2415 lbz r0, HSTATE_HOST_IPI(r13)
2419 /* OK, it's an IPI for us */
2423 42: /* It's not an IPI and it's for the host. We saved a copy of XIRR in
2424 * the PACA earlier, it will be picked up by the host ICP driver
2429 43: /* We raced with the host, we need to resend that IPI, bummer */
2431 stbcix r0, r6, r8 /* set the IPI */
2437 * Save away FP, VMX and VSX registers.
2439 * N.B. r30 and r31 are volatile across this function,
2440 * thus it is not callable from C.
2447 #ifdef CONFIG_ALTIVEC
2449 oris r8,r8,MSR_VEC@h
2450 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2454 oris r8,r8,MSR_VSX@h
2455 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2459 addi r3,r3,VCPU_FPRS
2461 #ifdef CONFIG_ALTIVEC
2463 addi r3,r31,VCPU_VRS
2465 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2467 mfspr r6,SPRN_VRSAVE
2468 stw r6,VCPU_VRSAVE(r31)
2473 * Load up FP, VMX and VSX registers
2475 * N.B. r30 and r31 are volatile across this function,
2476 * thus it is not callable from C.
2483 #ifdef CONFIG_ALTIVEC
2485 oris r8,r8,MSR_VEC@h
2486 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2490 oris r8,r8,MSR_VSX@h
2491 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2495 addi r3,r4,VCPU_FPRS
2497 #ifdef CONFIG_ALTIVEC
2499 addi r3,r31,VCPU_VRS
2501 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2503 lwz r7,VCPU_VRSAVE(r31)
2504 mtspr SPRN_VRSAVE,r7
2510 * We come here if we get any exception or interrupt while we are
2511 * executing host real mode code while in guest MMU context.
2512 * For now just spin, but we should do something better.
2514 kvmppc_bad_host_intr:
2518 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
2519 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
2520 * r11 has the guest MSR value (in/out)
2521 * r9 has a vcpu pointer (in)
2522 * r0 is used as a scratch register
2524 kvmppc_msr_interrupt:
2525 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
2526 cmpwi r0, 2 /* Check if we are in transactional state.. */
2527 ld r11, VCPU_INTR_MSR(r9)
2529 /* ... if transactional, change to suspended */
2531 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
2535 * This works around a hardware bug on POWER8E processors, where
2536 * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
2537 * performance monitor interrupt. Instead, when we need to have
2538 * an interrupt pending, we have to arrange for a counter to overflow.
2542 mtspr SPRN_MMCR2, r3
2543 lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
2544 ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
2545 mtspr SPRN_MMCR0, r3