2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
30 /*****************************************************************************
32 * Real Mode handlers that need to be in the linear mapping *
34 ****************************************************************************/
36 .globl kvmppc_skip_interrupt
37 kvmppc_skip_interrupt:
45 .globl kvmppc_skip_Hinterrupt
46 kvmppc_skip_Hinterrupt:
55 * Call kvmppc_hv_entry in real mode.
56 * Must be called with interrupts hard-disabled.
60 * LR = return address to continue at after eventually re-enabling MMU
62 _GLOBAL(kvmppc_hv_entry_trampoline)
64 LOAD_REG_ADDR(r5, kvmppc_hv_entry)
69 mtmsrd r0,1 /* clear RI in MSR */
75 #define VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE))
77 /******************************************************************************
81 *****************************************************************************/
87 * We come in here when wakened from nap mode on a secondary hw thread.
88 * Relocation is off and most register values are lost.
89 * r13 points to the PACA.
91 .globl kvm_start_guest
93 ld r1,PACAEMERGSP(r13)
94 subi r1,r1,STACK_FRAME_OVERHEAD
97 /* were we napping due to cede? */
98 lbz r0,HSTATE_NAPPING(r13)
102 /* get vcpu pointer */
103 ld r4, HSTATE_KVM_VCPU(r13)
105 /* We got here with an IPI; clear it */
106 ld r5, HSTATE_XICS_PHYS(r13)
110 lwzcix r8, r5, r7 /* ack the interrupt */
112 stbcix r0, r5, r6 /* clear it */
113 stwcix r8, r5, r7 /* EOI it */
115 /* NV GPR values from power7_idle() will no longer be valid */
116 stb r0, PACA_NAPSTATELOST(r13)
118 .global kvmppc_hv_entry
127 * all other volatile GPRS = free
130 std r0, HSTATE_VMHANDLER(r13)
132 ld r14, VCPU_GPR(r14)(r4)
133 ld r15, VCPU_GPR(r15)(r4)
134 ld r16, VCPU_GPR(r16)(r4)
135 ld r17, VCPU_GPR(r17)(r4)
136 ld r18, VCPU_GPR(r18)(r4)
137 ld r19, VCPU_GPR(r19)(r4)
138 ld r20, VCPU_GPR(r20)(r4)
139 ld r21, VCPU_GPR(r21)(r4)
140 ld r22, VCPU_GPR(r22)(r4)
141 ld r23, VCPU_GPR(r23)(r4)
142 ld r24, VCPU_GPR(r24)(r4)
143 ld r25, VCPU_GPR(r25)(r4)
144 ld r26, VCPU_GPR(r26)(r4)
145 ld r27, VCPU_GPR(r27)(r4)
146 ld r28, VCPU_GPR(r28)(r4)
147 ld r29, VCPU_GPR(r29)(r4)
148 ld r30, VCPU_GPR(r30)(r4)
149 ld r31, VCPU_GPR(r31)(r4)
151 /* Load guest PMU registers */
152 /* R4 is live here (vcpu pointer) */
154 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
155 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
157 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
158 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
159 lwz r6, VCPU_PMC + 8(r4)
160 lwz r7, VCPU_PMC + 12(r4)
161 lwz r8, VCPU_PMC + 16(r4)
162 lwz r9, VCPU_PMC + 20(r4)
164 lwz r10, VCPU_PMC + 24(r4)
165 lwz r11, VCPU_PMC + 28(r4)
166 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
176 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
178 ld r5, VCPU_MMCR + 8(r4)
179 ld r6, VCPU_MMCR + 16(r4)
185 /* Load up FP, VMX and VSX registers */
189 /* Switch DSCR to guest value */
192 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
195 * Set the decrementer to the guest decrementer.
197 ld r8,VCPU_DEC_EXPIRES(r4)
203 ld r5, VCPU_SPRG0(r4)
204 ld r6, VCPU_SPRG1(r4)
205 ld r7, VCPU_SPRG2(r4)
206 ld r8, VCPU_SPRG3(r4)
212 /* Save R1 in the PACA */
213 std r1, HSTATE_HOST_R1(r13)
215 /* Increment yield count if they have a VPA */
219 lwz r5, LPPACA_YIELDCOUNT(r3)
221 stw r5, LPPACA_YIELDCOUNT(r3)
223 /* Load up DAR and DSISR */
225 lwz r6, VCPU_DSISR(r4)
229 /* Set partition DABR */
236 /* Restore AMR and UAMOR, set AMOR to all 1s */
243 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
253 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
255 * POWER7 host -> guest partition switch code.
256 * We don't have to lock against concurrent tlbies,
257 * but we do have to coordinate across hardware threads.
259 /* Increment entry count iff exit count is zero. */
260 ld r5,HSTATE_KVM_VCORE(r13)
261 addi r9,r5,VCORE_ENTRY_EXIT
263 cmpwi r3,0x100 /* any threads starting to exit? */
264 bge secondary_too_late /* if so we're too late to the party */
269 /* Primary thread switches to guest partition. */
270 ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
276 li r0,LPID_RSVD /* switch to reserved LPID */
279 mtspr SPRN_SDR1,r6 /* switch to partition page table */
283 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
286 /* Secondary threads wait for primary to have done partition switch */
287 20: lbz r0,VCORE_IN_GUEST(r5)
291 /* Set LPCR and RMOR. */
292 10: ld r8,KVM_LPCR(r9)
298 /* Check if HDEC expires soon */
301 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
306 * Invalidate the TLB if we could possibly have stale TLB
307 * entries for this partition on this core due to the use
309 * XXX maybe only need this on primary thread?
311 ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
312 lwz r5,VCPU_VCPUID(r4)
313 lhz r6,PACAPACAINDEX(r13)
314 rldimi r6,r5,0,62 /* XXX map as if threads 1:1 p:v */
315 lhz r8,VCPU_LAST_CPU(r4)
316 sldi r7,r6,1 /* see if this is the same vcpu */
317 add r7,r7,r9 /* as last ran on this pcpu */
318 lhz r0,KVM_LAST_VCPU(r7)
319 cmpw r6,r8 /* on the same cpu core as last time? */
321 cmpw r0,r5 /* same vcpu as this core last ran? */
323 3: sth r6,VCPU_LAST_CPU(r4) /* if not, invalidate partition TLB */
324 sth r5,KVM_LAST_VCPU(r7)
327 li r7,0x800 /* IS field = 0b10 */
335 /* Save purr/spurr */
338 std r5,HSTATE_PURR(r13)
339 std r6,HSTATE_SPURR(r13)
347 * PPC970 host -> guest partition switch code.
348 * We have to lock against concurrent tlbies,
349 * using native_tlbie_lock to lock against host tlbies
350 * and kvm->arch.tlbie_lock to lock against guest tlbies.
351 * We also have to invalidate the TLB since its
352 * entries aren't tagged with the LPID.
354 30: ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
356 /* first take native_tlbie_lock */
359 .tc native_tlbie_lock[TC],native_tlbie_lock
361 ld r3,toc_tlbie_lock@toc(2)
362 lwz r8,PACA_LOCK_TOKEN(r13)
370 ld r7,KVM_LPCR(r9) /* use kvm->arch.lpcr to store HID4 */
372 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
376 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
379 stw r0,0(r3) /* drop native_tlbie_lock */
381 /* invalidate the whole TLB */
390 /* Take the guest's tlbie_lock */
391 addi r3,r9,KVM_TLBIE_LOCK
399 mtspr SPRN_SDR1,r6 /* switch to partition page table */
401 /* Set up HID4 with the guest's LPID etc. */
406 /* drop the guest's tlbie_lock */
410 /* Check if HDEC expires soon */
413 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
417 /* Enable HDEC interrupts */
420 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
430 /* Load up guest SLB entries */
431 31: lwz r5,VCPU_SLB_MAX(r4)
436 1: ld r8,VCPU_SLB_E(r6)
439 addi r6,r6,VCPU_SLB_SIZE
443 /* Restore state of CTRL run bit; assume 1 on entry */
457 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
461 ld r11, VCPU_MSR(r4) /* r11 = vcpu->arch.msr & ~MSR_HV */
463 rldicl r11, r11, 63 - MSR_HV_LG, 1
464 rotldi r11, r11, 1 + MSR_HV_LG
467 /* Check if we can deliver an external or decrementer interrupt now */
468 ld r0,VCPU_PENDING_EXC(r4)
469 li r8,(1 << BOOK3S_IRQPRIO_EXTERNAL)
470 oris r8,r8,(1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h
480 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
482 li r0,BOOK3S_INTERRUPT_EXTERNAL
486 li r11,(MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
492 li r0,BOOK3S_INTERRUPT_DECREMENTER
495 /* Move SRR0 and SRR1 into the respective regs */
496 5: mtspr SPRN_SRR0, r6
499 stb r0,VCPU_CEDED(r4) /* cancel cede */
505 /* Activate guest mode, so faults get handled by KVM */
506 li r9, KVM_GUEST_MODE_GUEST
507 stb r9, HSTATE_IN_GUEST(r13)
516 ld r0, VCPU_GPR(r0)(r4)
517 ld r1, VCPU_GPR(r1)(r4)
518 ld r2, VCPU_GPR(r2)(r4)
519 ld r3, VCPU_GPR(r3)(r4)
520 ld r5, VCPU_GPR(r5)(r4)
521 ld r6, VCPU_GPR(r6)(r4)
522 ld r7, VCPU_GPR(r7)(r4)
523 ld r8, VCPU_GPR(r8)(r4)
524 ld r9, VCPU_GPR(r9)(r4)
525 ld r10, VCPU_GPR(r10)(r4)
526 ld r11, VCPU_GPR(r11)(r4)
527 ld r12, VCPU_GPR(r12)(r4)
528 ld r13, VCPU_GPR(r13)(r4)
530 ld r4, VCPU_GPR(r4)(r4)
535 /******************************************************************************
539 *****************************************************************************/
542 * We come here from the first-level interrupt handlers.
544 .globl kvmppc_interrupt
548 * R12 = interrupt vector
550 * guest CR, R12 saved in shadow VCPU SCRATCH1/0
551 * guest R13 saved in SPRN_SCRATCH0
553 /* abuse host_r2 as third scratch area; we get r2 from PACATOC(r13) */
554 std r9, HSTATE_HOST_R2(r13)
555 ld r9, HSTATE_KVM_VCPU(r13)
559 std r0, VCPU_GPR(r0)(r9)
560 std r1, VCPU_GPR(r1)(r9)
561 std r2, VCPU_GPR(r2)(r9)
562 std r3, VCPU_GPR(r3)(r9)
563 std r4, VCPU_GPR(r4)(r9)
564 std r5, VCPU_GPR(r5)(r9)
565 std r6, VCPU_GPR(r6)(r9)
566 std r7, VCPU_GPR(r7)(r9)
567 std r8, VCPU_GPR(r8)(r9)
568 ld r0, HSTATE_HOST_R2(r13)
569 std r0, VCPU_GPR(r9)(r9)
570 std r10, VCPU_GPR(r10)(r9)
571 std r11, VCPU_GPR(r11)(r9)
572 ld r3, HSTATE_SCRATCH0(r13)
573 lwz r4, HSTATE_SCRATCH1(r13)
574 std r3, VCPU_GPR(r12)(r9)
577 /* Restore R1/R2 so we can handle faults */
578 ld r1, HSTATE_HOST_R1(r13)
583 std r10, VCPU_SRR0(r9)
584 std r11, VCPU_SRR1(r9)
585 andi. r0, r12, 2 /* need to read HSRR0/1? */
587 mfspr r10, SPRN_HSRR0
588 mfspr r11, SPRN_HSRR1
590 1: std r10, VCPU_PC(r9)
591 std r11, VCPU_MSR(r9)
595 std r3, VCPU_GPR(r13)(r9)
598 /* Unset guest mode */
599 li r0, KVM_GUEST_MODE_NONE
600 stb r0, HSTATE_IN_GUEST(r13)
602 stw r12,VCPU_TRAP(r9)
604 /* Save HEIR (HV emulation assist reg) in last_inst
605 if this is an HEI (HV emulation interrupt, e40) */
606 li r3,KVM_INST_FETCH_FAILED
608 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
611 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
612 11: stw r3,VCPU_LAST_INST(r9)
614 /* these are volatile across C function calls */
621 /* If this is a page table miss then see if it's theirs or ours */
622 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
624 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
626 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
628 /* See if this is a leftover HDEC interrupt */
629 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
635 /* See if this is an hcall we can handle in real mode */
636 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
637 beq hcall_try_real_mode
639 /* Check for mediated interrupts (could be done earlier really ...) */
641 cmpwi r12,BOOK3S_INTERRUPT_EXTERNAL
647 bne bounce_ext_interrupt
649 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
652 hcall_real_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
658 std r5,VCPU_DEC_EXPIRES(r9)
660 /* Save more register state */
664 stw r7, VCPU_DSISR(r9)
666 /* don't overwrite fault_dar/fault_dsisr if HDSI */
667 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
669 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
670 std r6, VCPU_FAULT_DAR(r9)
671 stw r7, VCPU_FAULT_DSISR(r9)
673 /* Save guest CTRL register, set runlatch to 1 */
674 6: mfspr r6,SPRN_CTRLF
681 /* Read the guest SLB and save it away */
682 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
688 andis. r0,r8,SLB_ESID_V@h
690 add r8,r8,r6 /* put index in */
692 std r8,VCPU_SLB_E(r7)
693 std r3,VCPU_SLB_V(r7)
694 addi r7,r7,VCPU_SLB_SIZE
698 stw r5,VCPU_SLB_MAX(r9)
701 * Save the guest PURR/SPURR
709 std r6,VCPU_SPURR(r9)
714 * Restore host PURR/SPURR and add guest times
715 * so that the time in the guest gets accounted.
717 ld r3,HSTATE_PURR(r13)
718 ld r4,HSTATE_SPURR(r13)
723 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
731 hdec_soon: /* r9 = vcpu, r12 = trap, r13 = paca */
734 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
736 * POWER7 guest -> host partition switch code.
737 * We don't have to lock against tlbies but we do
738 * have to coordinate the hardware threads.
740 /* Increment the threads-exiting-guest count in the 0xff00
741 bits of vcore->entry_exit_count */
743 ld r5,HSTATE_KVM_VCORE(r13)
744 addi r6,r5,VCORE_ENTRY_EXIT
752 * At this point we have an interrupt that we have to pass
753 * up to the kernel or qemu; we can't handle it in real mode.
754 * Thus we have to do a partition switch, so we have to
755 * collect the other threads, if we are the first thread
756 * to take an interrupt. To do this, we set the HDEC to 0,
757 * which causes an HDEC interrupt in all threads within 2ns
758 * because the HDEC register is shared between all 4 threads.
759 * However, we don't need to bother if this is an HDEC
760 * interrupt, since the other threads will already be on their
761 * way here in that case.
763 cmpwi r3,0x100 /* Are we the first here? */
765 cmpwi r3,1 /* Are any other threads in the guest? */
767 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
773 * Send an IPI to any napping threads, since an HDEC interrupt
774 * doesn't wake CPUs up from nap.
776 lwz r3,VCORE_NAPPING_THREADS(r5)
780 andc. r3,r3,r0 /* no sense IPI'ing ourselves */
782 mulli r4,r4,PACA_SIZE /* get paca for thread 0 */
786 ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */
789 stbcix r0,r7,r8 /* trigger the IPI */
794 /* Secondary threads wait for primary to do partition switch */
795 43: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
796 ld r5,HSTATE_KVM_VCORE(r13)
801 13: lbz r3,VCORE_IN_GUEST(r5)
807 /* Primary thread waits for all the secondaries to exit guest */
808 15: lwz r3,VCORE_ENTRY_EXIT(r5)
815 /* Primary thread switches back to host partition */
816 ld r6,KVM_HOST_SDR1(r4)
817 lwz r7,KVM_HOST_LPID(r4)
818 li r8,LPID_RSVD /* switch to reserved LPID */
821 mtspr SPRN_SDR1,r6 /* switch to partition page table */
825 stb r0,VCORE_IN_GUEST(r5)
826 lis r8,0x7fff /* MAX_INT@h */
829 16: ld r8,KVM_HOST_LPCR(r4)
835 * PPC970 guest -> host partition switch code.
836 * We have to lock against concurrent tlbies, and
837 * we have to flush the whole TLB.
839 32: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
841 /* Take the guest's tlbie_lock */
842 lwz r8,PACA_LOCK_TOKEN(r13)
843 addi r3,r4,KVM_TLBIE_LOCK
851 ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */
853 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
857 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
860 stw r0,0(r3) /* drop guest tlbie_lock */
862 /* invalidate the whole TLB */
871 /* take native_tlbie_lock */
872 ld r3,toc_tlbie_lock@toc(2)
880 ld r6,KVM_HOST_SDR1(r4)
881 mtspr SPRN_SDR1,r6 /* switch to host page table */
883 /* Set up host HID4 value */
888 stw r0,0(r3) /* drop native_tlbie_lock */
890 lis r8,0x7fff /* MAX_INT@h */
893 /* Disable HDEC interrupts */
896 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
906 /* load host SLB entries */
907 33: ld r8,PACA_SLBSHADOWPTR(r13)
910 ld r5,SLBSHADOW_SAVEAREA(r8)
911 ld r6,SLBSHADOW_SAVEAREA+8(r8)
912 andis. r7,r5,SLB_ESID_V@h
918 /* Save and reset AMR and UAMOR before turning on the MMU */
923 std r6,VCPU_UAMOR(r9)
926 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
928 /* Restore host DABR and DABRX */
929 ld r5,HSTATE_DABR(r13)
934 /* Switch DSCR back to host value */
937 ld r7, HSTATE_DSCR(r13)
938 std r8, VCPU_DSCR(r7)
940 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
942 /* Save non-volatile GPRs */
943 std r14, VCPU_GPR(r14)(r9)
944 std r15, VCPU_GPR(r15)(r9)
945 std r16, VCPU_GPR(r16)(r9)
946 std r17, VCPU_GPR(r17)(r9)
947 std r18, VCPU_GPR(r18)(r9)
948 std r19, VCPU_GPR(r19)(r9)
949 std r20, VCPU_GPR(r20)(r9)
950 std r21, VCPU_GPR(r21)(r9)
951 std r22, VCPU_GPR(r22)(r9)
952 std r23, VCPU_GPR(r23)(r9)
953 std r24, VCPU_GPR(r24)(r9)
954 std r25, VCPU_GPR(r25)(r9)
955 std r26, VCPU_GPR(r26)(r9)
956 std r27, VCPU_GPR(r27)(r9)
957 std r28, VCPU_GPR(r28)(r9)
958 std r29, VCPU_GPR(r29)(r9)
959 std r30, VCPU_GPR(r30)(r9)
960 std r31, VCPU_GPR(r31)(r9)
967 std r3, VCPU_SPRG0(r9)
968 std r4, VCPU_SPRG1(r9)
969 std r5, VCPU_SPRG2(r9)
970 std r6, VCPU_SPRG3(r9)
972 /* Increment yield count if they have a VPA */
973 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
976 lwz r3, LPPACA_YIELDCOUNT(r8)
978 stw r3, LPPACA_YIELDCOUNT(r8)
980 /* Save PMU registers if requested */
981 /* r8 and cr0.eq are live here */
983 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
984 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
985 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
987 beq 21f /* if no VPA, save PMU stuff anyway */
988 lbz r7, LPPACA_PMCINUSE(r8)
989 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
991 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
993 21: mfspr r5, SPRN_MMCR1
995 std r4, VCPU_MMCR(r9)
996 std r5, VCPU_MMCR + 8(r9)
997 std r6, VCPU_MMCR + 16(r9)
1005 mfspr r10, SPRN_PMC7
1006 mfspr r11, SPRN_PMC8
1007 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1008 stw r3, VCPU_PMC(r9)
1009 stw r4, VCPU_PMC + 4(r9)
1010 stw r5, VCPU_PMC + 8(r9)
1011 stw r6, VCPU_PMC + 12(r9)
1012 stw r7, VCPU_PMC + 16(r9)
1013 stw r8, VCPU_PMC + 20(r9)
1015 stw r10, VCPU_PMC + 24(r9)
1016 stw r11, VCPU_PMC + 28(r9)
1017 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1023 /* Secondary threads go off to take a nap on POWER7 */
1025 lwz r0,VCPU_PTID(r3)
1028 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1031 * Reload DEC. HDEC interrupts were disabled when
1032 * we reloaded the host's LPCR value.
1034 ld r3, HSTATE_DECEXP(r13)
1039 /* Reload the host's PMU registers */
1040 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
1041 lbz r4, LPPACA_PMCINUSE(r3)
1043 beq 23f /* skip if not */
1044 lwz r3, HSTATE_PMC(r13)
1045 lwz r4, HSTATE_PMC + 4(r13)
1046 lwz r5, HSTATE_PMC + 8(r13)
1047 lwz r6, HSTATE_PMC + 12(r13)
1048 lwz r8, HSTATE_PMC + 16(r13)
1049 lwz r9, HSTATE_PMC + 20(r13)
1051 lwz r10, HSTATE_PMC + 24(r13)
1052 lwz r11, HSTATE_PMC + 28(r13)
1053 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1061 mtspr SPRN_PMC7, r10
1062 mtspr SPRN_PMC8, r11
1063 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1064 ld r3, HSTATE_MMCR(r13)
1065 ld r4, HSTATE_MMCR + 8(r13)
1066 ld r5, HSTATE_MMCR + 16(r13)
1067 mtspr SPRN_MMCR1, r4
1068 mtspr SPRN_MMCRA, r5
1069 mtspr SPRN_MMCR0, r3
1073 * For external and machine check interrupts, we need
1074 * to call the Linux handler to process the interrupt.
1075 * We do that by jumping to the interrupt vector address
1076 * which we have in r12. The [h]rfid at the end of the
1077 * handler will return to the book3s_hv_interrupts.S code.
1078 * For other interrupts we do the rfid to get back
1079 * to the book3s_interrupts.S code here.
1081 ld r8, HSTATE_VMHANDLER(r13)
1082 ld r7, HSTATE_HOST_MSR(r13)
1084 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1086 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1088 /* RFI into the highmem handler, or branch to interrupt handler */
1093 mtmsrd r6, 1 /* Clear RI in MSR */
1102 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1103 mtspr SPRN_HSRR0, r8
1104 mtspr SPRN_HSRR1, r7
1108 * Check whether an HDSI is an HPTE not found fault or something else.
1109 * If it is an HPTE not found fault that is due to the guest accessing
1110 * a page that they have mapped but which we have paged out, then
1111 * we continue on with the guest exit path. In all other cases,
1112 * reflect the HDSI to the guest as a DSI.
1116 mfspr r6, SPRN_HDSISR
1117 /* HPTE not found fault or protection fault? */
1118 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1119 beq 1f /* if not, send it to the guest */
1120 andi. r0, r11, MSR_DR /* data relocation enabled? */
1123 PPC_SLBFEE_DOT(r5, r0) /* if so, look up SLB */
1124 bne 1f /* if no SLB entry found */
1125 4: std r4, VCPU_FAULT_DAR(r9)
1126 stw r6, VCPU_FAULT_DSISR(r9)
1128 /* Search the hash table. */
1129 mr r3, r9 /* vcpu pointer */
1130 li r7, 1 /* data fault */
1131 bl .kvmppc_hpte_hv_fault
1132 ld r9, HSTATE_KVM_VCPU(r13)
1134 ld r11, VCPU_MSR(r9)
1135 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1136 cmpdi r3, 0 /* retry the instruction */
1138 cmpdi r3, -1 /* handle in kernel mode */
1140 cmpdi r3, -2 /* MMIO emulation; need instr word */
1143 /* Synthesize a DSI for the guest */
1144 ld r4, VCPU_FAULT_DAR(r9)
1146 1: mtspr SPRN_DAR, r4
1147 mtspr SPRN_DSISR, r6
1148 mtspr SPRN_SRR0, r10
1149 mtspr SPRN_SRR1, r11
1150 li r10, BOOK3S_INTERRUPT_DATA_STORAGE
1151 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1153 6: ld r7, VCPU_CTR(r9)
1154 lwz r8, VCPU_XER(r9)
1160 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1161 ld r5, KVM_VRMA_SLB_V(r5)
1164 /* If this is for emulated MMIO, load the instruction word */
1165 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1167 /* Set guest mode to 'jump over instruction' so if lwz faults
1168 * we'll just continue at the next IP. */
1169 li r0, KVM_GUEST_MODE_SKIP
1170 stb r0, HSTATE_IN_GUEST(r13)
1172 /* Do the access with MSR:DR enabled */
1174 ori r4, r3, MSR_DR /* Enable paging for data */
1179 /* Store the result */
1180 stw r8, VCPU_LAST_INST(r9)
1182 /* Unset guest mode. */
1183 li r0, KVM_GUEST_MODE_NONE
1184 stb r0, HSTATE_IN_GUEST(r13)
1188 * Similarly for an HISI, reflect it to the guest as an ISI unless
1189 * it is an HPTE not found fault for a page that we have paged out.
1192 andis. r0, r11, SRR1_ISI_NOPT@h
1194 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1197 PPC_SLBFEE_DOT(r5, r0) /* if so, look up SLB */
1198 bne 1f /* if no SLB entry found */
1200 /* Search the hash table. */
1201 mr r3, r9 /* vcpu pointer */
1204 li r7, 0 /* instruction fault */
1205 bl .kvmppc_hpte_hv_fault
1206 ld r9, HSTATE_KVM_VCPU(r13)
1208 ld r11, VCPU_MSR(r9)
1209 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1210 cmpdi r3, 0 /* retry the instruction */
1212 cmpdi r3, -1 /* handle in kernel mode */
1215 /* Synthesize an ISI for the guest */
1217 1: mtspr SPRN_SRR0, r10
1218 mtspr SPRN_SRR1, r11
1219 li r10, BOOK3S_INTERRUPT_INST_STORAGE
1220 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1222 6: ld r7, VCPU_CTR(r9)
1223 lwz r8, VCPU_XER(r9)
1229 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1230 ld r5, KVM_VRMA_SLB_V(r6)
1234 * Try to handle an hcall in real mode.
1235 * Returns to the guest if we handle it, or continues on up to
1236 * the kernel if we can't (i.e. if we don't have a handler for
1237 * it, or if the handler returns H_TOO_HARD).
1239 .globl hcall_try_real_mode
1240 hcall_try_real_mode:
1241 ld r3,VCPU_GPR(r3)(r9)
1245 cmpldi r3,hcall_real_table_end - hcall_real_table
1247 LOAD_REG_ADDR(r4, hcall_real_table)
1253 mr r3,r9 /* get vcpu pointer */
1254 ld r4,VCPU_GPR(r4)(r9)
1257 beq hcall_real_fallback
1258 ld r4,HSTATE_KVM_VCPU(r13)
1259 std r3,VCPU_GPR(r3)(r4)
1264 /* We've attempted a real mode hcall, but it's punted it back
1265 * to userspace. We need to restore some clobbered volatiles
1266 * before resuming the pass-it-to-qemu path */
1267 hcall_real_fallback:
1268 li r12,BOOK3S_INTERRUPT_SYSCALL
1269 ld r9, HSTATE_KVM_VCPU(r13)
1273 .globl hcall_real_table
1275 .long 0 /* 0 - unused */
1276 .long .kvmppc_h_remove - hcall_real_table
1277 .long .kvmppc_h_enter - hcall_real_table
1278 .long .kvmppc_h_read - hcall_real_table
1279 .long 0 /* 0x10 - H_CLEAR_MOD */
1280 .long 0 /* 0x14 - H_CLEAR_REF */
1281 .long .kvmppc_h_protect - hcall_real_table
1282 .long 0 /* 0x1c - H_GET_TCE */
1283 .long .kvmppc_h_put_tce - hcall_real_table
1284 .long 0 /* 0x24 - H_SET_SPRG0 */
1285 .long .kvmppc_h_set_dabr - hcall_real_table
1331 .long .kvmppc_h_cede - hcall_real_table
1348 .long .kvmppc_h_bulk_remove - hcall_real_table
1349 hcall_real_table_end:
1355 bounce_ext_interrupt:
1359 li r10,BOOK3S_INTERRUPT_EXTERNAL
1360 li r11,(MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1364 _GLOBAL(kvmppc_h_set_dabr)
1365 std r4,VCPU_DABR(r3)
1370 _GLOBAL(kvmppc_h_cede)
1372 std r11,VCPU_MSR(r3)
1374 stb r0,VCPU_CEDED(r3)
1375 sync /* order setting ceded vs. testing prodded */
1376 lbz r5,VCPU_PRODDED(r3)
1379 li r0,0 /* set trap to 0 to say hcall is handled */
1380 stw r0,VCPU_TRAP(r3)
1382 std r0,VCPU_GPR(r3)(r3)
1384 b 2f /* just send it up to host on 970 */
1385 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
1388 * Set our bit in the bitmask of napping threads unless all the
1389 * other threads are already napping, in which case we send this
1392 ld r5,HSTATE_KVM_VCORE(r13)
1393 lwz r6,VCPU_PTID(r3)
1394 lwz r8,VCORE_ENTRY_EXIT(r5)
1398 addi r6,r5,VCORE_NAPPING_THREADS
1407 stb r0,HSTATE_NAPPING(r13)
1408 /* order napping_threads update vs testing entry_exit_count */
1411 lwz r7,VCORE_ENTRY_EXIT(r5)
1413 bge 33f /* another thread already exiting */
1416 * Although not specifically required by the architecture, POWER7
1417 * preserves the following registers in nap mode, even if an SMT mode
1418 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
1419 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
1421 /* Save non-volatile GPRs */
1422 std r14, VCPU_GPR(r14)(r3)
1423 std r15, VCPU_GPR(r15)(r3)
1424 std r16, VCPU_GPR(r16)(r3)
1425 std r17, VCPU_GPR(r17)(r3)
1426 std r18, VCPU_GPR(r18)(r3)
1427 std r19, VCPU_GPR(r19)(r3)
1428 std r20, VCPU_GPR(r20)(r3)
1429 std r21, VCPU_GPR(r21)(r3)
1430 std r22, VCPU_GPR(r22)(r3)
1431 std r23, VCPU_GPR(r23)(r3)
1432 std r24, VCPU_GPR(r24)(r3)
1433 std r25, VCPU_GPR(r25)(r3)
1434 std r26, VCPU_GPR(r26)(r3)
1435 std r27, VCPU_GPR(r27)(r3)
1436 std r28, VCPU_GPR(r28)(r3)
1437 std r29, VCPU_GPR(r29)(r3)
1438 std r30, VCPU_GPR(r30)(r3)
1439 std r31, VCPU_GPR(r31)(r3)
1445 * Take a nap until a decrementer or external interrupt occurs,
1446 * with PECE1 (wake on decr) and PECE0 (wake on external) set in LPCR
1449 stb r0,PACAPROCSTART(r13)
1451 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
1455 std r0, HSTATE_SCRATCH0(r13)
1457 ld r0, HSTATE_SCRATCH0(r13)
1464 /* Woken by external or decrementer interrupt */
1465 ld r1, HSTATE_HOST_R1(r13)
1468 /* If we're a secondary thread and we got here by an IPI, ack it */
1469 ld r4,HSTATE_KVM_VCPU(r13)
1470 lwz r3,VCPU_PTID(r4)
1474 rlwinm r3,r3,44-31,0x7 /* extract wake reason field */
1475 cmpwi r3,4 /* was it an external interrupt? */
1477 ld r5, HSTATE_XICS_PHYS(r13)
1481 lwzcix r8,r5,r7 /* ack the interrupt */
1483 stbcix r0,r5,r6 /* clear it */
1484 stwcix r8,r5,r7 /* EOI it */
1486 /* load up FP state */
1490 ld r14, VCPU_GPR(r14)(r4)
1491 ld r15, VCPU_GPR(r15)(r4)
1492 ld r16, VCPU_GPR(r16)(r4)
1493 ld r17, VCPU_GPR(r17)(r4)
1494 ld r18, VCPU_GPR(r18)(r4)
1495 ld r19, VCPU_GPR(r19)(r4)
1496 ld r20, VCPU_GPR(r20)(r4)
1497 ld r21, VCPU_GPR(r21)(r4)
1498 ld r22, VCPU_GPR(r22)(r4)
1499 ld r23, VCPU_GPR(r23)(r4)
1500 ld r24, VCPU_GPR(r24)(r4)
1501 ld r25, VCPU_GPR(r25)(r4)
1502 ld r26, VCPU_GPR(r26)(r4)
1503 ld r27, VCPU_GPR(r27)(r4)
1504 ld r28, VCPU_GPR(r28)(r4)
1505 ld r29, VCPU_GPR(r29)(r4)
1506 ld r30, VCPU_GPR(r30)(r4)
1507 ld r31, VCPU_GPR(r31)(r4)
1509 /* clear our bit in vcore->napping_threads */
1510 33: ld r5,HSTATE_KVM_VCORE(r13)
1511 lwz r3,VCPU_PTID(r4)
1514 addi r6,r5,VCORE_NAPPING_THREADS
1520 stb r0,HSTATE_NAPPING(r13)
1522 /* see if any other thread is already exiting */
1523 lwz r0,VCORE_ENTRY_EXIT(r5)
1525 blt kvmppc_cede_reentry /* if not go back to guest */
1527 /* some threads are exiting, so go to the guest exit path */
1528 b hcall_real_fallback
1530 /* cede when already previously prodded case */
1532 stb r0,VCPU_PRODDED(r3)
1533 sync /* order testing prodded vs. clearing ceded */
1534 stb r0,VCPU_CEDED(r3)
1538 /* we've ceded but we want to give control to the host */
1543 ld r5,HSTATE_KVM_VCORE(r13)
1545 13: lbz r3,VCORE_IN_GUEST(r5)
1549 ld r11,PACA_SLBSHADOWPTR(r13)
1551 .rept SLB_NUM_BOLTED
1552 ld r5,SLBSHADOW_SAVEAREA(r11)
1553 ld r6,SLBSHADOW_SAVEAREA+8(r11)
1554 andis. r7,r5,SLB_ESID_V@h
1561 /* Clear any pending IPI - assume we're a secondary thread */
1562 ld r5, HSTATE_XICS_PHYS(r13)
1564 lwzcix r3, r5, r7 /* ack any pending interrupt */
1565 rlwinm. r0, r3, 0, 0xffffff /* any pending? */
1570 stbcix r0, r5, r6 /* clear the IPI */
1571 stwcix r3, r5, r7 /* EOI it */
1574 /* increment the nap count and then go to nap mode */
1575 ld r4, HSTATE_KVM_VCORE(r13)
1576 addi r4, r4, VCORE_NAP_COUNT
1577 lwsync /* make previous updates visible */
1585 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
1589 std r0, HSTATE_SCRATCH0(r13)
1591 ld r0, HSTATE_SCRATCH0(r13)
1598 * Save away FP, VMX and VSX registers.
1601 _GLOBAL(kvmppc_save_fp)
1604 #ifdef CONFIG_ALTIVEC
1606 oris r8,r8,MSR_VEC@h
1607 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1611 oris r8,r8,MSR_VSX@h
1612 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1620 li r6,reg*16+VCPU_VSRS
1628 stfd reg,reg*8+VCPU_FPRS(r3)
1632 ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
1635 stfd fr0,VCPU_FPSCR(r3)
1637 #ifdef CONFIG_ALTIVEC
1641 li r6,reg*16+VCPU_VRS
1648 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1650 mfspr r6,SPRN_VRSAVE
1651 stw r6,VCPU_VRSAVE(r3)
1657 * Load up FP, VMX and VSX registers
1660 .globl kvmppc_load_fp
1664 #ifdef CONFIG_ALTIVEC
1666 oris r8,r8,MSR_VEC@h
1667 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1671 oris r8,r8,MSR_VSX@h
1672 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1676 lfd fr0,VCPU_FPSCR(r4)
1682 li r7,reg*16+VCPU_VSRS
1690 lfd reg,reg*8+VCPU_FPRS(r4)
1694 ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
1697 #ifdef CONFIG_ALTIVEC
1704 li r7,reg*16+VCPU_VRS
1708 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1710 lwz r7,VCPU_VRSAVE(r4)
1711 mtspr SPRN_VRSAVE,r7