4 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 #include <linux/kernel.h>
12 #include <linux/kprobes.h>
13 #include <linux/ptrace.h>
14 #include <asm/sstep.h>
15 #include <asm/processor.h>
16 #include <asm/uaccess.h>
17 #include <asm/cputable.h>
19 extern char system_call_common[];
22 /* Bits in SRR1 that are copied from MSR */
23 #define MSR_MASK 0xffffffff87c0ffffUL
25 #define MSR_MASK 0x87c0ffff
29 #define XER_SO 0x80000000U
30 #define XER_OV 0x40000000U
31 #define XER_CA 0x20000000U
35 * Functions in ldstfp.S
37 extern int do_lfs(int rn, unsigned long ea);
38 extern int do_lfd(int rn, unsigned long ea);
39 extern int do_stfs(int rn, unsigned long ea);
40 extern int do_stfd(int rn, unsigned long ea);
41 extern int do_lvx(int rn, unsigned long ea);
42 extern int do_stvx(int rn, unsigned long ea);
43 extern int do_lxvd2x(int rn, unsigned long ea);
44 extern int do_stxvd2x(int rn, unsigned long ea);
48 * Determine whether a conditional branch instruction would branch.
50 static int __kprobes branch_taken(unsigned int instr, struct pt_regs *regs)
52 unsigned int bo = (instr >> 21) & 0x1f;
56 /* decrement counter */
58 if (((bo >> 1) & 1) ^ (regs->ctr == 0))
61 if ((bo & 0x10) == 0) {
62 /* check bit from CR */
63 bi = (instr >> 16) & 0x1f;
64 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1))
71 static long __kprobes address_ok(struct pt_regs *regs, unsigned long ea, int nb)
75 return __access_ok(ea, nb, USER_DS);
79 * Calculate effective address for a D-form instruction
81 static unsigned long __kprobes dform_ea(unsigned int instr, struct pt_regs *regs)
86 ra = (instr >> 16) & 0x1f;
87 ea = (signed short) instr; /* sign-extend */
90 if (instr & 0x04000000) /* update forms */
94 if (!(regs->msr & MSR_SF))
102 * Calculate effective address for a DS-form instruction
104 static unsigned long __kprobes dsform_ea(unsigned int instr, struct pt_regs *regs)
109 ra = (instr >> 16) & 0x1f;
110 ea = (signed short) (instr & ~3); /* sign-extend */
113 if ((instr & 3) == 1) /* update forms */
116 if (!(regs->msr & MSR_SF))
120 #endif /* __powerpc64 */
123 * Calculate effective address for an X-form instruction
125 static unsigned long __kprobes xform_ea(unsigned int instr, struct pt_regs *regs,
131 ra = (instr >> 16) & 0x1f;
132 rb = (instr >> 11) & 0x1f;
136 if (do_update) /* update forms */
140 if (!(regs->msr & MSR_SF))
147 * Return the largest power of 2, not greater than sizeof(unsigned long),
148 * such that x is a multiple of it.
150 static inline unsigned long max_align(unsigned long x)
152 x |= sizeof(unsigned long);
153 return x & -x; /* isolates rightmost bit */
157 static inline unsigned long byterev_2(unsigned long x)
159 return ((x >> 8) & 0xff) | ((x & 0xff) << 8);
162 static inline unsigned long byterev_4(unsigned long x)
164 return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) |
165 ((x & 0xff00) << 8) | ((x & 0xff) << 24);
169 static inline unsigned long byterev_8(unsigned long x)
171 return (byterev_4(x) << 32) | byterev_4(x >> 32);
175 static int __kprobes read_mem_aligned(unsigned long *dest, unsigned long ea,
183 err = __get_user(x, (unsigned char __user *) ea);
186 err = __get_user(x, (unsigned short __user *) ea);
189 err = __get_user(x, (unsigned int __user *) ea);
193 err = __get_user(x, (unsigned long __user *) ea);
202 static int __kprobes read_mem_unaligned(unsigned long *dest, unsigned long ea,
203 int nb, struct pt_regs *regs)
206 unsigned long x, b, c;
208 /* unaligned, do this in pieces */
210 for (; nb > 0; nb -= c) {
214 err = read_mem_aligned(&b, ea, c);
217 x = (x << (8 * c)) + b;
225 * Read memory at address ea for nb bytes, return 0 for success
226 * or -EFAULT if an error occurred.
228 static int __kprobes read_mem(unsigned long *dest, unsigned long ea, int nb,
229 struct pt_regs *regs)
231 if (!address_ok(regs, ea, nb))
233 if ((ea & (nb - 1)) == 0)
234 return read_mem_aligned(dest, ea, nb);
235 return read_mem_unaligned(dest, ea, nb, regs);
238 static int __kprobes write_mem_aligned(unsigned long val, unsigned long ea,
245 err = __put_user(val, (unsigned char __user *) ea);
248 err = __put_user(val, (unsigned short __user *) ea);
251 err = __put_user(val, (unsigned int __user *) ea);
255 err = __put_user(val, (unsigned long __user *) ea);
262 static int __kprobes write_mem_unaligned(unsigned long val, unsigned long ea,
263 int nb, struct pt_regs *regs)
268 /* unaligned or little-endian, do this in pieces */
269 for (; nb > 0; nb -= c) {
273 err = write_mem_aligned(val >> (nb - c) * 8, ea, c);
282 * Write memory at address ea for nb bytes, return 0 for success
283 * or -EFAULT if an error occurred.
285 static int __kprobes write_mem(unsigned long val, unsigned long ea, int nb,
286 struct pt_regs *regs)
288 if (!address_ok(regs, ea, nb))
290 if ((ea & (nb - 1)) == 0)
291 return write_mem_aligned(val, ea, nb);
292 return write_mem_unaligned(val, ea, nb, regs);
295 #ifdef CONFIG_PPC_FPU
297 * Check the address and alignment, and call func to do the actual
300 static int __kprobes do_fp_load(int rn, int (*func)(int, unsigned long),
301 unsigned long ea, int nb,
302 struct pt_regs *regs)
305 unsigned long val[sizeof(double) / sizeof(long)];
308 if (!address_ok(regs, ea, nb))
311 return (*func)(rn, ea);
312 ptr = (unsigned long) &val[0];
313 if (sizeof(unsigned long) == 8 || nb == 4) {
314 err = read_mem_unaligned(&val[0], ea, nb, regs);
315 ptr += sizeof(unsigned long) - nb;
317 /* reading a double on 32-bit */
318 err = read_mem_unaligned(&val[0], ea, 4, regs);
320 err = read_mem_unaligned(&val[1], ea + 4, 4, regs);
324 return (*func)(rn, ptr);
327 static int __kprobes do_fp_store(int rn, int (*func)(int, unsigned long),
328 unsigned long ea, int nb,
329 struct pt_regs *regs)
332 unsigned long val[sizeof(double) / sizeof(long)];
335 if (!address_ok(regs, ea, nb))
338 return (*func)(rn, ea);
339 ptr = (unsigned long) &val[0];
340 if (sizeof(unsigned long) == 8 || nb == 4) {
341 ptr += sizeof(unsigned long) - nb;
342 err = (*func)(rn, ptr);
345 err = write_mem_unaligned(val[0], ea, nb, regs);
347 /* writing a double on 32-bit */
348 err = (*func)(rn, ptr);
351 err = write_mem_unaligned(val[0], ea, 4, regs);
353 err = write_mem_unaligned(val[1], ea + 4, 4, regs);
359 #ifdef CONFIG_ALTIVEC
360 /* For Altivec/VMX, no need to worry about alignment */
361 static int __kprobes do_vec_load(int rn, int (*func)(int, unsigned long),
362 unsigned long ea, struct pt_regs *regs)
364 if (!address_ok(regs, ea & ~0xfUL, 16))
366 return (*func)(rn, ea);
369 static int __kprobes do_vec_store(int rn, int (*func)(int, unsigned long),
370 unsigned long ea, struct pt_regs *regs)
372 if (!address_ok(regs, ea & ~0xfUL, 16))
374 return (*func)(rn, ea);
376 #endif /* CONFIG_ALTIVEC */
379 static int __kprobes do_vsx_load(int rn, int (*func)(int, unsigned long),
380 unsigned long ea, struct pt_regs *regs)
383 unsigned long val[2];
385 if (!address_ok(regs, ea, 16))
388 return (*func)(rn, ea);
389 err = read_mem_unaligned(&val[0], ea, 8, regs);
391 err = read_mem_unaligned(&val[1], ea + 8, 8, regs);
393 err = (*func)(rn, (unsigned long) &val[0]);
397 static int __kprobes do_vsx_store(int rn, int (*func)(int, unsigned long),
398 unsigned long ea, struct pt_regs *regs)
401 unsigned long val[2];
403 if (!address_ok(regs, ea, 16))
406 return (*func)(rn, ea);
407 err = (*func)(rn, (unsigned long) &val[0]);
410 err = write_mem_unaligned(val[0], ea, 8, regs);
412 err = write_mem_unaligned(val[1], ea + 8, 8, regs);
415 #endif /* CONFIG_VSX */
417 #define __put_user_asmx(x, addr, err, op, cr) \
418 __asm__ __volatile__( \
419 "1: " op " %2,0,%3\n" \
422 ".section .fixup,\"ax\"\n" \
426 ".section __ex_table,\"a\"\n" \
427 PPC_LONG_ALIGN "\n" \
430 : "=r" (err), "=r" (cr) \
431 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
433 #define __get_user_asmx(x, addr, err, op) \
434 __asm__ __volatile__( \
435 "1: "op" %1,0,%2\n" \
437 ".section .fixup,\"ax\"\n" \
441 ".section __ex_table,\"a\"\n" \
442 PPC_LONG_ALIGN "\n" \
445 : "=r" (err), "=r" (x) \
446 : "r" (addr), "i" (-EFAULT), "0" (err))
448 #define __cacheop_user_asmx(addr, err, op) \
449 __asm__ __volatile__( \
452 ".section .fixup,\"ax\"\n" \
456 ".section __ex_table,\"a\"\n" \
457 PPC_LONG_ALIGN "\n" \
461 : "r" (addr), "i" (-EFAULT), "0" (err))
463 static void __kprobes set_cr0(struct pt_regs *regs, int rd)
465 long val = regs->gpr[rd];
467 regs->ccr = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
469 if (!(regs->msr & MSR_SF))
473 regs->ccr |= 0x80000000;
475 regs->ccr |= 0x40000000;
477 regs->ccr |= 0x20000000;
480 static void __kprobes add_with_carry(struct pt_regs *regs, int rd,
481 unsigned long val1, unsigned long val2,
482 unsigned long carry_in)
484 unsigned long val = val1 + val2;
490 if (!(regs->msr & MSR_SF)) {
491 val = (unsigned int) val;
492 val1 = (unsigned int) val1;
495 if (val < val1 || (carry_in && val == val1))
498 regs->xer &= ~XER_CA;
501 static void __kprobes do_cmp_signed(struct pt_regs *regs, long v1, long v2,
504 unsigned int crval, shift;
506 crval = (regs->xer >> 31) & 1; /* get SO bit */
513 shift = (7 - crfld) * 4;
514 regs->ccr = (regs->ccr & ~(0xf << shift)) | (crval << shift);
517 static void __kprobes do_cmp_unsigned(struct pt_regs *regs, unsigned long v1,
518 unsigned long v2, int crfld)
520 unsigned int crval, shift;
522 crval = (regs->xer >> 31) & 1; /* get SO bit */
529 shift = (7 - crfld) * 4;
530 regs->ccr = (regs->ccr & ~(0xf << shift)) | (crval << shift);
534 * Elements of 32-bit rotate and mask instructions.
536 #define MASK32(mb, me) ((0xffffffffUL >> (mb)) + \
537 ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
539 #define MASK64_L(mb) (~0UL >> (mb))
540 #define MASK64_R(me) ((signed long)-0x8000000000000000L >> (me))
541 #define MASK64(mb, me) (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
542 #define DATA32(x) (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32))
544 #define DATA32(x) (x)
546 #define ROTATE(x, n) ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
549 * Emulate instructions that cause a transfer of control,
550 * loads and stores, and a few other instructions.
551 * Returns 1 if the step was emulated, 0 if not,
552 * or -1 if the instruction is one that should not be stepped,
553 * such as an rfid, or a mtmsrd that would clear MSR_RI.
555 int __kprobes emulate_step(struct pt_regs *regs, unsigned int instr)
557 unsigned int opcode, ra, rb, rd, spr, u;
558 unsigned long int imm;
559 unsigned long int val, val2;
560 unsigned long int ea;
561 unsigned int cr, mb, me, sh;
563 unsigned long old_ra;
566 opcode = instr >> 26;
569 imm = (signed short)(instr & 0xfffc);
570 if ((instr & 2) == 0)
573 if ((regs->msr & MSR_SF) == 0)
574 regs->nip &= 0xffffffffUL;
576 regs->link = regs->nip;
577 if (branch_taken(instr, regs))
583 * N.B. this uses knowledge about how the syscall
584 * entry code works. If that is changed, this will
585 * need to be changed also.
587 if (regs->gpr[0] == 0x1ebe &&
588 cpu_has_feature(CPU_FTR_REAL_LE)) {
592 regs->gpr[9] = regs->gpr[13];
593 regs->gpr[10] = MSR_KERNEL;
594 regs->gpr[11] = regs->nip + 4;
595 regs->gpr[12] = regs->msr & MSR_MASK;
596 regs->gpr[13] = (unsigned long) get_paca();
597 regs->nip = (unsigned long) &system_call_common;
598 regs->msr = MSR_KERNEL;
602 imm = instr & 0x03fffffc;
603 if (imm & 0x02000000)
605 if ((instr & 2) == 0)
608 regs->link = regs->nip + 4;
609 if ((regs->msr & MSR_SF) == 0)
610 regs->link &= 0xffffffffUL;
612 if ((regs->msr & MSR_SF) == 0)
617 switch ((instr >> 1) & 0x3ff) {
619 case 528: /* bcctr */
620 imm = (instr & 0x400)? regs->ctr: regs->link;
622 if ((regs->msr & MSR_SF) == 0) {
623 regs->nip &= 0xffffffffUL;
627 regs->link = regs->nip;
628 if (branch_taken(instr, regs))
632 case 18: /* rfid, scary */
635 case 150: /* isync */
640 case 129: /* crandc */
641 case 193: /* crxor */
642 case 225: /* crnand */
643 case 257: /* crand */
644 case 289: /* creqv */
645 case 417: /* crorc */
647 ra = (instr >> 16) & 0x1f;
648 rb = (instr >> 11) & 0x1f;
649 rd = (instr >> 21) & 0x1f;
650 ra = (regs->ccr >> (31 - ra)) & 1;
651 rb = (regs->ccr >> (31 - rb)) & 1;
652 val = (instr >> (6 + ra * 2 + rb)) & 1;
653 regs->ccr = (regs->ccr & ~(1UL << (31 - rd))) |
659 switch ((instr >> 1) & 0x3ff) {
662 switch ((instr >> 21) & 3) {
664 asm volatile("lwsync" : : : "memory");
666 case 2: /* ptesync */
667 asm volatile("ptesync" : : : "memory");
674 case 854: /* eieio */
681 /* Following cases refer to regs->gpr[], so we need all regs */
682 if (!FULL_REGS(regs))
685 rd = (instr >> 21) & 0x1f;
686 ra = (instr >> 16) & 0x1f;
687 rb = (instr >> 11) & 0x1f;
691 regs->gpr[rd] = regs->gpr[ra] * (short) instr;
696 add_with_carry(regs, rd, ~regs->gpr[ra], imm, 1);
700 imm = (unsigned short) instr;
704 val = (unsigned int) val;
706 do_cmp_unsigned(regs, val, imm, rd >> 2);
716 do_cmp_signed(regs, val, imm, rd >> 2);
721 add_with_carry(regs, rd, regs->gpr[ra], imm, 0);
724 case 13: /* addic. */
726 add_with_carry(regs, rd, regs->gpr[ra], imm, 0);
733 imm += regs->gpr[ra];
738 imm = ((short) instr) << 16;
740 imm += regs->gpr[ra];
744 case 20: /* rlwimi */
745 mb = (instr >> 6) & 0x1f;
746 me = (instr >> 1) & 0x1f;
747 val = DATA32(regs->gpr[rd]);
748 imm = MASK32(mb, me);
749 regs->gpr[ra] = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
752 case 21: /* rlwinm */
753 mb = (instr >> 6) & 0x1f;
754 me = (instr >> 1) & 0x1f;
755 val = DATA32(regs->gpr[rd]);
756 regs->gpr[ra] = ROTATE(val, rb) & MASK32(mb, me);
760 mb = (instr >> 6) & 0x1f;
761 me = (instr >> 1) & 0x1f;
762 rb = regs->gpr[rb] & 0x1f;
763 val = DATA32(regs->gpr[rd]);
764 regs->gpr[ra] = ROTATE(val, rb) & MASK32(mb, me);
768 imm = (unsigned short) instr;
769 regs->gpr[ra] = regs->gpr[rd] | imm;
773 imm = (unsigned short) instr;
774 regs->gpr[ra] = regs->gpr[rd] | (imm << 16);
778 imm = (unsigned short) instr;
779 regs->gpr[ra] = regs->gpr[rd] ^ imm;
783 imm = (unsigned short) instr;
784 regs->gpr[ra] = regs->gpr[rd] ^ (imm << 16);
788 imm = (unsigned short) instr;
789 regs->gpr[ra] = regs->gpr[rd] & imm;
793 case 29: /* andis. */
794 imm = (unsigned short) instr;
795 regs->gpr[ra] = regs->gpr[rd] & (imm << 16);
801 mb = ((instr >> 6) & 0x1f) | (instr & 0x20);
803 if ((instr & 0x10) == 0) {
804 sh = rb | ((instr & 2) << 4);
805 val = ROTATE(val, sh);
806 switch ((instr >> 2) & 3) {
808 regs->gpr[ra] = val & MASK64_L(mb);
811 regs->gpr[ra] = val & MASK64_R(mb);
814 regs->gpr[ra] = val & MASK64(mb, 63 - sh);
817 imm = MASK64(mb, 63 - sh);
818 regs->gpr[ra] = (regs->gpr[ra] & ~imm) |
823 sh = regs->gpr[rb] & 0x3f;
824 val = ROTATE(val, sh);
825 switch ((instr >> 1) & 7) {
827 regs->gpr[ra] = val & MASK64_L(mb);
830 regs->gpr[ra] = val & MASK64_R(mb);
837 switch ((instr >> 1) & 0x3ff) {
839 if (regs->msr & MSR_PR)
841 regs->gpr[rd] = regs->msr & MSR_MASK;
843 case 146: /* mtmsr */
844 if (regs->msr & MSR_PR)
847 if ((imm & MSR_RI) == 0)
848 /* can't step mtmsr that would clear MSR_RI */
853 case 178: /* mtmsrd */
854 /* only MSR_EE and MSR_RI get changed if bit 15 set */
855 /* mtmsrd doesn't change MSR_HV and MSR_ME */
856 if (regs->msr & MSR_PR)
858 imm = (instr & 0x10000)? 0x8002: 0xefffffffffffefffUL;
859 imm = (regs->msr & MSR_MASK & ~imm)
860 | (regs->gpr[rd] & imm);
861 if ((imm & MSR_RI) == 0)
862 /* can't step mtmsrd that would clear MSR_RI */
868 regs->gpr[rd] = regs->ccr;
869 regs->gpr[rd] &= 0xffffffffUL;
872 case 144: /* mtcrf */
875 for (sh = 0; sh < 8; ++sh) {
876 if (instr & (0x80000 >> sh))
877 regs->ccr = (regs->ccr & ~imm) |
883 case 339: /* mfspr */
884 spr = (instr >> 11) & 0x3ff;
886 case 0x20: /* mfxer */
887 regs->gpr[rd] = regs->xer;
888 regs->gpr[rd] &= 0xffffffffUL;
890 case 0x100: /* mflr */
891 regs->gpr[rd] = regs->link;
893 case 0x120: /* mfctr */
894 regs->gpr[rd] = regs->ctr;
899 case 467: /* mtspr */
900 spr = (instr >> 11) & 0x3ff;
902 case 0x20: /* mtxer */
903 regs->xer = (regs->gpr[rd] & 0xffffffffUL);
905 case 0x100: /* mtlr */
906 regs->link = regs->gpr[rd];
908 case 0x120: /* mtctr */
909 regs->ctr = regs->gpr[rd];
915 * Compare instructions
919 val2 = regs->gpr[rb];
922 /* word (32-bit) compare */
927 do_cmp_signed(regs, val, val2, rd >> 2);
932 val2 = regs->gpr[rb];
935 /* word (32-bit) compare */
936 val = (unsigned int) val;
937 val2 = (unsigned int) val2;
940 do_cmp_unsigned(regs, val, val2, rd >> 2);
944 * Arithmetic instructions
947 add_with_carry(regs, rd, ~regs->gpr[ra],
952 asm("mulhdu %0,%1,%2" : "=r" (regs->gpr[rd]) :
953 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
957 add_with_carry(regs, rd, regs->gpr[ra],
961 case 11: /* mulhwu */
962 asm("mulhwu %0,%1,%2" : "=r" (regs->gpr[rd]) :
963 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
967 regs->gpr[rd] = regs->gpr[rb] - regs->gpr[ra];
971 asm("mulhd %0,%1,%2" : "=r" (regs->gpr[rd]) :
972 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
976 asm("mulhw %0,%1,%2" : "=r" (regs->gpr[rd]) :
977 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
981 regs->gpr[rd] = -regs->gpr[ra];
984 case 136: /* subfe */
985 add_with_carry(regs, rd, ~regs->gpr[ra], regs->gpr[rb],
990 add_with_carry(regs, rd, regs->gpr[ra], regs->gpr[rb],
994 case 200: /* subfze */
995 add_with_carry(regs, rd, ~regs->gpr[ra], 0L,
999 case 202: /* addze */
1000 add_with_carry(regs, rd, regs->gpr[ra], 0L,
1001 regs->xer & XER_CA);
1004 case 232: /* subfme */
1005 add_with_carry(regs, rd, ~regs->gpr[ra], -1L,
1006 regs->xer & XER_CA);
1008 #ifdef __powerpc64__
1009 case 233: /* mulld */
1010 regs->gpr[rd] = regs->gpr[ra] * regs->gpr[rb];
1013 case 234: /* addme */
1014 add_with_carry(regs, rd, regs->gpr[ra], -1L,
1015 regs->xer & XER_CA);
1018 case 235: /* mullw */
1019 regs->gpr[rd] = (unsigned int) regs->gpr[ra] *
1020 (unsigned int) regs->gpr[rb];
1024 regs->gpr[rd] = regs->gpr[ra] + regs->gpr[rb];
1026 #ifdef __powerpc64__
1027 case 457: /* divdu */
1028 regs->gpr[rd] = regs->gpr[ra] / regs->gpr[rb];
1031 case 459: /* divwu */
1032 regs->gpr[rd] = (unsigned int) regs->gpr[ra] /
1033 (unsigned int) regs->gpr[rb];
1035 #ifdef __powerpc64__
1036 case 489: /* divd */
1037 regs->gpr[rd] = (long int) regs->gpr[ra] /
1038 (long int) regs->gpr[rb];
1041 case 491: /* divw */
1042 regs->gpr[rd] = (int) regs->gpr[ra] /
1043 (int) regs->gpr[rb];
1048 * Logical instructions
1050 case 26: /* cntlzw */
1051 asm("cntlzw %0,%1" : "=r" (regs->gpr[ra]) :
1052 "r" (regs->gpr[rd]));
1054 #ifdef __powerpc64__
1055 case 58: /* cntlzd */
1056 asm("cntlzd %0,%1" : "=r" (regs->gpr[ra]) :
1057 "r" (regs->gpr[rd]));
1061 regs->gpr[ra] = regs->gpr[rd] & regs->gpr[rb];
1065 regs->gpr[ra] = regs->gpr[rd] & ~regs->gpr[rb];
1069 regs->gpr[ra] = ~(regs->gpr[rd] | regs->gpr[rb]);
1073 regs->gpr[ra] = ~(regs->gpr[rd] ^ regs->gpr[rb]);
1077 regs->gpr[ra] = regs->gpr[rd] ^ regs->gpr[rb];
1081 regs->gpr[ra] = regs->gpr[rd] | ~regs->gpr[rb];
1085 regs->gpr[ra] = regs->gpr[rd] | regs->gpr[rb];
1088 case 476: /* nand */
1089 regs->gpr[ra] = ~(regs->gpr[rd] & regs->gpr[rb]);
1092 case 922: /* extsh */
1093 regs->gpr[ra] = (signed short) regs->gpr[rd];
1096 case 954: /* extsb */
1097 regs->gpr[ra] = (signed char) regs->gpr[rd];
1099 #ifdef __powerpc64__
1100 case 986: /* extsw */
1101 regs->gpr[ra] = (signed int) regs->gpr[rd];
1106 * Shift instructions
1109 sh = regs->gpr[rb] & 0x3f;
1111 regs->gpr[ra] = (regs->gpr[rd] << sh) & 0xffffffffUL;
1117 sh = regs->gpr[rb] & 0x3f;
1119 regs->gpr[ra] = (regs->gpr[rd] & 0xffffffffUL) >> sh;
1124 case 792: /* sraw */
1125 sh = regs->gpr[rb] & 0x3f;
1126 ival = (signed int) regs->gpr[rd];
1127 regs->gpr[ra] = ival >> (sh < 32 ? sh : 31);
1128 if (ival < 0 && (sh >= 32 || (ival & ((1 << sh) - 1)) != 0))
1129 regs->xer |= XER_CA;
1131 regs->xer &= ~XER_CA;
1134 case 824: /* srawi */
1136 ival = (signed int) regs->gpr[rd];
1137 regs->gpr[ra] = ival >> sh;
1138 if (ival < 0 && (ival & ((1 << sh) - 1)) != 0)
1139 regs->xer |= XER_CA;
1141 regs->xer &= ~XER_CA;
1144 #ifdef __powerpc64__
1146 sh = regs->gpr[rd] & 0x7f;
1148 regs->gpr[ra] = regs->gpr[rd] << sh;
1154 sh = regs->gpr[rb] & 0x7f;
1156 regs->gpr[ra] = regs->gpr[rd] >> sh;
1161 case 794: /* srad */
1162 sh = regs->gpr[rb] & 0x7f;
1163 ival = (signed long int) regs->gpr[rd];
1164 regs->gpr[ra] = ival >> (sh < 64 ? sh : 63);
1165 if (ival < 0 && (sh >= 64 || (ival & ((1 << sh) - 1)) != 0))
1166 regs->xer |= XER_CA;
1168 regs->xer &= ~XER_CA;
1171 case 826: /* sradi with sh_5 = 0 */
1172 case 827: /* sradi with sh_5 = 1 */
1173 sh = rb | ((instr & 2) << 4);
1174 ival = (signed long int) regs->gpr[rd];
1175 regs->gpr[ra] = ival >> sh;
1176 if (ival < 0 && (ival & ((1 << sh) - 1)) != 0)
1177 regs->xer |= XER_CA;
1179 regs->xer &= ~XER_CA;
1181 #endif /* __powerpc64__ */
1184 * Cache instructions
1186 case 54: /* dcbst */
1187 ea = xform_ea(instr, regs, 0);
1188 if (!address_ok(regs, ea, 8))
1191 __cacheop_user_asmx(ea, err, "dcbst");
1197 ea = xform_ea(instr, regs, 0);
1198 if (!address_ok(regs, ea, 8))
1201 __cacheop_user_asmx(ea, err, "dcbf");
1206 case 246: /* dcbtst */
1208 ea = xform_ea(instr, regs, 0);
1209 prefetchw((void *) ea);
1213 case 278: /* dcbt */
1215 ea = xform_ea(instr, regs, 0);
1216 prefetch((void *) ea);
1225 * Following cases are for loads and stores, so bail out
1226 * if we're in little-endian mode.
1228 if (regs->msr & MSR_LE)
1232 * Save register RA in case it's an update form load or store
1233 * and the access faults.
1235 old_ra = regs->gpr[ra];
1240 switch ((instr >> 1) & 0x3ff) {
1241 case 20: /* lwarx */
1242 ea = xform_ea(instr, regs, 0);
1244 break; /* can't handle misaligned */
1246 if (!address_ok(regs, ea, 4))
1249 __get_user_asmx(val, ea, err, "lwarx");
1251 regs->gpr[rd] = val;
1254 case 150: /* stwcx. */
1255 ea = xform_ea(instr, regs, 0);
1257 break; /* can't handle misaligned */
1259 if (!address_ok(regs, ea, 4))
1262 __put_user_asmx(regs->gpr[rd], ea, err, "stwcx.", cr);
1264 regs->ccr = (regs->ccr & 0x0fffffff) |
1266 ((regs->xer >> 3) & 0x10000000);
1269 #ifdef __powerpc64__
1270 case 84: /* ldarx */
1271 ea = xform_ea(instr, regs, 0);
1273 break; /* can't handle misaligned */
1275 if (!address_ok(regs, ea, 8))
1278 __get_user_asmx(val, ea, err, "ldarx");
1280 regs->gpr[rd] = val;
1283 case 214: /* stdcx. */
1284 ea = xform_ea(instr, regs, 0);
1286 break; /* can't handle misaligned */
1288 if (!address_ok(regs, ea, 8))
1291 __put_user_asmx(regs->gpr[rd], ea, err, "stdcx.", cr);
1293 regs->ccr = (regs->ccr & 0x0fffffff) |
1295 ((regs->xer >> 3) & 0x10000000);
1300 err = read_mem(®s->gpr[rd], xform_ea(instr, regs, u),
1306 case 55: /* lwzux */
1307 err = read_mem(®s->gpr[rd], xform_ea(instr, regs, u),
1312 case 119: /* lbzux */
1313 err = read_mem(®s->gpr[rd], xform_ea(instr, regs, u),
1317 #ifdef CONFIG_ALTIVEC
1319 case 359: /* lvxl */
1320 if (!(regs->msr & MSR_VEC))
1322 ea = xform_ea(instr, regs, 0);
1323 err = do_vec_load(rd, do_lvx, ea, regs);
1326 case 231: /* stvx */
1327 case 487: /* stvxl */
1328 if (!(regs->msr & MSR_VEC))
1330 ea = xform_ea(instr, regs, 0);
1331 err = do_vec_store(rd, do_stvx, ea, regs);
1333 #endif /* CONFIG_ALTIVEC */
1335 #ifdef __powerpc64__
1336 case 149: /* stdx */
1337 case 181: /* stdux */
1338 val = regs->gpr[rd];
1339 err = write_mem(val, xform_ea(instr, regs, u), 8, regs);
1343 case 151: /* stwx */
1344 case 183: /* stwux */
1345 val = regs->gpr[rd];
1346 err = write_mem(val, xform_ea(instr, regs, u), 4, regs);
1349 case 215: /* stbx */
1350 case 247: /* stbux */
1351 val = regs->gpr[rd];
1352 err = write_mem(val, xform_ea(instr, regs, u), 1, regs);
1355 case 279: /* lhzx */
1356 case 311: /* lhzux */
1357 err = read_mem(®s->gpr[rd], xform_ea(instr, regs, u),
1361 #ifdef __powerpc64__
1362 case 341: /* lwax */
1363 case 373: /* lwaux */
1364 err = read_mem(®s->gpr[rd], xform_ea(instr, regs, u),
1367 regs->gpr[rd] = (signed int) regs->gpr[rd];
1371 case 343: /* lhax */
1372 case 375: /* lhaux */
1373 err = read_mem(®s->gpr[rd], xform_ea(instr, regs, u),
1376 regs->gpr[rd] = (signed short) regs->gpr[rd];
1379 case 407: /* sthx */
1380 case 439: /* sthux */
1381 val = regs->gpr[rd];
1382 err = write_mem(val, xform_ea(instr, regs, u), 2, regs);
1385 #ifdef __powerpc64__
1386 case 532: /* ldbrx */
1387 err = read_mem(&val, xform_ea(instr, regs, 0), 8, regs);
1389 regs->gpr[rd] = byterev_8(val);
1394 case 534: /* lwbrx */
1395 err = read_mem(&val, xform_ea(instr, regs, 0), 4, regs);
1397 regs->gpr[rd] = byterev_4(val);
1400 #ifdef CONFIG_PPC_CPU
1401 case 535: /* lfsx */
1402 case 567: /* lfsux */
1403 if (!(regs->msr & MSR_FP))
1405 ea = xform_ea(instr, regs, u);
1406 err = do_fp_load(rd, do_lfs, ea, 4, regs);
1409 case 599: /* lfdx */
1410 case 631: /* lfdux */
1411 if (!(regs->msr & MSR_FP))
1413 ea = xform_ea(instr, regs, u);
1414 err = do_fp_load(rd, do_lfd, ea, 8, regs);
1417 case 663: /* stfsx */
1418 case 695: /* stfsux */
1419 if (!(regs->msr & MSR_FP))
1421 ea = xform_ea(instr, regs, u);
1422 err = do_fp_store(rd, do_stfs, ea, 4, regs);
1425 case 727: /* stfdx */
1426 case 759: /* stfdux */
1427 if (!(regs->msr & MSR_FP))
1429 ea = xform_ea(instr, regs, u);
1430 err = do_fp_store(rd, do_stfd, ea, 8, regs);
1434 #ifdef __powerpc64__
1435 case 660: /* stdbrx */
1436 val = byterev_8(regs->gpr[rd]);
1437 err = write_mem(val, xform_ea(instr, regs, 0), 8, regs);
1441 case 662: /* stwbrx */
1442 val = byterev_4(regs->gpr[rd]);
1443 err = write_mem(val, xform_ea(instr, regs, 0), 4, regs);
1446 case 790: /* lhbrx */
1447 err = read_mem(&val, xform_ea(instr, regs, 0), 2, regs);
1449 regs->gpr[rd] = byterev_2(val);
1452 case 918: /* sthbrx */
1453 val = byterev_2(regs->gpr[rd]);
1454 err = write_mem(val, xform_ea(instr, regs, 0), 2, regs);
1458 case 844: /* lxvd2x */
1459 case 876: /* lxvd2ux */
1460 if (!(regs->msr & MSR_VSX))
1462 rd |= (instr & 1) << 5;
1463 ea = xform_ea(instr, regs, u);
1464 err = do_vsx_load(rd, do_lxvd2x, ea, regs);
1467 case 972: /* stxvd2x */
1468 case 1004: /* stxvd2ux */
1469 if (!(regs->msr & MSR_VSX))
1471 rd |= (instr & 1) << 5;
1472 ea = xform_ea(instr, regs, u);
1473 err = do_vsx_store(rd, do_stxvd2x, ea, regs);
1476 #endif /* CONFIG_VSX */
1482 err = read_mem(®s->gpr[rd], dform_ea(instr, regs), 4, regs);
1487 err = read_mem(®s->gpr[rd], dform_ea(instr, regs), 1, regs);
1492 val = regs->gpr[rd];
1493 err = write_mem(val, dform_ea(instr, regs), 4, regs);
1498 val = regs->gpr[rd];
1499 err = write_mem(val, dform_ea(instr, regs), 1, regs);
1504 err = read_mem(®s->gpr[rd], dform_ea(instr, regs), 2, regs);
1509 err = read_mem(®s->gpr[rd], dform_ea(instr, regs), 2, regs);
1511 regs->gpr[rd] = (signed short) regs->gpr[rd];
1516 val = regs->gpr[rd];
1517 err = write_mem(val, dform_ea(instr, regs), 2, regs);
1521 ra = (instr >> 16) & 0x1f;
1523 break; /* invalid form, ra in range to load */
1524 ea = dform_ea(instr, regs);
1526 err = read_mem(®s->gpr[rd], ea, 4, regs);
1530 } while (++rd < 32);
1534 ea = dform_ea(instr, regs);
1536 err = write_mem(regs->gpr[rd], ea, 4, regs);
1540 } while (++rd < 32);
1543 #ifdef CONFIG_PPC_FPU
1546 if (!(regs->msr & MSR_FP))
1548 ea = dform_ea(instr, regs);
1549 err = do_fp_load(rd, do_lfs, ea, 4, regs);
1554 if (!(regs->msr & MSR_FP))
1556 ea = dform_ea(instr, regs);
1557 err = do_fp_load(rd, do_lfd, ea, 8, regs);
1561 case 53: /* stfsu */
1562 if (!(regs->msr & MSR_FP))
1564 ea = dform_ea(instr, regs);
1565 err = do_fp_store(rd, do_stfs, ea, 4, regs);
1569 case 55: /* stfdu */
1570 if (!(regs->msr & MSR_FP))
1572 ea = dform_ea(instr, regs);
1573 err = do_fp_store(rd, do_stfd, ea, 8, regs);
1577 #ifdef __powerpc64__
1578 case 58: /* ld[u], lwa */
1579 switch (instr & 3) {
1581 err = read_mem(®s->gpr[rd], dsform_ea(instr, regs),
1585 err = read_mem(®s->gpr[rd], dsform_ea(instr, regs),
1589 err = read_mem(®s->gpr[rd], dsform_ea(instr, regs),
1592 regs->gpr[rd] = (signed int) regs->gpr[rd];
1597 case 62: /* std[u] */
1598 val = regs->gpr[rd];
1599 switch (instr & 3) {
1601 err = write_mem(val, dsform_ea(instr, regs), 8, regs);
1604 err = write_mem(val, dsform_ea(instr, regs), 8, regs);
1608 #endif /* __powerpc64__ */
1615 regs->gpr[ra] = old_ra;
1616 return 0; /* invoke DSI if -EFAULT? */
1620 #ifdef __powerpc64__
1621 if ((regs->msr & MSR_SF) == 0)
1622 regs->nip &= 0xffffffffUL;