2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/export.h>
31 #include <linux/ctype.h>
32 #include <linux/cache.h>
33 #include <linux/init.h>
34 #include <linux/signal.h>
35 #include <linux/memblock.h>
36 #include <linux/context_tracking.h>
38 #include <asm/processor.h>
39 #include <asm/pgtable.h>
41 #include <asm/mmu_context.h>
43 #include <asm/types.h>
44 #include <asm/uaccess.h>
45 #include <asm/machdep.h>
47 #include <asm/tlbflush.h>
51 #include <asm/cacheflush.h>
52 #include <asm/cputable.h>
53 #include <asm/sections.h>
54 #include <asm/copro.h>
56 #include <asm/code-patching.h>
57 #include <asm/fadump.h>
58 #include <asm/firmware.h>
60 #include <asm/trace.h>
63 #define DBG(fmt...) udbg_printf(fmt)
69 #define DBG_LOW(fmt...) udbg_printf(fmt)
71 #define DBG_LOW(fmt...)
79 * Note: pte --> Linux PTE
80 * HPTE --> PowerPC Hashed Page Table Entry
83 * htab_initialize is called with the MMU off (of course), but
84 * the kernel has been copied down to zero so it can directly
85 * reference global data. At this point it is very difficult
86 * to print debug info.
91 extern unsigned long dart_tablebase;
92 #endif /* CONFIG_U3_DART */
94 static unsigned long _SDR1;
95 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
96 EXPORT_SYMBOL_GPL(mmu_psize_defs);
98 struct hash_pte *htab_address;
99 unsigned long htab_size_bytes;
100 unsigned long htab_hash_mask;
101 EXPORT_SYMBOL_GPL(htab_hash_mask);
102 int mmu_linear_psize = MMU_PAGE_4K;
103 EXPORT_SYMBOL_GPL(mmu_linear_psize);
104 int mmu_virtual_psize = MMU_PAGE_4K;
105 int mmu_vmalloc_psize = MMU_PAGE_4K;
106 #ifdef CONFIG_SPARSEMEM_VMEMMAP
107 int mmu_vmemmap_psize = MMU_PAGE_4K;
109 int mmu_io_psize = MMU_PAGE_4K;
110 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
111 EXPORT_SYMBOL_GPL(mmu_kernel_ssize);
112 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
113 u16 mmu_slb_size = 64;
114 EXPORT_SYMBOL_GPL(mmu_slb_size);
115 #ifdef CONFIG_PPC_64K_PAGES
116 int mmu_ci_restrictions;
118 #ifdef CONFIG_DEBUG_PAGEALLOC
119 static u8 *linear_map_hash_slots;
120 static unsigned long linear_map_hash_count;
121 static DEFINE_SPINLOCK(linear_map_hash_lock);
122 #endif /* CONFIG_DEBUG_PAGEALLOC */
124 /* There are definitions of page sizes arrays to be used when none
125 * is provided by the firmware.
128 /* Pre-POWER4 CPUs (4k pages only)
130 static struct mmu_psize_def mmu_psize_defaults_old[] = {
134 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
140 /* POWER4, GPUL, POWER5
142 * Support for 16Mb large pages
144 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
148 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
155 .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
156 [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
162 unsigned long htab_convert_pte_flags(unsigned long pteflags)
164 unsigned long rflags = 0;
166 /* _PAGE_EXEC -> NOEXEC */
167 if ((pteflags & _PAGE_EXEC) == 0)
171 * Linux use slb key 0 for kernel and 1 for user.
172 * kernel areas are mapped by PP bits 00
173 * and and there is no kernel RO (_PAGE_KERNEL_RO).
174 * User area mapped by 0x2 and read only use by
177 if (pteflags & _PAGE_USER) {
179 if (!((pteflags & _PAGE_RW) && (pteflags & _PAGE_DIRTY)))
183 * Always add "C" bit for perf. Memory coherence is always enabled
185 rflags |= HPTE_R_C | HPTE_R_M;
189 if (pteflags & _PAGE_WRITETHRU)
191 if (pteflags & _PAGE_NO_CACHE)
193 if (pteflags & _PAGE_GUARDED)
199 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
200 unsigned long pstart, unsigned long prot,
201 int psize, int ssize)
203 unsigned long vaddr, paddr;
204 unsigned int step, shift;
207 shift = mmu_psize_defs[psize].shift;
210 prot = htab_convert_pte_flags(prot);
212 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
213 vstart, vend, pstart, prot, psize, ssize);
215 for (vaddr = vstart, paddr = pstart; vaddr < vend;
216 vaddr += step, paddr += step) {
217 unsigned long hash, hpteg;
218 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
219 unsigned long vpn = hpt_vpn(vaddr, vsid, ssize);
220 unsigned long tprot = prot;
223 * If we hit a bad address return error.
227 /* Make kernel text executable */
228 if (overlaps_kernel_text(vaddr, vaddr + step))
231 /* Make kvm guest trampolines executable */
232 if (overlaps_kvm_tmp(vaddr, vaddr + step))
236 * If relocatable, check if it overlaps interrupt vectors that
237 * are copied down to real 0. For relocatable kernel
238 * (e.g. kdump case) we copy interrupt vectors down to real
239 * address 0. Mark that region as executable. This is
240 * because on p8 system with relocation on exception feature
241 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
242 * in order to execute the interrupt handlers in virtual
243 * mode the vector region need to be marked as executable.
245 if ((PHYSICAL_START > MEMORY_START) &&
246 overlaps_interrupt_vector_text(vaddr, vaddr + step))
249 hash = hpt_hash(vpn, shift, ssize);
250 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
252 BUG_ON(!ppc_md.hpte_insert);
253 ret = ppc_md.hpte_insert(hpteg, vpn, paddr, tprot,
254 HPTE_V_BOLTED, psize, psize, ssize);
258 #ifdef CONFIG_DEBUG_PAGEALLOC
259 if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
260 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
261 #endif /* CONFIG_DEBUG_PAGEALLOC */
263 return ret < 0 ? ret : 0;
266 #ifdef CONFIG_MEMORY_HOTPLUG
267 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
268 int psize, int ssize)
271 unsigned int step, shift;
273 shift = mmu_psize_defs[psize].shift;
276 if (!ppc_md.hpte_removebolted) {
277 printk(KERN_WARNING "Platform doesn't implement "
278 "hpte_removebolted\n");
282 for (vaddr = vstart; vaddr < vend; vaddr += step)
283 ppc_md.hpte_removebolted(vaddr, psize, ssize);
287 #endif /* CONFIG_MEMORY_HOTPLUG */
289 static int __init htab_dt_scan_seg_sizes(unsigned long node,
290 const char *uname, int depth,
293 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
297 /* We are scanning "cpu" nodes only */
298 if (type == NULL || strcmp(type, "cpu") != 0)
301 prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
304 for (; size >= 4; size -= 4, ++prop) {
305 if (be32_to_cpu(prop[0]) == 40) {
306 DBG("1T segment support detected\n");
307 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
311 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
315 static void __init htab_init_seg_sizes(void)
317 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
320 static int __init get_idx_from_shift(unsigned int shift)
344 static int __init htab_dt_scan_page_sizes(unsigned long node,
345 const char *uname, int depth,
348 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
352 /* We are scanning "cpu" nodes only */
353 if (type == NULL || strcmp(type, "cpu") != 0)
356 prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
360 pr_info("Page sizes from device-tree:\n");
362 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
364 unsigned int base_shift = be32_to_cpu(prop[0]);
365 unsigned int slbenc = be32_to_cpu(prop[1]);
366 unsigned int lpnum = be32_to_cpu(prop[2]);
367 struct mmu_psize_def *def;
370 size -= 3; prop += 3;
371 base_idx = get_idx_from_shift(base_shift);
373 /* skip the pte encoding also */
374 prop += lpnum * 2; size -= lpnum * 2;
377 def = &mmu_psize_defs[base_idx];
378 if (base_idx == MMU_PAGE_16M)
379 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
381 def->shift = base_shift;
382 if (base_shift <= 23)
385 def->avpnm = (1 << (base_shift - 23)) - 1;
388 * We don't know for sure what's up with tlbiel, so
389 * for now we only set it for 4K and 64K pages
391 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
396 while (size > 0 && lpnum) {
397 unsigned int shift = be32_to_cpu(prop[0]);
398 int penc = be32_to_cpu(prop[1]);
400 prop += 2; size -= 2;
403 idx = get_idx_from_shift(shift);
408 pr_err("Invalid penc for base_shift=%d "
409 "shift=%d\n", base_shift, shift);
411 def->penc[idx] = penc;
412 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
413 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
414 base_shift, shift, def->sllp,
415 def->avpnm, def->tlbiel, def->penc[idx]);
422 #ifdef CONFIG_HUGETLB_PAGE
423 /* Scan for 16G memory blocks that have been set aside for huge pages
424 * and reserve those blocks for 16G huge pages.
426 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
427 const char *uname, int depth,
429 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
430 const __be64 *addr_prop;
431 const __be32 *page_count_prop;
432 unsigned int expected_pages;
433 long unsigned int phys_addr;
434 long unsigned int block_size;
436 /* We are scanning "memory" nodes only */
437 if (type == NULL || strcmp(type, "memory") != 0)
440 /* This property is the log base 2 of the number of virtual pages that
441 * will represent this memory block. */
442 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
443 if (page_count_prop == NULL)
445 expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
446 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
447 if (addr_prop == NULL)
449 phys_addr = be64_to_cpu(addr_prop[0]);
450 block_size = be64_to_cpu(addr_prop[1]);
451 if (block_size != (16 * GB))
453 printk(KERN_INFO "Huge page(16GB) memory: "
454 "addr = 0x%lX size = 0x%lX pages = %d\n",
455 phys_addr, block_size, expected_pages);
456 if (phys_addr + (16 * GB) <= memblock_end_of_DRAM()) {
457 memblock_reserve(phys_addr, block_size * expected_pages);
458 add_gpage(phys_addr, block_size, expected_pages);
462 #endif /* CONFIG_HUGETLB_PAGE */
464 static void mmu_psize_set_default_penc(void)
467 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
468 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
469 mmu_psize_defs[bpsize].penc[apsize] = -1;
472 #ifdef CONFIG_PPC_64K_PAGES
474 static bool might_have_hea(void)
477 * The HEA ethernet adapter requires awareness of the
478 * GX bus. Without that awareness we can easily assume
479 * we will never see an HEA ethernet device.
481 #ifdef CONFIG_IBMEBUS
482 return !cpu_has_feature(CPU_FTR_ARCH_207S);
488 #endif /* #ifdef CONFIG_PPC_64K_PAGES */
490 static void __init htab_init_page_sizes(void)
494 /* se the invalid penc to -1 */
495 mmu_psize_set_default_penc();
497 /* Default to 4K pages only */
498 memcpy(mmu_psize_defs, mmu_psize_defaults_old,
499 sizeof(mmu_psize_defaults_old));
502 * Try to find the available page sizes in the device-tree
504 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
505 if (rc != 0) /* Found */
509 * Not in the device-tree, let's fallback on known size
510 * list for 16M capable GP & GR
512 if (mmu_has_feature(MMU_FTR_16M_PAGE))
513 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
514 sizeof(mmu_psize_defaults_gp));
516 #ifndef CONFIG_DEBUG_PAGEALLOC
518 * Pick a size for the linear mapping. Currently, we only support
519 * 16M, 1M and 4K which is the default
521 if (mmu_psize_defs[MMU_PAGE_16M].shift)
522 mmu_linear_psize = MMU_PAGE_16M;
523 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
524 mmu_linear_psize = MMU_PAGE_1M;
525 #endif /* CONFIG_DEBUG_PAGEALLOC */
527 #ifdef CONFIG_PPC_64K_PAGES
529 * Pick a size for the ordinary pages. Default is 4K, we support
530 * 64K for user mappings and vmalloc if supported by the processor.
531 * We only use 64k for ioremap if the processor
532 * (and firmware) support cache-inhibited large pages.
533 * If not, we use 4k and set mmu_ci_restrictions so that
534 * hash_page knows to switch processes that use cache-inhibited
535 * mappings to 4k pages.
537 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
538 mmu_virtual_psize = MMU_PAGE_64K;
539 mmu_vmalloc_psize = MMU_PAGE_64K;
540 if (mmu_linear_psize == MMU_PAGE_4K)
541 mmu_linear_psize = MMU_PAGE_64K;
542 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
544 * When running on pSeries using 64k pages for ioremap
545 * would stop us accessing the HEA ethernet. So if we
546 * have the chance of ever seeing one, stay at 4k.
548 if (!might_have_hea() || !machine_is(pseries))
549 mmu_io_psize = MMU_PAGE_64K;
551 mmu_ci_restrictions = 1;
553 #endif /* CONFIG_PPC_64K_PAGES */
555 #ifdef CONFIG_SPARSEMEM_VMEMMAP
556 /* We try to use 16M pages for vmemmap if that is supported
557 * and we have at least 1G of RAM at boot
559 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
560 memblock_phys_mem_size() >= 0x40000000)
561 mmu_vmemmap_psize = MMU_PAGE_16M;
562 else if (mmu_psize_defs[MMU_PAGE_64K].shift)
563 mmu_vmemmap_psize = MMU_PAGE_64K;
565 mmu_vmemmap_psize = MMU_PAGE_4K;
566 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
568 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
569 "virtual = %d, io = %d"
570 #ifdef CONFIG_SPARSEMEM_VMEMMAP
574 mmu_psize_defs[mmu_linear_psize].shift,
575 mmu_psize_defs[mmu_virtual_psize].shift,
576 mmu_psize_defs[mmu_io_psize].shift
577 #ifdef CONFIG_SPARSEMEM_VMEMMAP
578 ,mmu_psize_defs[mmu_vmemmap_psize].shift
582 #ifdef CONFIG_HUGETLB_PAGE
583 /* Reserve 16G huge page memory sections for huge pages */
584 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
585 #endif /* CONFIG_HUGETLB_PAGE */
588 static int __init htab_dt_scan_pftsize(unsigned long node,
589 const char *uname, int depth,
592 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
595 /* We are scanning "cpu" nodes only */
596 if (type == NULL || strcmp(type, "cpu") != 0)
599 prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
601 /* pft_size[0] is the NUMA CEC cookie */
602 ppc64_pft_size = be32_to_cpu(prop[1]);
608 static unsigned long __init htab_get_table_size(void)
610 unsigned long mem_size, rnd_mem_size, pteg_count, psize;
612 /* If hash size isn't already provided by the platform, we try to
613 * retrieve it from the device-tree. If it's not there neither, we
614 * calculate it now based on the total RAM size
616 if (ppc64_pft_size == 0)
617 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
619 return 1UL << ppc64_pft_size;
621 /* round mem_size up to next power of 2 */
622 mem_size = memblock_phys_mem_size();
623 rnd_mem_size = 1UL << __ilog2(mem_size);
624 if (rnd_mem_size < mem_size)
628 psize = mmu_psize_defs[mmu_virtual_psize].shift;
629 pteg_count = max(rnd_mem_size >> (psize + 1), 1UL << 11);
631 return pteg_count << 7;
634 #ifdef CONFIG_MEMORY_HOTPLUG
635 int create_section_mapping(unsigned long start, unsigned long end)
637 return htab_bolt_mapping(start, end, __pa(start),
638 pgprot_val(PAGE_KERNEL), mmu_linear_psize,
642 int remove_section_mapping(unsigned long start, unsigned long end)
644 return htab_remove_mapping(start, end, mmu_linear_psize,
647 #endif /* CONFIG_MEMORY_HOTPLUG */
649 static void __init htab_initialize(void)
652 unsigned long pteg_count;
654 unsigned long base = 0, size = 0, limit;
655 struct memblock_region *reg;
657 DBG(" -> htab_initialize()\n");
659 /* Initialize segment sizes */
660 htab_init_seg_sizes();
662 /* Initialize page sizes */
663 htab_init_page_sizes();
665 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
666 mmu_kernel_ssize = MMU_SEGSIZE_1T;
667 mmu_highuser_ssize = MMU_SEGSIZE_1T;
668 printk(KERN_INFO "Using 1TB segments\n");
672 * Calculate the required size of the htab. We want the number of
673 * PTEGs to equal one half the number of real pages.
675 htab_size_bytes = htab_get_table_size();
676 pteg_count = htab_size_bytes >> 7;
678 htab_hash_mask = pteg_count - 1;
680 if (firmware_has_feature(FW_FEATURE_LPAR)) {
681 /* Using a hypervisor which owns the htab */
684 #ifdef CONFIG_FA_DUMP
686 * If firmware assisted dump is active firmware preserves
687 * the contents of htab along with entire partition memory.
688 * Clear the htab if firmware assisted dump is active so
689 * that we dont end up using old mappings.
691 if (is_fadump_active() && ppc_md.hpte_clear_all)
692 ppc_md.hpte_clear_all();
695 /* Find storage for the HPT. Must be contiguous in
696 * the absolute address space. On cell we want it to be
697 * in the first 2 Gig so we can use it for IOMMU hacks.
699 if (machine_is(cell))
702 limit = MEMBLOCK_ALLOC_ANYWHERE;
704 table = memblock_alloc_base(htab_size_bytes, htab_size_bytes, limit);
706 DBG("Hash table allocated at %lx, size: %lx\n", table,
709 htab_address = __va(table);
711 /* htab absolute addr + encoded htabsize */
712 _SDR1 = table + __ilog2(pteg_count) - 11;
714 /* Initialize the HPT with no entries */
715 memset((void *)table, 0, htab_size_bytes);
718 mtspr(SPRN_SDR1, _SDR1);
721 prot = pgprot_val(PAGE_KERNEL);
723 #ifdef CONFIG_DEBUG_PAGEALLOC
724 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
725 linear_map_hash_slots = __va(memblock_alloc_base(linear_map_hash_count,
727 memset(linear_map_hash_slots, 0, linear_map_hash_count);
728 #endif /* CONFIG_DEBUG_PAGEALLOC */
730 /* On U3 based machines, we need to reserve the DART area and
731 * _NOT_ map it to avoid cache paradoxes as it's remapped non
735 /* create bolted the linear mapping in the hash table */
736 for_each_memblock(memory, reg) {
737 base = (unsigned long)__va(reg->base);
740 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
743 #ifdef CONFIG_U3_DART
744 /* Do not map the DART space. Fortunately, it will be aligned
745 * in such a way that it will not cross two memblock regions and
746 * will fit within a single 16Mb page.
747 * The DART space is assumed to be a full 16Mb region even if
748 * we only use 2Mb of that space. We will use more of it later
749 * for AGP GART. We have to use a full 16Mb large page.
751 DBG("DART base: %lx\n", dart_tablebase);
753 if (dart_tablebase != 0 && dart_tablebase >= base
754 && dart_tablebase < (base + size)) {
755 unsigned long dart_table_end = dart_tablebase + 16 * MB;
756 if (base != dart_tablebase)
757 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
761 if ((base + size) > dart_table_end)
762 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
764 __pa(dart_table_end),
770 #endif /* CONFIG_U3_DART */
771 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
772 prot, mmu_linear_psize, mmu_kernel_ssize));
774 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
777 * If we have a memory_limit and we've allocated TCEs then we need to
778 * explicitly map the TCE area at the top of RAM. We also cope with the
779 * case that the TCEs start below memory_limit.
780 * tce_alloc_start/end are 16MB aligned so the mapping should work
781 * for either 4K or 16MB pages.
783 if (tce_alloc_start) {
784 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
785 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
787 if (base + size >= tce_alloc_start)
788 tce_alloc_start = base + size + 1;
790 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
791 __pa(tce_alloc_start), prot,
792 mmu_linear_psize, mmu_kernel_ssize));
796 DBG(" <- htab_initialize()\n");
801 void __init early_init_mmu(void)
803 /* Initialize the MMU Hash table and create the linear mapping
804 * of memory. Has to be done before SLB initialization as this is
805 * currently where the page size encoding is obtained.
809 /* Initialize SLB management */
814 void early_init_mmu_secondary(void)
816 /* Initialize hash table for that CPU */
817 if (!firmware_has_feature(FW_FEATURE_LPAR))
818 mtspr(SPRN_SDR1, _SDR1);
823 #endif /* CONFIG_SMP */
826 * Called by asm hashtable.S for doing lazy icache flush
828 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
832 if (!pfn_valid(pte_pfn(pte)))
835 page = pte_page(pte);
838 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
840 flush_dcache_icache_page(page);
841 set_bit(PG_arch_1, &page->flags);
848 #ifdef CONFIG_PPC_MM_SLICES
849 static unsigned int get_paca_psize(unsigned long addr)
852 unsigned char *hpsizes;
853 unsigned long index, mask_index;
855 if (addr < SLICE_LOW_TOP) {
856 lpsizes = get_paca()->context.low_slices_psize;
857 index = GET_LOW_SLICE_INDEX(addr);
858 return (lpsizes >> (index * 4)) & 0xF;
860 hpsizes = get_paca()->context.high_slices_psize;
861 index = GET_HIGH_SLICE_INDEX(addr);
862 mask_index = index & 0x1;
863 return (hpsizes[index >> 1] >> (mask_index * 4)) & 0xF;
867 unsigned int get_paca_psize(unsigned long addr)
869 return get_paca()->context.user_psize;
874 * Demote a segment to using 4k pages.
875 * For now this makes the whole process use 4k pages.
877 #ifdef CONFIG_PPC_64K_PAGES
878 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
880 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
882 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
883 copro_flush_all_slbs(mm);
884 if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) {
886 copy_mm_to_paca(&mm->context);
887 slb_flush_and_rebolt();
890 #endif /* CONFIG_PPC_64K_PAGES */
892 #ifdef CONFIG_PPC_SUBPAGE_PROT
894 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
895 * Userspace sets the subpage permissions using the subpage_prot system call.
897 * Result is 0: full permissions, _PAGE_RW: read-only,
898 * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
900 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
902 struct subpage_prot_table *spt = &mm->context.spt;
906 if (ea >= spt->maxaddr)
908 if (ea < 0x100000000UL) {
909 /* addresses below 4GB use spt->low_prot */
910 sbpm = spt->low_prot;
912 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
916 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
919 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
921 /* extract 2-bit bitfield for this 4k subpage */
922 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
924 /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
925 spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0);
929 #else /* CONFIG_PPC_SUBPAGE_PROT */
930 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
936 void hash_failure_debug(unsigned long ea, unsigned long access,
937 unsigned long vsid, unsigned long trap,
938 int ssize, int psize, int lpsize, unsigned long pte)
940 if (!printk_ratelimit())
942 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
943 ea, access, current->comm);
944 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
945 trap, vsid, ssize, psize, lpsize, pte);
948 static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
949 int psize, bool user_region)
952 if (psize != get_paca_psize(ea)) {
953 copy_mm_to_paca(&mm->context);
954 slb_flush_and_rebolt();
956 } else if (get_paca()->vmalloc_sllp !=
957 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
958 get_paca()->vmalloc_sllp =
959 mmu_psize_defs[mmu_vmalloc_psize].sllp;
960 slb_vmalloc_update();
966 * 1 - normal page fault
967 * -1 - critical hash insertion error
968 * -2 - access not permitted by subpage protection mechanism
970 int hash_page_mm(struct mm_struct *mm, unsigned long ea,
971 unsigned long access, unsigned long trap,
975 enum ctx_state prev_state = exception_enter();
980 const struct cpumask *tmp;
981 int rc, user_region = 0;
984 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
986 trace_hash_fault(ea, access, trap);
988 /* Get region & vsid */
989 switch (REGION_ID(ea)) {
993 DBG_LOW(" user region with no mm !\n");
997 psize = get_slice_psize(mm, ea);
998 ssize = user_segment_size(ea);
999 vsid = get_vsid(mm->context.id, ea, ssize);
1001 case VMALLOC_REGION_ID:
1002 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1003 if (ea < VMALLOC_END)
1004 psize = mmu_vmalloc_psize;
1006 psize = mmu_io_psize;
1007 ssize = mmu_kernel_ssize;
1010 /* Not a valid range
1011 * Send the problem up to do_page_fault
1016 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1020 DBG_LOW("Bad address!\n");
1026 if (pgdir == NULL) {
1031 /* Check CPU locality */
1032 tmp = cpumask_of(smp_processor_id());
1033 if (user_region && cpumask_equal(mm_cpumask(mm), tmp))
1034 flags |= HPTE_LOCAL_UPDATE;
1036 #ifndef CONFIG_PPC_64K_PAGES
1037 /* If we use 4K pages and our psize is not 4K, then we might
1038 * be hitting a special driver mapping, and need to align the
1039 * address before we fetch the PTE.
1041 * It could also be a hugepage mapping, in which case this is
1042 * not necessary, but it's not harmful, either.
1044 if (psize != MMU_PAGE_4K)
1045 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1046 #endif /* CONFIG_PPC_64K_PAGES */
1048 /* Get PTE and page size from page tables */
1049 ptep = __find_linux_pte_or_hugepte(pgdir, ea, &is_thp, &hugeshift);
1050 if (ptep == NULL || !pte_present(*ptep)) {
1051 DBG_LOW(" no PTE !\n");
1056 /* Add _PAGE_PRESENT to the required access perm */
1057 access |= _PAGE_PRESENT;
1059 /* Pre-check access permissions (will be re-checked atomically
1060 * in __hash_page_XX but this pre-check is a fast path
1062 if (access & ~pte_val(*ptep)) {
1063 DBG_LOW(" no access !\n");
1070 rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1071 trap, flags, ssize, psize);
1072 #ifdef CONFIG_HUGETLB_PAGE
1074 rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1075 flags, ssize, hugeshift, psize);
1079 * if we have hugeshift, and is not transhuge with
1080 * hugetlb disabled, something is really wrong.
1086 if (current->mm == mm)
1087 check_paca_psize(ea, mm, psize, user_region);
1092 #ifndef CONFIG_PPC_64K_PAGES
1093 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1095 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1096 pte_val(*(ptep + PTRS_PER_PTE)));
1098 /* Do actual hashing */
1099 #ifdef CONFIG_PPC_64K_PAGES
1100 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
1101 if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1102 demote_segment_4k(mm, ea);
1103 psize = MMU_PAGE_4K;
1106 /* If this PTE is non-cacheable and we have restrictions on
1107 * using non cacheable large pages, then we switch to 4k
1109 if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
1110 (pte_val(*ptep) & _PAGE_NO_CACHE)) {
1112 demote_segment_4k(mm, ea);
1113 psize = MMU_PAGE_4K;
1114 } else if (ea < VMALLOC_END) {
1116 * some driver did a non-cacheable mapping
1117 * in vmalloc space, so switch vmalloc
1120 printk(KERN_ALERT "Reducing vmalloc segment "
1121 "to 4kB pages because of "
1122 "non-cacheable mapping\n");
1123 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1124 copro_flush_all_slbs(mm);
1128 #endif /* CONFIG_PPC_64K_PAGES */
1130 if (current->mm == mm)
1131 check_paca_psize(ea, mm, psize, user_region);
1133 #ifdef CONFIG_PPC_64K_PAGES
1134 if (psize == MMU_PAGE_64K)
1135 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1138 #endif /* CONFIG_PPC_64K_PAGES */
1140 int spp = subpage_protection(mm, ea);
1144 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1148 /* Dump some info in case of hash insertion failure, they should
1149 * never happen so it is really useful to know if/when they do
1152 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1153 psize, pte_val(*ptep));
1154 #ifndef CONFIG_PPC_64K_PAGES
1155 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1157 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1158 pte_val(*(ptep + PTRS_PER_PTE)));
1160 DBG_LOW(" -> rc=%d\n", rc);
1163 exception_exit(prev_state);
1166 EXPORT_SYMBOL_GPL(hash_page_mm);
1168 int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
1169 unsigned long dsisr)
1171 unsigned long flags = 0;
1172 struct mm_struct *mm = current->mm;
1174 if (REGION_ID(ea) == VMALLOC_REGION_ID)
1177 if (dsisr & DSISR_NOHPTE)
1178 flags |= HPTE_NOHPTE_UPDATE;
1180 return hash_page_mm(mm, ea, access, trap, flags);
1182 EXPORT_SYMBOL_GPL(hash_page);
1184 int __hash_page(unsigned long ea, unsigned long msr, unsigned long trap,
1185 unsigned long dsisr)
1187 unsigned long access = _PAGE_PRESENT;
1188 unsigned long flags = 0;
1189 struct mm_struct *mm = current->mm;
1191 if (REGION_ID(ea) == VMALLOC_REGION_ID)
1194 if (dsisr & DSISR_NOHPTE)
1195 flags |= HPTE_NOHPTE_UPDATE;
1197 if (dsisr & DSISR_ISSTORE)
1200 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
1201 * accessing a userspace segment (even from the kernel). We assume
1202 * kernel addresses always have the high bit set.
1204 if ((msr & MSR_PR) || (REGION_ID(ea) == USER_REGION_ID))
1205 access |= _PAGE_USER;
1208 access |= _PAGE_EXEC;
1210 return hash_page_mm(mm, ea, access, trap, flags);
1213 void hash_preload(struct mm_struct *mm, unsigned long ea,
1214 unsigned long access, unsigned long trap)
1220 unsigned long flags;
1221 int rc, ssize, update_flags = 0;
1223 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1225 #ifdef CONFIG_PPC_MM_SLICES
1226 /* We only prefault standard pages for now */
1227 if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
1231 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1232 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1234 /* Get Linux PTE if available */
1240 ssize = user_segment_size(ea);
1241 vsid = get_vsid(mm->context.id, ea, ssize);
1245 * Hash doesn't like irqs. Walking linux page table with irq disabled
1246 * saves us from holding multiple locks.
1248 local_irq_save(flags);
1251 * THP pages use update_mmu_cache_pmd. We don't do
1252 * hash preload there. Hence can ignore THP here
1254 ptep = find_linux_pte_or_hugepte(pgdir, ea, NULL, &hugepage_shift);
1258 WARN_ON(hugepage_shift);
1259 #ifdef CONFIG_PPC_64K_PAGES
1260 /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
1261 * a 64K kernel), then we don't preload, hash_page() will take
1262 * care of it once we actually try to access the page.
1263 * That way we don't have to duplicate all of the logic for segment
1264 * page size demotion here
1266 if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
1268 #endif /* CONFIG_PPC_64K_PAGES */
1270 /* Is that local to this CPU ? */
1271 if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1272 update_flags |= HPTE_LOCAL_UPDATE;
1275 #ifdef CONFIG_PPC_64K_PAGES
1276 if (mm->context.user_psize == MMU_PAGE_64K)
1277 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1278 update_flags, ssize);
1280 #endif /* CONFIG_PPC_64K_PAGES */
1281 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
1282 ssize, subpage_protection(mm, ea));
1284 /* Dump some info in case of hash insertion failure, they should
1285 * never happen so it is really useful to know if/when they do
1288 hash_failure_debug(ea, access, vsid, trap, ssize,
1289 mm->context.user_psize,
1290 mm->context.user_psize,
1293 local_irq_restore(flags);
1296 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1297 * do not forget to update the assembly call site !
1299 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1300 unsigned long flags)
1302 unsigned long hash, index, shift, hidx, slot;
1303 int local = flags & HPTE_LOCAL_UPDATE;
1305 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1306 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1307 hash = hpt_hash(vpn, shift, ssize);
1308 hidx = __rpte_to_hidx(pte, index);
1309 if (hidx & _PTEIDX_SECONDARY)
1311 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1312 slot += hidx & _PTEIDX_GROUP_IX;
1313 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
1315 * We use same base page size and actual psize, because we don't
1316 * use these functions for hugepage
1318 ppc_md.hpte_invalidate(slot, vpn, psize, psize, ssize, local);
1319 } pte_iterate_hashed_end();
1321 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1322 /* Transactions are not aborted by tlbiel, only tlbie.
1323 * Without, syncing a page back to a block device w/ PIO could pick up
1324 * transactional data (bad!) so we force an abort here. Before the
1325 * sync the page will be made read-only, which will flush_hash_page.
1326 * BIG ISSUE here: if the kernel uses a page from userspace without
1327 * unmapping it first, it may see the speculated version.
1329 if (local && cpu_has_feature(CPU_FTR_TM) &&
1330 current->thread.regs &&
1331 MSR_TM_ACTIVE(current->thread.regs->msr)) {
1333 tm_abort(TM_CAUSE_TLBI);
1338 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1339 void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
1340 pmd_t *pmdp, unsigned int psize, int ssize,
1341 unsigned long flags)
1343 int i, max_hpte_count, valid;
1344 unsigned long s_addr;
1345 unsigned char *hpte_slot_array;
1346 unsigned long hidx, shift, vpn, hash, slot;
1347 int local = flags & HPTE_LOCAL_UPDATE;
1349 s_addr = addr & HPAGE_PMD_MASK;
1350 hpte_slot_array = get_hpte_slot_array(pmdp);
1352 * IF we try to do a HUGE PTE update after a withdraw is done.
1353 * we will find the below NULL. This happens when we do
1354 * split_huge_page_pmd
1356 if (!hpte_slot_array)
1359 if (ppc_md.hugepage_invalidate) {
1360 ppc_md.hugepage_invalidate(vsid, s_addr, hpte_slot_array,
1361 psize, ssize, local);
1365 * No bluk hpte removal support, invalidate each entry
1367 shift = mmu_psize_defs[psize].shift;
1368 max_hpte_count = HPAGE_PMD_SIZE >> shift;
1369 for (i = 0; i < max_hpte_count; i++) {
1371 * 8 bits per each hpte entries
1372 * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
1374 valid = hpte_valid(hpte_slot_array, i);
1377 hidx = hpte_hash_index(hpte_slot_array, i);
1380 addr = s_addr + (i * (1ul << shift));
1381 vpn = hpt_vpn(addr, vsid, ssize);
1382 hash = hpt_hash(vpn, shift, ssize);
1383 if (hidx & _PTEIDX_SECONDARY)
1386 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1387 slot += hidx & _PTEIDX_GROUP_IX;
1388 ppc_md.hpte_invalidate(slot, vpn, psize,
1389 MMU_PAGE_16M, ssize, local);
1392 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1393 /* Transactions are not aborted by tlbiel, only tlbie.
1394 * Without, syncing a page back to a block device w/ PIO could pick up
1395 * transactional data (bad!) so we force an abort here. Before the
1396 * sync the page will be made read-only, which will flush_hash_page.
1397 * BIG ISSUE here: if the kernel uses a page from userspace without
1398 * unmapping it first, it may see the speculated version.
1400 if (local && cpu_has_feature(CPU_FTR_TM) &&
1401 current->thread.regs &&
1402 MSR_TM_ACTIVE(current->thread.regs->msr)) {
1404 tm_abort(TM_CAUSE_TLBI);
1409 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1411 void flush_hash_range(unsigned long number, int local)
1413 if (ppc_md.flush_hash_range)
1414 ppc_md.flush_hash_range(number, local);
1417 struct ppc64_tlb_batch *batch =
1418 this_cpu_ptr(&ppc64_tlb_batch);
1420 for (i = 0; i < number; i++)
1421 flush_hash_page(batch->vpn[i], batch->pte[i],
1422 batch->psize, batch->ssize, local);
1427 * low_hash_fault is called when we the low level hash code failed
1428 * to instert a PTE due to an hypervisor error
1430 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1432 enum ctx_state prev_state = exception_enter();
1434 if (user_mode(regs)) {
1435 #ifdef CONFIG_PPC_SUBPAGE_PROT
1437 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1440 _exception(SIGBUS, regs, BUS_ADRERR, address);
1442 bad_page_fault(regs, address, SIGBUS);
1444 exception_exit(prev_state);
1447 long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1448 unsigned long pa, unsigned long rflags,
1449 unsigned long vflags, int psize, int ssize)
1451 unsigned long hpte_group;
1455 hpte_group = ((hash & htab_hash_mask) *
1456 HPTES_PER_GROUP) & ~0x7UL;
1458 /* Insert into the hash table, primary slot */
1459 slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1460 psize, psize, ssize);
1462 /* Primary is full, try the secondary */
1463 if (unlikely(slot == -1)) {
1464 hpte_group = ((~hash & htab_hash_mask) *
1465 HPTES_PER_GROUP) & ~0x7UL;
1466 slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags,
1467 vflags | HPTE_V_SECONDARY,
1468 psize, psize, ssize);
1471 hpte_group = ((hash & htab_hash_mask) *
1472 HPTES_PER_GROUP)&~0x7UL;
1474 ppc_md.hpte_remove(hpte_group);
1482 #ifdef CONFIG_DEBUG_PAGEALLOC
1483 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1486 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1487 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1488 unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL));
1491 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1493 /* Don't create HPTE entries for bad address */
1497 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1499 mmu_linear_psize, mmu_kernel_ssize);
1502 spin_lock(&linear_map_hash_lock);
1503 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1504 linear_map_hash_slots[lmi] = ret | 0x80;
1505 spin_unlock(&linear_map_hash_lock);
1508 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1510 unsigned long hash, hidx, slot;
1511 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1512 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1514 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1515 spin_lock(&linear_map_hash_lock);
1516 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1517 hidx = linear_map_hash_slots[lmi] & 0x7f;
1518 linear_map_hash_slots[lmi] = 0;
1519 spin_unlock(&linear_map_hash_lock);
1520 if (hidx & _PTEIDX_SECONDARY)
1522 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1523 slot += hidx & _PTEIDX_GROUP_IX;
1524 ppc_md.hpte_invalidate(slot, vpn, mmu_linear_psize, mmu_linear_psize,
1525 mmu_kernel_ssize, 0);
1528 void __kernel_map_pages(struct page *page, int numpages, int enable)
1530 unsigned long flags, vaddr, lmi;
1533 local_irq_save(flags);
1534 for (i = 0; i < numpages; i++, page++) {
1535 vaddr = (unsigned long)page_address(page);
1536 lmi = __pa(vaddr) >> PAGE_SHIFT;
1537 if (lmi >= linear_map_hash_count)
1540 kernel_map_linear_page(vaddr, lmi);
1542 kernel_unmap_linear_page(vaddr, lmi);
1544 local_irq_restore(flags);
1546 #endif /* CONFIG_DEBUG_PAGEALLOC */
1548 void setup_initial_memory_limit(phys_addr_t first_memblock_base,
1549 phys_addr_t first_memblock_size)
1551 /* We don't currently support the first MEMBLOCK not mapping 0
1552 * physical on those processors
1554 BUG_ON(first_memblock_base != 0);
1556 /* On LPAR systems, the first entry is our RMA region,
1557 * non-LPAR 64-bit hash MMU systems don't have a limitation
1558 * on real mode access, but using the first entry works well
1559 * enough. We also clamp it to 1G to avoid some funky things
1560 * such as RTAS bugs etc...
1562 ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
1564 /* Finally limit subsequent allocations */
1565 memblock_set_current_limit(ppc64_rma_size);