2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/export.h>
31 #include <linux/ctype.h>
32 #include <linux/cache.h>
33 #include <linux/init.h>
34 #include <linux/signal.h>
35 #include <linux/memblock.h>
37 #include <asm/processor.h>
38 #include <asm/pgtable.h>
40 #include <asm/mmu_context.h>
42 #include <asm/types.h>
43 #include <asm/system.h>
44 #include <asm/uaccess.h>
45 #include <asm/machdep.h>
47 #include <asm/abs_addr.h>
48 #include <asm/tlbflush.h>
52 #include <asm/cacheflush.h>
53 #include <asm/cputable.h>
54 #include <asm/sections.h>
57 #include <asm/code-patching.h>
58 #include <asm/fadump.h>
59 #include <asm/firmware.h>
62 #define DBG(fmt...) udbg_printf(fmt)
68 #define DBG_LOW(fmt...) udbg_printf(fmt)
70 #define DBG_LOW(fmt...)
78 * Note: pte --> Linux PTE
79 * HPTE --> PowerPC Hashed Page Table Entry
82 * htab_initialize is called with the MMU off (of course), but
83 * the kernel has been copied down to zero so it can directly
84 * reference global data. At this point it is very difficult
85 * to print debug info.
90 extern unsigned long dart_tablebase;
91 #endif /* CONFIG_U3_DART */
93 static unsigned long _SDR1;
94 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
96 struct hash_pte *htab_address;
97 unsigned long htab_size_bytes;
98 unsigned long htab_hash_mask;
99 EXPORT_SYMBOL_GPL(htab_hash_mask);
100 int mmu_linear_psize = MMU_PAGE_4K;
101 int mmu_virtual_psize = MMU_PAGE_4K;
102 int mmu_vmalloc_psize = MMU_PAGE_4K;
103 #ifdef CONFIG_SPARSEMEM_VMEMMAP
104 int mmu_vmemmap_psize = MMU_PAGE_4K;
106 int mmu_io_psize = MMU_PAGE_4K;
107 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
108 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
109 u16 mmu_slb_size = 64;
110 EXPORT_SYMBOL_GPL(mmu_slb_size);
111 #ifdef CONFIG_PPC_64K_PAGES
112 int mmu_ci_restrictions;
114 #ifdef CONFIG_DEBUG_PAGEALLOC
115 static u8 *linear_map_hash_slots;
116 static unsigned long linear_map_hash_count;
117 static DEFINE_SPINLOCK(linear_map_hash_lock);
118 #endif /* CONFIG_DEBUG_PAGEALLOC */
120 /* There are definitions of page sizes arrays to be used when none
121 * is provided by the firmware.
124 /* Pre-POWER4 CPUs (4k pages only)
126 static struct mmu_psize_def mmu_psize_defaults_old[] = {
136 /* POWER4, GPUL, POWER5
138 * Support for 16Mb large pages
140 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
157 static unsigned long htab_convert_pte_flags(unsigned long pteflags)
159 unsigned long rflags = pteflags & 0x1fa;
161 /* _PAGE_EXEC -> NOEXEC */
162 if ((pteflags & _PAGE_EXEC) == 0)
165 /* PP bits. PAGE_USER is already PP bit 0x2, so we only
166 * need to add in 0x1 if it's a read-only user page
168 if ((pteflags & _PAGE_USER) && !((pteflags & _PAGE_RW) &&
169 (pteflags & _PAGE_DIRTY)))
173 return rflags | HPTE_R_C;
176 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
177 unsigned long pstart, unsigned long prot,
178 int psize, int ssize)
180 unsigned long vaddr, paddr;
181 unsigned int step, shift;
184 shift = mmu_psize_defs[psize].shift;
187 prot = htab_convert_pte_flags(prot);
189 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
190 vstart, vend, pstart, prot, psize, ssize);
192 for (vaddr = vstart, paddr = pstart; vaddr < vend;
193 vaddr += step, paddr += step) {
194 unsigned long hash, hpteg;
195 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
196 unsigned long va = hpt_va(vaddr, vsid, ssize);
197 unsigned long tprot = prot;
199 /* Make kernel text executable */
200 if (overlaps_kernel_text(vaddr, vaddr + step))
203 hash = hpt_hash(va, shift, ssize);
204 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
206 BUG_ON(!ppc_md.hpte_insert);
207 ret = ppc_md.hpte_insert(hpteg, va, paddr, tprot,
208 HPTE_V_BOLTED, psize, ssize);
212 #ifdef CONFIG_DEBUG_PAGEALLOC
213 if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
214 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
215 #endif /* CONFIG_DEBUG_PAGEALLOC */
217 return ret < 0 ? ret : 0;
220 #ifdef CONFIG_MEMORY_HOTPLUG
221 static int htab_remove_mapping(unsigned long vstart, unsigned long vend,
222 int psize, int ssize)
225 unsigned int step, shift;
227 shift = mmu_psize_defs[psize].shift;
230 if (!ppc_md.hpte_removebolted) {
231 printk(KERN_WARNING "Platform doesn't implement "
232 "hpte_removebolted\n");
236 for (vaddr = vstart; vaddr < vend; vaddr += step)
237 ppc_md.hpte_removebolted(vaddr, psize, ssize);
241 #endif /* CONFIG_MEMORY_HOTPLUG */
243 static int __init htab_dt_scan_seg_sizes(unsigned long node,
244 const char *uname, int depth,
247 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
249 unsigned long size = 0;
251 /* We are scanning "cpu" nodes only */
252 if (type == NULL || strcmp(type, "cpu") != 0)
255 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes",
259 for (; size >= 4; size -= 4, ++prop) {
261 DBG("1T segment support detected\n");
262 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
266 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
270 static void __init htab_init_seg_sizes(void)
272 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
275 static int __init htab_dt_scan_page_sizes(unsigned long node,
276 const char *uname, int depth,
279 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
281 unsigned long size = 0;
283 /* We are scanning "cpu" nodes only */
284 if (type == NULL || strcmp(type, "cpu") != 0)
287 prop = (u32 *)of_get_flat_dt_prop(node,
288 "ibm,segment-page-sizes", &size);
290 DBG("Page sizes from device-tree:\n");
292 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
294 unsigned int shift = prop[0];
295 unsigned int slbenc = prop[1];
296 unsigned int lpnum = prop[2];
297 unsigned int lpenc = 0;
298 struct mmu_psize_def *def;
301 size -= 3; prop += 3;
302 while(size > 0 && lpnum) {
303 if (prop[0] == shift)
305 prop += 2; size -= 2;
320 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
328 def = &mmu_psize_defs[idx];
333 def->avpnm = (1 << (shift - 23)) - 1;
336 /* We don't know for sure what's up with tlbiel, so
337 * for now we only set it for 4K and 64K pages
339 if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)
344 DBG(" %d: shift=%02x, sllp=%04lx, avpnm=%08lx, "
345 "tlbiel=%d, penc=%d\n",
346 idx, shift, def->sllp, def->avpnm, def->tlbiel,
354 #ifdef CONFIG_HUGETLB_PAGE
355 /* Scan for 16G memory blocks that have been set aside for huge pages
356 * and reserve those blocks for 16G huge pages.
358 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
359 const char *uname, int depth,
361 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
362 unsigned long *addr_prop;
363 u32 *page_count_prop;
364 unsigned int expected_pages;
365 long unsigned int phys_addr;
366 long unsigned int block_size;
368 /* We are scanning "memory" nodes only */
369 if (type == NULL || strcmp(type, "memory") != 0)
372 /* This property is the log base 2 of the number of virtual pages that
373 * will represent this memory block. */
374 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
375 if (page_count_prop == NULL)
377 expected_pages = (1 << page_count_prop[0]);
378 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
379 if (addr_prop == NULL)
381 phys_addr = addr_prop[0];
382 block_size = addr_prop[1];
383 if (block_size != (16 * GB))
385 printk(KERN_INFO "Huge page(16GB) memory: "
386 "addr = 0x%lX size = 0x%lX pages = %d\n",
387 phys_addr, block_size, expected_pages);
388 if (phys_addr + (16 * GB) <= memblock_end_of_DRAM()) {
389 memblock_reserve(phys_addr, block_size * expected_pages);
390 add_gpage(phys_addr, block_size, expected_pages);
394 #endif /* CONFIG_HUGETLB_PAGE */
396 static void __init htab_init_page_sizes(void)
400 /* Default to 4K pages only */
401 memcpy(mmu_psize_defs, mmu_psize_defaults_old,
402 sizeof(mmu_psize_defaults_old));
405 * Try to find the available page sizes in the device-tree
407 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
408 if (rc != 0) /* Found */
412 * Not in the device-tree, let's fallback on known size
413 * list for 16M capable GP & GR
415 if (mmu_has_feature(MMU_FTR_16M_PAGE))
416 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
417 sizeof(mmu_psize_defaults_gp));
419 #ifndef CONFIG_DEBUG_PAGEALLOC
421 * Pick a size for the linear mapping. Currently, we only support
422 * 16M, 1M and 4K which is the default
424 if (mmu_psize_defs[MMU_PAGE_16M].shift)
425 mmu_linear_psize = MMU_PAGE_16M;
426 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
427 mmu_linear_psize = MMU_PAGE_1M;
428 #endif /* CONFIG_DEBUG_PAGEALLOC */
430 #ifdef CONFIG_PPC_64K_PAGES
432 * Pick a size for the ordinary pages. Default is 4K, we support
433 * 64K for user mappings and vmalloc if supported by the processor.
434 * We only use 64k for ioremap if the processor
435 * (and firmware) support cache-inhibited large pages.
436 * If not, we use 4k and set mmu_ci_restrictions so that
437 * hash_page knows to switch processes that use cache-inhibited
438 * mappings to 4k pages.
440 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
441 mmu_virtual_psize = MMU_PAGE_64K;
442 mmu_vmalloc_psize = MMU_PAGE_64K;
443 if (mmu_linear_psize == MMU_PAGE_4K)
444 mmu_linear_psize = MMU_PAGE_64K;
445 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
447 * Don't use 64k pages for ioremap on pSeries, since
448 * that would stop us accessing the HEA ethernet.
450 if (!machine_is(pseries))
451 mmu_io_psize = MMU_PAGE_64K;
453 mmu_ci_restrictions = 1;
455 #endif /* CONFIG_PPC_64K_PAGES */
457 #ifdef CONFIG_SPARSEMEM_VMEMMAP
458 /* We try to use 16M pages for vmemmap if that is supported
459 * and we have at least 1G of RAM at boot
461 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
462 memblock_phys_mem_size() >= 0x40000000)
463 mmu_vmemmap_psize = MMU_PAGE_16M;
464 else if (mmu_psize_defs[MMU_PAGE_64K].shift)
465 mmu_vmemmap_psize = MMU_PAGE_64K;
467 mmu_vmemmap_psize = MMU_PAGE_4K;
468 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
470 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
471 "virtual = %d, io = %d"
472 #ifdef CONFIG_SPARSEMEM_VMEMMAP
476 mmu_psize_defs[mmu_linear_psize].shift,
477 mmu_psize_defs[mmu_virtual_psize].shift,
478 mmu_psize_defs[mmu_io_psize].shift
479 #ifdef CONFIG_SPARSEMEM_VMEMMAP
480 ,mmu_psize_defs[mmu_vmemmap_psize].shift
484 #ifdef CONFIG_HUGETLB_PAGE
485 /* Reserve 16G huge page memory sections for huge pages */
486 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
487 #endif /* CONFIG_HUGETLB_PAGE */
490 static int __init htab_dt_scan_pftsize(unsigned long node,
491 const char *uname, int depth,
494 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
497 /* We are scanning "cpu" nodes only */
498 if (type == NULL || strcmp(type, "cpu") != 0)
501 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
503 /* pft_size[0] is the NUMA CEC cookie */
504 ppc64_pft_size = prop[1];
510 static unsigned long __init htab_get_table_size(void)
512 unsigned long mem_size, rnd_mem_size, pteg_count, psize;
514 /* If hash size isn't already provided by the platform, we try to
515 * retrieve it from the device-tree. If it's not there neither, we
516 * calculate it now based on the total RAM size
518 if (ppc64_pft_size == 0)
519 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
521 return 1UL << ppc64_pft_size;
523 /* round mem_size up to next power of 2 */
524 mem_size = memblock_phys_mem_size();
525 rnd_mem_size = 1UL << __ilog2(mem_size);
526 if (rnd_mem_size < mem_size)
530 psize = mmu_psize_defs[mmu_virtual_psize].shift;
531 pteg_count = max(rnd_mem_size >> (psize + 1), 1UL << 11);
533 return pteg_count << 7;
536 #ifdef CONFIG_MEMORY_HOTPLUG
537 int create_section_mapping(unsigned long start, unsigned long end)
539 return htab_bolt_mapping(start, end, __pa(start),
540 pgprot_val(PAGE_KERNEL), mmu_linear_psize,
544 int remove_section_mapping(unsigned long start, unsigned long end)
546 return htab_remove_mapping(start, end, mmu_linear_psize,
549 #endif /* CONFIG_MEMORY_HOTPLUG */
551 #define FUNCTION_TEXT(A) ((*(unsigned long *)(A)))
553 static void __init htab_finish_init(void)
555 extern unsigned int *htab_call_hpte_insert1;
556 extern unsigned int *htab_call_hpte_insert2;
557 extern unsigned int *htab_call_hpte_remove;
558 extern unsigned int *htab_call_hpte_updatepp;
560 #ifdef CONFIG_PPC_HAS_HASH_64K
561 extern unsigned int *ht64_call_hpte_insert1;
562 extern unsigned int *ht64_call_hpte_insert2;
563 extern unsigned int *ht64_call_hpte_remove;
564 extern unsigned int *ht64_call_hpte_updatepp;
566 patch_branch(ht64_call_hpte_insert1,
567 FUNCTION_TEXT(ppc_md.hpte_insert),
569 patch_branch(ht64_call_hpte_insert2,
570 FUNCTION_TEXT(ppc_md.hpte_insert),
572 patch_branch(ht64_call_hpte_remove,
573 FUNCTION_TEXT(ppc_md.hpte_remove),
575 patch_branch(ht64_call_hpte_updatepp,
576 FUNCTION_TEXT(ppc_md.hpte_updatepp),
579 #endif /* CONFIG_PPC_HAS_HASH_64K */
581 patch_branch(htab_call_hpte_insert1,
582 FUNCTION_TEXT(ppc_md.hpte_insert),
584 patch_branch(htab_call_hpte_insert2,
585 FUNCTION_TEXT(ppc_md.hpte_insert),
587 patch_branch(htab_call_hpte_remove,
588 FUNCTION_TEXT(ppc_md.hpte_remove),
590 patch_branch(htab_call_hpte_updatepp,
591 FUNCTION_TEXT(ppc_md.hpte_updatepp),
595 static void __init htab_initialize(void)
598 unsigned long pteg_count;
600 unsigned long base = 0, size = 0, limit;
601 struct memblock_region *reg;
603 DBG(" -> htab_initialize()\n");
605 /* Initialize segment sizes */
606 htab_init_seg_sizes();
608 /* Initialize page sizes */
609 htab_init_page_sizes();
611 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
612 mmu_kernel_ssize = MMU_SEGSIZE_1T;
613 mmu_highuser_ssize = MMU_SEGSIZE_1T;
614 printk(KERN_INFO "Using 1TB segments\n");
618 * Calculate the required size of the htab. We want the number of
619 * PTEGs to equal one half the number of real pages.
621 htab_size_bytes = htab_get_table_size();
622 pteg_count = htab_size_bytes >> 7;
624 htab_hash_mask = pteg_count - 1;
626 if (firmware_has_feature(FW_FEATURE_LPAR)) {
627 /* Using a hypervisor which owns the htab */
630 #ifdef CONFIG_FA_DUMP
632 * If firmware assisted dump is active firmware preserves
633 * the contents of htab along with entire partition memory.
634 * Clear the htab if firmware assisted dump is active so
635 * that we dont end up using old mappings.
637 if (is_fadump_active() && ppc_md.hpte_clear_all)
638 ppc_md.hpte_clear_all();
641 /* Find storage for the HPT. Must be contiguous in
642 * the absolute address space. On cell we want it to be
643 * in the first 2 Gig so we can use it for IOMMU hacks.
645 if (machine_is(cell))
648 limit = MEMBLOCK_ALLOC_ANYWHERE;
650 table = memblock_alloc_base(htab_size_bytes, htab_size_bytes, limit);
652 DBG("Hash table allocated at %lx, size: %lx\n", table,
655 htab_address = abs_to_virt(table);
657 /* htab absolute addr + encoded htabsize */
658 _SDR1 = table + __ilog2(pteg_count) - 11;
660 /* Initialize the HPT with no entries */
661 memset((void *)table, 0, htab_size_bytes);
664 mtspr(SPRN_SDR1, _SDR1);
667 prot = pgprot_val(PAGE_KERNEL);
669 #ifdef CONFIG_DEBUG_PAGEALLOC
670 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
671 linear_map_hash_slots = __va(memblock_alloc_base(linear_map_hash_count,
673 memset(linear_map_hash_slots, 0, linear_map_hash_count);
674 #endif /* CONFIG_DEBUG_PAGEALLOC */
676 /* On U3 based machines, we need to reserve the DART area and
677 * _NOT_ map it to avoid cache paradoxes as it's remapped non
681 /* create bolted the linear mapping in the hash table */
682 for_each_memblock(memory, reg) {
683 base = (unsigned long)__va(reg->base);
686 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
689 #ifdef CONFIG_U3_DART
690 /* Do not map the DART space. Fortunately, it will be aligned
691 * in such a way that it will not cross two memblock regions and
692 * will fit within a single 16Mb page.
693 * The DART space is assumed to be a full 16Mb region even if
694 * we only use 2Mb of that space. We will use more of it later
695 * for AGP GART. We have to use a full 16Mb large page.
697 DBG("DART base: %lx\n", dart_tablebase);
699 if (dart_tablebase != 0 && dart_tablebase >= base
700 && dart_tablebase < (base + size)) {
701 unsigned long dart_table_end = dart_tablebase + 16 * MB;
702 if (base != dart_tablebase)
703 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
707 if ((base + size) > dart_table_end)
708 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
710 __pa(dart_table_end),
716 #endif /* CONFIG_U3_DART */
717 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
718 prot, mmu_linear_psize, mmu_kernel_ssize));
720 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
723 * If we have a memory_limit and we've allocated TCEs then we need to
724 * explicitly map the TCE area at the top of RAM. We also cope with the
725 * case that the TCEs start below memory_limit.
726 * tce_alloc_start/end are 16MB aligned so the mapping should work
727 * for either 4K or 16MB pages.
729 if (tce_alloc_start) {
730 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
731 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
733 if (base + size >= tce_alloc_start)
734 tce_alloc_start = base + size + 1;
736 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
737 __pa(tce_alloc_start), prot,
738 mmu_linear_psize, mmu_kernel_ssize));
743 DBG(" <- htab_initialize()\n");
748 void __init early_init_mmu(void)
750 /* Setup initial STAB address in the PACA */
751 get_paca()->stab_real = __pa((u64)&initial_stab);
752 get_paca()->stab_addr = (u64)&initial_stab;
754 /* Initialize the MMU Hash table and create the linear mapping
755 * of memory. Has to be done before stab/slb initialization as
756 * this is currently where the page size encoding is obtained
760 /* Initialize stab / SLB management */
761 if (mmu_has_feature(MMU_FTR_SLB))
766 void __cpuinit early_init_mmu_secondary(void)
768 /* Initialize hash table for that CPU */
769 if (!firmware_has_feature(FW_FEATURE_LPAR))
770 mtspr(SPRN_SDR1, _SDR1);
772 /* Initialize STAB/SLB. We use a virtual address as it works
773 * in real mode on pSeries.
775 if (mmu_has_feature(MMU_FTR_SLB))
778 stab_initialize(get_paca()->stab_addr);
780 #endif /* CONFIG_SMP */
783 * Called by asm hashtable.S for doing lazy icache flush
785 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
789 if (!pfn_valid(pte_pfn(pte)))
792 page = pte_page(pte);
795 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
797 flush_dcache_icache_page(page);
798 set_bit(PG_arch_1, &page->flags);
805 #ifdef CONFIG_PPC_MM_SLICES
806 unsigned int get_paca_psize(unsigned long addr)
808 unsigned long index, slices;
810 if (addr < SLICE_LOW_TOP) {
811 slices = get_paca()->context.low_slices_psize;
812 index = GET_LOW_SLICE_INDEX(addr);
814 slices = get_paca()->context.high_slices_psize;
815 index = GET_HIGH_SLICE_INDEX(addr);
817 return (slices >> (index * 4)) & 0xF;
821 unsigned int get_paca_psize(unsigned long addr)
823 return get_paca()->context.user_psize;
828 * Demote a segment to using 4k pages.
829 * For now this makes the whole process use 4k pages.
831 #ifdef CONFIG_PPC_64K_PAGES
832 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
834 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
836 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
837 #ifdef CONFIG_SPU_BASE
838 spu_flush_all_slbs(mm);
840 if (get_paca_psize(addr) != MMU_PAGE_4K) {
841 get_paca()->context = mm->context;
842 slb_flush_and_rebolt();
845 #endif /* CONFIG_PPC_64K_PAGES */
847 #ifdef CONFIG_PPC_SUBPAGE_PROT
849 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
850 * Userspace sets the subpage permissions using the subpage_prot system call.
852 * Result is 0: full permissions, _PAGE_RW: read-only,
853 * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
855 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
857 struct subpage_prot_table *spt = &mm->context.spt;
861 if (ea >= spt->maxaddr)
863 if (ea < 0x100000000) {
864 /* addresses below 4GB use spt->low_prot */
865 sbpm = spt->low_prot;
867 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
871 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
874 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
876 /* extract 2-bit bitfield for this 4k subpage */
877 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
879 /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
880 spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0);
884 #else /* CONFIG_PPC_SUBPAGE_PROT */
885 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
891 void hash_failure_debug(unsigned long ea, unsigned long access,
892 unsigned long vsid, unsigned long trap,
893 int ssize, int psize, unsigned long pte)
895 if (!printk_ratelimit())
897 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
898 ea, access, current->comm);
899 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d psize=%d pte=0x%lx\n",
900 trap, vsid, ssize, psize, pte);
905 * 1 - normal page fault
906 * -1 - critical hash insertion error
907 * -2 - access not permitted by subpage protection mechanism
909 int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
913 struct mm_struct *mm;
916 const struct cpumask *tmp;
917 int rc, user_region = 0, local = 0;
920 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
923 if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) {
924 DBG_LOW(" out of pgtable range !\n");
928 /* Get region & vsid */
929 switch (REGION_ID(ea)) {
934 DBG_LOW(" user region with no mm !\n");
937 psize = get_slice_psize(mm, ea);
938 ssize = user_segment_size(ea);
939 vsid = get_vsid(mm->context.id, ea, ssize);
941 case VMALLOC_REGION_ID:
943 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
944 if (ea < VMALLOC_END)
945 psize = mmu_vmalloc_psize;
947 psize = mmu_io_psize;
948 ssize = mmu_kernel_ssize;
952 * Send the problem up to do_page_fault
956 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
963 /* Check CPU locality */
964 tmp = cpumask_of(smp_processor_id());
965 if (user_region && cpumask_equal(mm_cpumask(mm), tmp))
968 #ifndef CONFIG_PPC_64K_PAGES
969 /* If we use 4K pages and our psize is not 4K, then we might
970 * be hitting a special driver mapping, and need to align the
971 * address before we fetch the PTE.
973 * It could also be a hugepage mapping, in which case this is
974 * not necessary, but it's not harmful, either.
976 if (psize != MMU_PAGE_4K)
977 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
978 #endif /* CONFIG_PPC_64K_PAGES */
980 /* Get PTE and page size from page tables */
981 ptep = find_linux_pte_or_hugepte(pgdir, ea, &hugeshift);
982 if (ptep == NULL || !pte_present(*ptep)) {
983 DBG_LOW(" no PTE !\n");
987 /* Add _PAGE_PRESENT to the required access perm */
988 access |= _PAGE_PRESENT;
990 /* Pre-check access permissions (will be re-checked atomically
991 * in __hash_page_XX but this pre-check is a fast path
993 if (access & ~pte_val(*ptep)) {
994 DBG_LOW(" no access !\n");
998 #ifdef CONFIG_HUGETLB_PAGE
1000 return __hash_page_huge(ea, access, vsid, ptep, trap, local,
1001 ssize, hugeshift, psize);
1002 #endif /* CONFIG_HUGETLB_PAGE */
1004 #ifndef CONFIG_PPC_64K_PAGES
1005 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1007 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1008 pte_val(*(ptep + PTRS_PER_PTE)));
1010 /* Do actual hashing */
1011 #ifdef CONFIG_PPC_64K_PAGES
1012 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
1013 if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1014 demote_segment_4k(mm, ea);
1015 psize = MMU_PAGE_4K;
1018 /* If this PTE is non-cacheable and we have restrictions on
1019 * using non cacheable large pages, then we switch to 4k
1021 if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
1022 (pte_val(*ptep) & _PAGE_NO_CACHE)) {
1024 demote_segment_4k(mm, ea);
1025 psize = MMU_PAGE_4K;
1026 } else if (ea < VMALLOC_END) {
1028 * some driver did a non-cacheable mapping
1029 * in vmalloc space, so switch vmalloc
1032 printk(KERN_ALERT "Reducing vmalloc segment "
1033 "to 4kB pages because of "
1034 "non-cacheable mapping\n");
1035 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1036 #ifdef CONFIG_SPU_BASE
1037 spu_flush_all_slbs(mm);
1042 if (psize != get_paca_psize(ea)) {
1043 get_paca()->context = mm->context;
1044 slb_flush_and_rebolt();
1046 } else if (get_paca()->vmalloc_sllp !=
1047 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1048 get_paca()->vmalloc_sllp =
1049 mmu_psize_defs[mmu_vmalloc_psize].sllp;
1050 slb_vmalloc_update();
1052 #endif /* CONFIG_PPC_64K_PAGES */
1054 #ifdef CONFIG_PPC_HAS_HASH_64K
1055 if (psize == MMU_PAGE_64K)
1056 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1058 #endif /* CONFIG_PPC_HAS_HASH_64K */
1060 int spp = subpage_protection(mm, ea);
1064 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1068 /* Dump some info in case of hash insertion failure, they should
1069 * never happen so it is really useful to know if/when they do
1072 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1074 #ifndef CONFIG_PPC_64K_PAGES
1075 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1077 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1078 pte_val(*(ptep + PTRS_PER_PTE)));
1080 DBG_LOW(" -> rc=%d\n", rc);
1083 EXPORT_SYMBOL_GPL(hash_page);
1085 void hash_preload(struct mm_struct *mm, unsigned long ea,
1086 unsigned long access, unsigned long trap)
1091 unsigned long flags;
1092 int rc, ssize, local = 0;
1094 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1096 #ifdef CONFIG_PPC_MM_SLICES
1097 /* We only prefault standard pages for now */
1098 if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
1102 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1103 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1105 /* Get Linux PTE if available */
1109 ptep = find_linux_pte(pgdir, ea);
1113 #ifdef CONFIG_PPC_64K_PAGES
1114 /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
1115 * a 64K kernel), then we don't preload, hash_page() will take
1116 * care of it once we actually try to access the page.
1117 * That way we don't have to duplicate all of the logic for segment
1118 * page size demotion here
1120 if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
1122 #endif /* CONFIG_PPC_64K_PAGES */
1125 ssize = user_segment_size(ea);
1126 vsid = get_vsid(mm->context.id, ea, ssize);
1128 /* Hash doesn't like irqs */
1129 local_irq_save(flags);
1131 /* Is that local to this CPU ? */
1132 if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1136 #ifdef CONFIG_PPC_HAS_HASH_64K
1137 if (mm->context.user_psize == MMU_PAGE_64K)
1138 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1140 #endif /* CONFIG_PPC_HAS_HASH_64K */
1141 rc = __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
1142 subpage_protection(mm, ea));
1144 /* Dump some info in case of hash insertion failure, they should
1145 * never happen so it is really useful to know if/when they do
1148 hash_failure_debug(ea, access, vsid, trap, ssize,
1149 mm->context.user_psize, pte_val(*ptep));
1151 local_irq_restore(flags);
1154 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1155 * do not forget to update the assembly call site !
1157 void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
1160 unsigned long hash, index, shift, hidx, slot;
1162 DBG_LOW("flush_hash_page(va=%016lx)\n", va);
1163 pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
1164 hash = hpt_hash(va, shift, ssize);
1165 hidx = __rpte_to_hidx(pte, index);
1166 if (hidx & _PTEIDX_SECONDARY)
1168 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1169 slot += hidx & _PTEIDX_GROUP_IX;
1170 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
1171 ppc_md.hpte_invalidate(slot, va, psize, ssize, local);
1172 } pte_iterate_hashed_end();
1175 void flush_hash_range(unsigned long number, int local)
1177 if (ppc_md.flush_hash_range)
1178 ppc_md.flush_hash_range(number, local);
1181 struct ppc64_tlb_batch *batch =
1182 &__get_cpu_var(ppc64_tlb_batch);
1184 for (i = 0; i < number; i++)
1185 flush_hash_page(batch->vaddr[i], batch->pte[i],
1186 batch->psize, batch->ssize, local);
1191 * low_hash_fault is called when we the low level hash code failed
1192 * to instert a PTE due to an hypervisor error
1194 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1196 if (user_mode(regs)) {
1197 #ifdef CONFIG_PPC_SUBPAGE_PROT
1199 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1202 _exception(SIGBUS, regs, BUS_ADRERR, address);
1204 bad_page_fault(regs, address, SIGBUS);
1207 #ifdef CONFIG_DEBUG_PAGEALLOC
1208 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1210 unsigned long hash, hpteg;
1211 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1212 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1213 unsigned long mode = htab_convert_pte_flags(PAGE_KERNEL);
1216 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1217 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
1219 ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr),
1220 mode, HPTE_V_BOLTED,
1221 mmu_linear_psize, mmu_kernel_ssize);
1223 spin_lock(&linear_map_hash_lock);
1224 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1225 linear_map_hash_slots[lmi] = ret | 0x80;
1226 spin_unlock(&linear_map_hash_lock);
1229 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1231 unsigned long hash, hidx, slot;
1232 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1233 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1235 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1236 spin_lock(&linear_map_hash_lock);
1237 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1238 hidx = linear_map_hash_slots[lmi] & 0x7f;
1239 linear_map_hash_slots[lmi] = 0;
1240 spin_unlock(&linear_map_hash_lock);
1241 if (hidx & _PTEIDX_SECONDARY)
1243 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1244 slot += hidx & _PTEIDX_GROUP_IX;
1245 ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0);
1248 void kernel_map_pages(struct page *page, int numpages, int enable)
1250 unsigned long flags, vaddr, lmi;
1253 local_irq_save(flags);
1254 for (i = 0; i < numpages; i++, page++) {
1255 vaddr = (unsigned long)page_address(page);
1256 lmi = __pa(vaddr) >> PAGE_SHIFT;
1257 if (lmi >= linear_map_hash_count)
1260 kernel_map_linear_page(vaddr, lmi);
1262 kernel_unmap_linear_page(vaddr, lmi);
1264 local_irq_restore(flags);
1266 #endif /* CONFIG_DEBUG_PAGEALLOC */
1268 void setup_initial_memory_limit(phys_addr_t first_memblock_base,
1269 phys_addr_t first_memblock_size)
1271 /* We don't currently support the first MEMBLOCK not mapping 0
1272 * physical on those processors
1274 BUG_ON(first_memblock_base != 0);
1276 /* On LPAR systems, the first entry is our RMA region,
1277 * non-LPAR 64-bit hash MMU systems don't have a limitation
1278 * on real mode access, but using the first entry works well
1279 * enough. We also clamp it to 1G to avoid some funky things
1280 * such as RTAS bugs etc...
1282 ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
1284 /* Finally limit subsequent allocations */
1285 memblock_set_current_limit(ppc64_rma_size);