2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/export.h>
31 #include <linux/ctype.h>
32 #include <linux/cache.h>
33 #include <linux/init.h>
34 #include <linux/signal.h>
35 #include <linux/memblock.h>
36 #include <linux/context_tracking.h>
38 #include <asm/processor.h>
39 #include <asm/pgtable.h>
41 #include <asm/mmu_context.h>
43 #include <asm/types.h>
44 #include <asm/uaccess.h>
45 #include <asm/machdep.h>
47 #include <asm/tlbflush.h>
51 #include <asm/cacheflush.h>
52 #include <asm/cputable.h>
53 #include <asm/sections.h>
56 #include <asm/code-patching.h>
57 #include <asm/fadump.h>
58 #include <asm/firmware.h>
62 #define DBG(fmt...) udbg_printf(fmt)
68 #define DBG_LOW(fmt...) udbg_printf(fmt)
70 #define DBG_LOW(fmt...)
78 * Note: pte --> Linux PTE
79 * HPTE --> PowerPC Hashed Page Table Entry
82 * htab_initialize is called with the MMU off (of course), but
83 * the kernel has been copied down to zero so it can directly
84 * reference global data. At this point it is very difficult
85 * to print debug info.
90 extern unsigned long dart_tablebase;
91 #endif /* CONFIG_U3_DART */
93 static unsigned long _SDR1;
94 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
96 struct hash_pte *htab_address;
97 unsigned long htab_size_bytes;
98 unsigned long htab_hash_mask;
99 EXPORT_SYMBOL_GPL(htab_hash_mask);
100 int mmu_linear_psize = MMU_PAGE_4K;
101 int mmu_virtual_psize = MMU_PAGE_4K;
102 int mmu_vmalloc_psize = MMU_PAGE_4K;
103 #ifdef CONFIG_SPARSEMEM_VMEMMAP
104 int mmu_vmemmap_psize = MMU_PAGE_4K;
106 int mmu_io_psize = MMU_PAGE_4K;
107 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
108 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
109 u16 mmu_slb_size = 64;
110 EXPORT_SYMBOL_GPL(mmu_slb_size);
111 #ifdef CONFIG_PPC_64K_PAGES
112 int mmu_ci_restrictions;
114 #ifdef CONFIG_DEBUG_PAGEALLOC
115 static u8 *linear_map_hash_slots;
116 static unsigned long linear_map_hash_count;
117 static DEFINE_SPINLOCK(linear_map_hash_lock);
118 #endif /* CONFIG_DEBUG_PAGEALLOC */
120 /* There are definitions of page sizes arrays to be used when none
121 * is provided by the firmware.
124 /* Pre-POWER4 CPUs (4k pages only)
126 static struct mmu_psize_def mmu_psize_defaults_old[] = {
130 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
136 /* POWER4, GPUL, POWER5
138 * Support for 16Mb large pages
140 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
144 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
151 .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
152 [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
158 static unsigned long htab_convert_pte_flags(unsigned long pteflags)
160 unsigned long rflags = pteflags & 0x1fa;
162 /* _PAGE_EXEC -> NOEXEC */
163 if ((pteflags & _PAGE_EXEC) == 0)
166 /* PP bits. PAGE_USER is already PP bit 0x2, so we only
167 * need to add in 0x1 if it's a read-only user page
169 if ((pteflags & _PAGE_USER) && !((pteflags & _PAGE_RW) &&
170 (pteflags & _PAGE_DIRTY)))
173 * Always add "C" bit for perf. Memory coherence is always enabled
175 return rflags | HPTE_R_C | HPTE_R_M;
178 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
179 unsigned long pstart, unsigned long prot,
180 int psize, int ssize)
182 unsigned long vaddr, paddr;
183 unsigned int step, shift;
186 shift = mmu_psize_defs[psize].shift;
189 prot = htab_convert_pte_flags(prot);
191 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
192 vstart, vend, pstart, prot, psize, ssize);
194 for (vaddr = vstart, paddr = pstart; vaddr < vend;
195 vaddr += step, paddr += step) {
196 unsigned long hash, hpteg;
197 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
198 unsigned long vpn = hpt_vpn(vaddr, vsid, ssize);
199 unsigned long tprot = prot;
202 * If we hit a bad address return error.
206 /* Make kernel text executable */
207 if (overlaps_kernel_text(vaddr, vaddr + step))
210 /* Make kvm guest trampolines executable */
211 if (overlaps_kvm_tmp(vaddr, vaddr + step))
215 * If relocatable, check if it overlaps interrupt vectors that
216 * are copied down to real 0. For relocatable kernel
217 * (e.g. kdump case) we copy interrupt vectors down to real
218 * address 0. Mark that region as executable. This is
219 * because on p8 system with relocation on exception feature
220 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
221 * in order to execute the interrupt handlers in virtual
222 * mode the vector region need to be marked as executable.
224 if ((PHYSICAL_START > MEMORY_START) &&
225 overlaps_interrupt_vector_text(vaddr, vaddr + step))
228 hash = hpt_hash(vpn, shift, ssize);
229 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
231 BUG_ON(!ppc_md.hpte_insert);
232 ret = ppc_md.hpte_insert(hpteg, vpn, paddr, tprot,
233 HPTE_V_BOLTED, psize, psize, ssize);
237 #ifdef CONFIG_DEBUG_PAGEALLOC
238 if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
239 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
240 #endif /* CONFIG_DEBUG_PAGEALLOC */
242 return ret < 0 ? ret : 0;
245 #ifdef CONFIG_MEMORY_HOTPLUG
246 static int htab_remove_mapping(unsigned long vstart, unsigned long vend,
247 int psize, int ssize)
250 unsigned int step, shift;
252 shift = mmu_psize_defs[psize].shift;
255 if (!ppc_md.hpte_removebolted) {
256 printk(KERN_WARNING "Platform doesn't implement "
257 "hpte_removebolted\n");
261 for (vaddr = vstart; vaddr < vend; vaddr += step)
262 ppc_md.hpte_removebolted(vaddr, psize, ssize);
266 #endif /* CONFIG_MEMORY_HOTPLUG */
268 static int __init htab_dt_scan_seg_sizes(unsigned long node,
269 const char *uname, int depth,
272 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
274 unsigned long size = 0;
276 /* We are scanning "cpu" nodes only */
277 if (type == NULL || strcmp(type, "cpu") != 0)
280 prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
283 for (; size >= 4; size -= 4, ++prop) {
284 if (be32_to_cpu(prop[0]) == 40) {
285 DBG("1T segment support detected\n");
286 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
290 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
294 static void __init htab_init_seg_sizes(void)
296 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
299 static int __init get_idx_from_shift(unsigned int shift)
323 static int __init htab_dt_scan_page_sizes(unsigned long node,
324 const char *uname, int depth,
327 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
329 unsigned long size = 0;
331 /* We are scanning "cpu" nodes only */
332 if (type == NULL || strcmp(type, "cpu") != 0)
335 prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
337 pr_info("Page sizes from device-tree:\n");
339 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
341 unsigned int base_shift = be32_to_cpu(prop[0]);
342 unsigned int slbenc = be32_to_cpu(prop[1]);
343 unsigned int lpnum = be32_to_cpu(prop[2]);
344 struct mmu_psize_def *def;
347 size -= 3; prop += 3;
348 base_idx = get_idx_from_shift(base_shift);
351 * skip the pte encoding also
353 prop += lpnum * 2; size -= lpnum * 2;
356 def = &mmu_psize_defs[base_idx];
357 if (base_idx == MMU_PAGE_16M)
358 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
360 def->shift = base_shift;
361 if (base_shift <= 23)
364 def->avpnm = (1 << (base_shift - 23)) - 1;
367 * We don't know for sure what's up with tlbiel, so
368 * for now we only set it for 4K and 64K pages
370 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
375 while (size > 0 && lpnum) {
376 unsigned int shift = be32_to_cpu(prop[0]);
377 int penc = be32_to_cpu(prop[1]);
379 prop += 2; size -= 2;
382 idx = get_idx_from_shift(shift);
387 pr_err("Invalid penc for base_shift=%d "
388 "shift=%d\n", base_shift, shift);
390 def->penc[idx] = penc;
391 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
392 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
393 base_shift, shift, def->sllp,
394 def->avpnm, def->tlbiel, def->penc[idx]);
402 #ifdef CONFIG_HUGETLB_PAGE
403 /* Scan for 16G memory blocks that have been set aside for huge pages
404 * and reserve those blocks for 16G huge pages.
406 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
407 const char *uname, int depth,
409 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
411 __be32 *page_count_prop;
412 unsigned int expected_pages;
413 long unsigned int phys_addr;
414 long unsigned int block_size;
416 /* We are scanning "memory" nodes only */
417 if (type == NULL || strcmp(type, "memory") != 0)
420 /* This property is the log base 2 of the number of virtual pages that
421 * will represent this memory block. */
422 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
423 if (page_count_prop == NULL)
425 expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
426 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
427 if (addr_prop == NULL)
429 phys_addr = be64_to_cpu(addr_prop[0]);
430 block_size = be64_to_cpu(addr_prop[1]);
431 if (block_size != (16 * GB))
433 printk(KERN_INFO "Huge page(16GB) memory: "
434 "addr = 0x%lX size = 0x%lX pages = %d\n",
435 phys_addr, block_size, expected_pages);
436 if (phys_addr + (16 * GB) <= memblock_end_of_DRAM()) {
437 memblock_reserve(phys_addr, block_size * expected_pages);
438 add_gpage(phys_addr, block_size, expected_pages);
442 #endif /* CONFIG_HUGETLB_PAGE */
444 static void mmu_psize_set_default_penc(void)
447 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
448 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
449 mmu_psize_defs[bpsize].penc[apsize] = -1;
452 static void __init htab_init_page_sizes(void)
456 /* se the invalid penc to -1 */
457 mmu_psize_set_default_penc();
459 /* Default to 4K pages only */
460 memcpy(mmu_psize_defs, mmu_psize_defaults_old,
461 sizeof(mmu_psize_defaults_old));
464 * Try to find the available page sizes in the device-tree
466 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
467 if (rc != 0) /* Found */
471 * Not in the device-tree, let's fallback on known size
472 * list for 16M capable GP & GR
474 if (mmu_has_feature(MMU_FTR_16M_PAGE))
475 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
476 sizeof(mmu_psize_defaults_gp));
478 #ifndef CONFIG_DEBUG_PAGEALLOC
480 * Pick a size for the linear mapping. Currently, we only support
481 * 16M, 1M and 4K which is the default
483 if (mmu_psize_defs[MMU_PAGE_16M].shift)
484 mmu_linear_psize = MMU_PAGE_16M;
485 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
486 mmu_linear_psize = MMU_PAGE_1M;
487 #endif /* CONFIG_DEBUG_PAGEALLOC */
489 #ifdef CONFIG_PPC_64K_PAGES
491 * Pick a size for the ordinary pages. Default is 4K, we support
492 * 64K for user mappings and vmalloc if supported by the processor.
493 * We only use 64k for ioremap if the processor
494 * (and firmware) support cache-inhibited large pages.
495 * If not, we use 4k and set mmu_ci_restrictions so that
496 * hash_page knows to switch processes that use cache-inhibited
497 * mappings to 4k pages.
499 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
500 mmu_virtual_psize = MMU_PAGE_64K;
501 mmu_vmalloc_psize = MMU_PAGE_64K;
502 if (mmu_linear_psize == MMU_PAGE_4K)
503 mmu_linear_psize = MMU_PAGE_64K;
504 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
506 * Don't use 64k pages for ioremap on pSeries, since
507 * that would stop us accessing the HEA ethernet.
509 if (!machine_is(pseries))
510 mmu_io_psize = MMU_PAGE_64K;
512 mmu_ci_restrictions = 1;
514 #endif /* CONFIG_PPC_64K_PAGES */
516 #ifdef CONFIG_SPARSEMEM_VMEMMAP
517 /* We try to use 16M pages for vmemmap if that is supported
518 * and we have at least 1G of RAM at boot
520 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
521 memblock_phys_mem_size() >= 0x40000000)
522 mmu_vmemmap_psize = MMU_PAGE_16M;
523 else if (mmu_psize_defs[MMU_PAGE_64K].shift)
524 mmu_vmemmap_psize = MMU_PAGE_64K;
526 mmu_vmemmap_psize = MMU_PAGE_4K;
527 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
529 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
530 "virtual = %d, io = %d"
531 #ifdef CONFIG_SPARSEMEM_VMEMMAP
535 mmu_psize_defs[mmu_linear_psize].shift,
536 mmu_psize_defs[mmu_virtual_psize].shift,
537 mmu_psize_defs[mmu_io_psize].shift
538 #ifdef CONFIG_SPARSEMEM_VMEMMAP
539 ,mmu_psize_defs[mmu_vmemmap_psize].shift
543 #ifdef CONFIG_HUGETLB_PAGE
544 /* Reserve 16G huge page memory sections for huge pages */
545 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
546 #endif /* CONFIG_HUGETLB_PAGE */
549 static int __init htab_dt_scan_pftsize(unsigned long node,
550 const char *uname, int depth,
553 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
556 /* We are scanning "cpu" nodes only */
557 if (type == NULL || strcmp(type, "cpu") != 0)
560 prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
562 /* pft_size[0] is the NUMA CEC cookie */
563 ppc64_pft_size = be32_to_cpu(prop[1]);
569 static unsigned long __init htab_get_table_size(void)
571 unsigned long mem_size, rnd_mem_size, pteg_count, psize;
573 /* If hash size isn't already provided by the platform, we try to
574 * retrieve it from the device-tree. If it's not there neither, we
575 * calculate it now based on the total RAM size
577 if (ppc64_pft_size == 0)
578 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
580 return 1UL << ppc64_pft_size;
582 /* round mem_size up to next power of 2 */
583 mem_size = memblock_phys_mem_size();
584 rnd_mem_size = 1UL << __ilog2(mem_size);
585 if (rnd_mem_size < mem_size)
589 psize = mmu_psize_defs[mmu_virtual_psize].shift;
590 pteg_count = max(rnd_mem_size >> (psize + 1), 1UL << 11);
592 return pteg_count << 7;
595 #ifdef CONFIG_MEMORY_HOTPLUG
596 int create_section_mapping(unsigned long start, unsigned long end)
598 return htab_bolt_mapping(start, end, __pa(start),
599 pgprot_val(PAGE_KERNEL), mmu_linear_psize,
603 int remove_section_mapping(unsigned long start, unsigned long end)
605 return htab_remove_mapping(start, end, mmu_linear_psize,
608 #endif /* CONFIG_MEMORY_HOTPLUG */
610 #define FUNCTION_TEXT(A) ((*(unsigned long *)(A)))
612 static void __init htab_finish_init(void)
614 extern unsigned int *htab_call_hpte_insert1;
615 extern unsigned int *htab_call_hpte_insert2;
616 extern unsigned int *htab_call_hpte_remove;
617 extern unsigned int *htab_call_hpte_updatepp;
619 #ifdef CONFIG_PPC_HAS_HASH_64K
620 extern unsigned int *ht64_call_hpte_insert1;
621 extern unsigned int *ht64_call_hpte_insert2;
622 extern unsigned int *ht64_call_hpte_remove;
623 extern unsigned int *ht64_call_hpte_updatepp;
625 patch_branch(ht64_call_hpte_insert1,
626 FUNCTION_TEXT(ppc_md.hpte_insert),
628 patch_branch(ht64_call_hpte_insert2,
629 FUNCTION_TEXT(ppc_md.hpte_insert),
631 patch_branch(ht64_call_hpte_remove,
632 FUNCTION_TEXT(ppc_md.hpte_remove),
634 patch_branch(ht64_call_hpte_updatepp,
635 FUNCTION_TEXT(ppc_md.hpte_updatepp),
638 #endif /* CONFIG_PPC_HAS_HASH_64K */
640 patch_branch(htab_call_hpte_insert1,
641 FUNCTION_TEXT(ppc_md.hpte_insert),
643 patch_branch(htab_call_hpte_insert2,
644 FUNCTION_TEXT(ppc_md.hpte_insert),
646 patch_branch(htab_call_hpte_remove,
647 FUNCTION_TEXT(ppc_md.hpte_remove),
649 patch_branch(htab_call_hpte_updatepp,
650 FUNCTION_TEXT(ppc_md.hpte_updatepp),
654 static void __init htab_initialize(void)
657 unsigned long pteg_count;
659 unsigned long base = 0, size = 0, limit;
660 struct memblock_region *reg;
662 DBG(" -> htab_initialize()\n");
664 /* Initialize segment sizes */
665 htab_init_seg_sizes();
667 /* Initialize page sizes */
668 htab_init_page_sizes();
670 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
671 mmu_kernel_ssize = MMU_SEGSIZE_1T;
672 mmu_highuser_ssize = MMU_SEGSIZE_1T;
673 printk(KERN_INFO "Using 1TB segments\n");
677 * Calculate the required size of the htab. We want the number of
678 * PTEGs to equal one half the number of real pages.
680 htab_size_bytes = htab_get_table_size();
681 pteg_count = htab_size_bytes >> 7;
683 htab_hash_mask = pteg_count - 1;
685 if (firmware_has_feature(FW_FEATURE_LPAR)) {
686 /* Using a hypervisor which owns the htab */
689 #ifdef CONFIG_FA_DUMP
691 * If firmware assisted dump is active firmware preserves
692 * the contents of htab along with entire partition memory.
693 * Clear the htab if firmware assisted dump is active so
694 * that we dont end up using old mappings.
696 if (is_fadump_active() && ppc_md.hpte_clear_all)
697 ppc_md.hpte_clear_all();
700 /* Find storage for the HPT. Must be contiguous in
701 * the absolute address space. On cell we want it to be
702 * in the first 2 Gig so we can use it for IOMMU hacks.
704 if (machine_is(cell))
707 limit = MEMBLOCK_ALLOC_ANYWHERE;
709 table = memblock_alloc_base(htab_size_bytes, htab_size_bytes, limit);
711 DBG("Hash table allocated at %lx, size: %lx\n", table,
714 htab_address = __va(table);
716 /* htab absolute addr + encoded htabsize */
717 _SDR1 = table + __ilog2(pteg_count) - 11;
719 /* Initialize the HPT with no entries */
720 memset((void *)table, 0, htab_size_bytes);
723 mtspr(SPRN_SDR1, _SDR1);
726 prot = pgprot_val(PAGE_KERNEL);
728 #ifdef CONFIG_DEBUG_PAGEALLOC
729 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
730 linear_map_hash_slots = __va(memblock_alloc_base(linear_map_hash_count,
732 memset(linear_map_hash_slots, 0, linear_map_hash_count);
733 #endif /* CONFIG_DEBUG_PAGEALLOC */
735 /* On U3 based machines, we need to reserve the DART area and
736 * _NOT_ map it to avoid cache paradoxes as it's remapped non
740 /* create bolted the linear mapping in the hash table */
741 for_each_memblock(memory, reg) {
742 base = (unsigned long)__va(reg->base);
745 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
748 #ifdef CONFIG_U3_DART
749 /* Do not map the DART space. Fortunately, it will be aligned
750 * in such a way that it will not cross two memblock regions and
751 * will fit within a single 16Mb page.
752 * The DART space is assumed to be a full 16Mb region even if
753 * we only use 2Mb of that space. We will use more of it later
754 * for AGP GART. We have to use a full 16Mb large page.
756 DBG("DART base: %lx\n", dart_tablebase);
758 if (dart_tablebase != 0 && dart_tablebase >= base
759 && dart_tablebase < (base + size)) {
760 unsigned long dart_table_end = dart_tablebase + 16 * MB;
761 if (base != dart_tablebase)
762 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
766 if ((base + size) > dart_table_end)
767 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
769 __pa(dart_table_end),
775 #endif /* CONFIG_U3_DART */
776 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
777 prot, mmu_linear_psize, mmu_kernel_ssize));
779 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
782 * If we have a memory_limit and we've allocated TCEs then we need to
783 * explicitly map the TCE area at the top of RAM. We also cope with the
784 * case that the TCEs start below memory_limit.
785 * tce_alloc_start/end are 16MB aligned so the mapping should work
786 * for either 4K or 16MB pages.
788 if (tce_alloc_start) {
789 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
790 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
792 if (base + size >= tce_alloc_start)
793 tce_alloc_start = base + size + 1;
795 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
796 __pa(tce_alloc_start), prot,
797 mmu_linear_psize, mmu_kernel_ssize));
802 DBG(" <- htab_initialize()\n");
807 void __init early_init_mmu(void)
809 /* Setup initial STAB address in the PACA */
810 get_paca()->stab_real = __pa((u64)&initial_stab);
811 get_paca()->stab_addr = (u64)&initial_stab;
813 /* Initialize the MMU Hash table and create the linear mapping
814 * of memory. Has to be done before stab/slb initialization as
815 * this is currently where the page size encoding is obtained
819 /* Initialize stab / SLB management */
820 if (mmu_has_feature(MMU_FTR_SLB))
823 stab_initialize(get_paca()->stab_real);
827 void early_init_mmu_secondary(void)
829 /* Initialize hash table for that CPU */
830 if (!firmware_has_feature(FW_FEATURE_LPAR))
831 mtspr(SPRN_SDR1, _SDR1);
833 /* Initialize STAB/SLB. We use a virtual address as it works
834 * in real mode on pSeries.
836 if (mmu_has_feature(MMU_FTR_SLB))
839 stab_initialize(get_paca()->stab_addr);
841 #endif /* CONFIG_SMP */
844 * Called by asm hashtable.S for doing lazy icache flush
846 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
850 if (!pfn_valid(pte_pfn(pte)))
853 page = pte_page(pte);
856 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
858 flush_dcache_icache_page(page);
859 set_bit(PG_arch_1, &page->flags);
866 #ifdef CONFIG_PPC_MM_SLICES
867 unsigned int get_paca_psize(unsigned long addr)
870 unsigned char *hpsizes;
871 unsigned long index, mask_index;
873 if (addr < SLICE_LOW_TOP) {
874 lpsizes = get_paca()->context.low_slices_psize;
875 index = GET_LOW_SLICE_INDEX(addr);
876 return (lpsizes >> (index * 4)) & 0xF;
878 hpsizes = get_paca()->context.high_slices_psize;
879 index = GET_HIGH_SLICE_INDEX(addr);
880 mask_index = index & 0x1;
881 return (hpsizes[index >> 1] >> (mask_index * 4)) & 0xF;
885 unsigned int get_paca_psize(unsigned long addr)
887 return get_paca()->context.user_psize;
892 * Demote a segment to using 4k pages.
893 * For now this makes the whole process use 4k pages.
895 #ifdef CONFIG_PPC_64K_PAGES
896 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
898 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
900 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
901 #ifdef CONFIG_SPU_BASE
902 spu_flush_all_slbs(mm);
904 if (get_paca_psize(addr) != MMU_PAGE_4K) {
905 get_paca()->context = mm->context;
906 slb_flush_and_rebolt();
909 #endif /* CONFIG_PPC_64K_PAGES */
911 #ifdef CONFIG_PPC_SUBPAGE_PROT
913 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
914 * Userspace sets the subpage permissions using the subpage_prot system call.
916 * Result is 0: full permissions, _PAGE_RW: read-only,
917 * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
919 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
921 struct subpage_prot_table *spt = &mm->context.spt;
925 if (ea >= spt->maxaddr)
927 if (ea < 0x100000000UL) {
928 /* addresses below 4GB use spt->low_prot */
929 sbpm = spt->low_prot;
931 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
935 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
938 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
940 /* extract 2-bit bitfield for this 4k subpage */
941 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
943 /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
944 spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0);
948 #else /* CONFIG_PPC_SUBPAGE_PROT */
949 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
955 void hash_failure_debug(unsigned long ea, unsigned long access,
956 unsigned long vsid, unsigned long trap,
957 int ssize, int psize, int lpsize, unsigned long pte)
959 if (!printk_ratelimit())
961 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
962 ea, access, current->comm);
963 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
964 trap, vsid, ssize, psize, lpsize, pte);
969 * 1 - normal page fault
970 * -1 - critical hash insertion error
971 * -2 - access not permitted by subpage protection mechanism
973 int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
975 enum ctx_state prev_state = exception_enter();
978 struct mm_struct *mm;
981 const struct cpumask *tmp;
982 int rc, user_region = 0, local = 0;
985 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
988 /* Get region & vsid */
989 switch (REGION_ID(ea)) {
994 DBG_LOW(" user region with no mm !\n");
998 psize = get_slice_psize(mm, ea);
999 ssize = user_segment_size(ea);
1000 vsid = get_vsid(mm->context.id, ea, ssize);
1002 case VMALLOC_REGION_ID:
1004 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1005 if (ea < VMALLOC_END)
1006 psize = mmu_vmalloc_psize;
1008 psize = mmu_io_psize;
1009 ssize = mmu_kernel_ssize;
1012 /* Not a valid range
1013 * Send the problem up to do_page_fault
1018 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1022 DBG_LOW("Bad address!\n");
1028 if (pgdir == NULL) {
1033 /* Check CPU locality */
1034 tmp = cpumask_of(smp_processor_id());
1035 if (user_region && cpumask_equal(mm_cpumask(mm), tmp))
1038 #ifndef CONFIG_PPC_64K_PAGES
1039 /* If we use 4K pages and our psize is not 4K, then we might
1040 * be hitting a special driver mapping, and need to align the
1041 * address before we fetch the PTE.
1043 * It could also be a hugepage mapping, in which case this is
1044 * not necessary, but it's not harmful, either.
1046 if (psize != MMU_PAGE_4K)
1047 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1048 #endif /* CONFIG_PPC_64K_PAGES */
1050 /* Get PTE and page size from page tables */
1051 ptep = find_linux_pte_or_hugepte(pgdir, ea, &hugeshift);
1052 if (ptep == NULL || !pte_present(*ptep)) {
1053 DBG_LOW(" no PTE !\n");
1058 /* Add _PAGE_PRESENT to the required access perm */
1059 access |= _PAGE_PRESENT;
1061 /* Pre-check access permissions (will be re-checked atomically
1062 * in __hash_page_XX but this pre-check is a fast path
1064 if (access & ~pte_val(*ptep)) {
1065 DBG_LOW(" no access !\n");
1071 if (pmd_trans_huge(*(pmd_t *)ptep))
1072 rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1073 trap, local, ssize, psize);
1074 #ifdef CONFIG_HUGETLB_PAGE
1076 rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1077 local, ssize, hugeshift, psize);
1081 * if we have hugeshift, and is not transhuge with
1082 * hugetlb disabled, something is really wrong.
1091 #ifndef CONFIG_PPC_64K_PAGES
1092 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1094 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1095 pte_val(*(ptep + PTRS_PER_PTE)));
1097 /* Do actual hashing */
1098 #ifdef CONFIG_PPC_64K_PAGES
1099 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
1100 if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1101 demote_segment_4k(mm, ea);
1102 psize = MMU_PAGE_4K;
1105 /* If this PTE is non-cacheable and we have restrictions on
1106 * using non cacheable large pages, then we switch to 4k
1108 if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
1109 (pte_val(*ptep) & _PAGE_NO_CACHE)) {
1111 demote_segment_4k(mm, ea);
1112 psize = MMU_PAGE_4K;
1113 } else if (ea < VMALLOC_END) {
1115 * some driver did a non-cacheable mapping
1116 * in vmalloc space, so switch vmalloc
1119 printk(KERN_ALERT "Reducing vmalloc segment "
1120 "to 4kB pages because of "
1121 "non-cacheable mapping\n");
1122 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1123 #ifdef CONFIG_SPU_BASE
1124 spu_flush_all_slbs(mm);
1129 if (psize != get_paca_psize(ea)) {
1130 get_paca()->context = mm->context;
1131 slb_flush_and_rebolt();
1133 } else if (get_paca()->vmalloc_sllp !=
1134 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1135 get_paca()->vmalloc_sllp =
1136 mmu_psize_defs[mmu_vmalloc_psize].sllp;
1137 slb_vmalloc_update();
1139 #endif /* CONFIG_PPC_64K_PAGES */
1141 #ifdef CONFIG_PPC_HAS_HASH_64K
1142 if (psize == MMU_PAGE_64K)
1143 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1145 #endif /* CONFIG_PPC_HAS_HASH_64K */
1147 int spp = subpage_protection(mm, ea);
1151 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1155 /* Dump some info in case of hash insertion failure, they should
1156 * never happen so it is really useful to know if/when they do
1159 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1160 psize, pte_val(*ptep));
1161 #ifndef CONFIG_PPC_64K_PAGES
1162 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1164 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1165 pte_val(*(ptep + PTRS_PER_PTE)));
1167 DBG_LOW(" -> rc=%d\n", rc);
1170 exception_exit(prev_state);
1173 EXPORT_SYMBOL_GPL(hash_page);
1175 void hash_preload(struct mm_struct *mm, unsigned long ea,
1176 unsigned long access, unsigned long trap)
1182 unsigned long flags;
1183 int rc, ssize, local = 0;
1185 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1187 #ifdef CONFIG_PPC_MM_SLICES
1188 /* We only prefault standard pages for now */
1189 if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
1193 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1194 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1196 /* Get Linux PTE if available */
1202 ssize = user_segment_size(ea);
1203 vsid = get_vsid(mm->context.id, ea, ssize);
1207 * Hash doesn't like irqs. Walking linux page table with irq disabled
1208 * saves us from holding multiple locks.
1210 local_irq_save(flags);
1213 * THP pages use update_mmu_cache_pmd. We don't do
1214 * hash preload there. Hence can ignore THP here
1216 ptep = find_linux_pte_or_hugepte(pgdir, ea, &hugepage_shift);
1220 WARN_ON(hugepage_shift);
1221 #ifdef CONFIG_PPC_64K_PAGES
1222 /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
1223 * a 64K kernel), then we don't preload, hash_page() will take
1224 * care of it once we actually try to access the page.
1225 * That way we don't have to duplicate all of the logic for segment
1226 * page size demotion here
1228 if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
1230 #endif /* CONFIG_PPC_64K_PAGES */
1232 /* Is that local to this CPU ? */
1233 if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1237 #ifdef CONFIG_PPC_HAS_HASH_64K
1238 if (mm->context.user_psize == MMU_PAGE_64K)
1239 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1241 #endif /* CONFIG_PPC_HAS_HASH_64K */
1242 rc = __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
1243 subpage_protection(mm, ea));
1245 /* Dump some info in case of hash insertion failure, they should
1246 * never happen so it is really useful to know if/when they do
1249 hash_failure_debug(ea, access, vsid, trap, ssize,
1250 mm->context.user_psize,
1251 mm->context.user_psize,
1254 local_irq_restore(flags);
1257 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1258 * do not forget to update the assembly call site !
1260 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1263 unsigned long hash, index, shift, hidx, slot;
1265 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1266 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1267 hash = hpt_hash(vpn, shift, ssize);
1268 hidx = __rpte_to_hidx(pte, index);
1269 if (hidx & _PTEIDX_SECONDARY)
1271 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1272 slot += hidx & _PTEIDX_GROUP_IX;
1273 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
1275 * We use same base page size and actual psize, because we don't
1276 * use these functions for hugepage
1278 ppc_md.hpte_invalidate(slot, vpn, psize, psize, ssize, local);
1279 } pte_iterate_hashed_end();
1281 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1282 /* Transactions are not aborted by tlbiel, only tlbie.
1283 * Without, syncing a page back to a block device w/ PIO could pick up
1284 * transactional data (bad!) so we force an abort here. Before the
1285 * sync the page will be made read-only, which will flush_hash_page.
1286 * BIG ISSUE here: if the kernel uses a page from userspace without
1287 * unmapping it first, it may see the speculated version.
1289 if (local && cpu_has_feature(CPU_FTR_TM) &&
1290 current->thread.regs &&
1291 MSR_TM_ACTIVE(current->thread.regs->msr)) {
1293 tm_abort(TM_CAUSE_TLBI);
1298 void flush_hash_range(unsigned long number, int local)
1300 if (ppc_md.flush_hash_range)
1301 ppc_md.flush_hash_range(number, local);
1304 struct ppc64_tlb_batch *batch =
1305 &__get_cpu_var(ppc64_tlb_batch);
1307 for (i = 0; i < number; i++)
1308 flush_hash_page(batch->vpn[i], batch->pte[i],
1309 batch->psize, batch->ssize, local);
1314 * low_hash_fault is called when we the low level hash code failed
1315 * to instert a PTE due to an hypervisor error
1317 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1319 enum ctx_state prev_state = exception_enter();
1321 if (user_mode(regs)) {
1322 #ifdef CONFIG_PPC_SUBPAGE_PROT
1324 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1327 _exception(SIGBUS, regs, BUS_ADRERR, address);
1329 bad_page_fault(regs, address, SIGBUS);
1331 exception_exit(prev_state);
1334 long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1335 unsigned long pa, unsigned long rflags,
1336 unsigned long vflags, int psize, int ssize)
1338 unsigned long hpte_group;
1342 hpte_group = ((hash & htab_hash_mask) *
1343 HPTES_PER_GROUP) & ~0x7UL;
1345 /* Insert into the hash table, primary slot */
1346 slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1347 psize, psize, ssize);
1349 /* Primary is full, try the secondary */
1350 if (unlikely(slot == -1)) {
1351 hpte_group = ((~hash & htab_hash_mask) *
1352 HPTES_PER_GROUP) & ~0x7UL;
1353 slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags,
1354 vflags | HPTE_V_SECONDARY,
1355 psize, psize, ssize);
1358 hpte_group = ((hash & htab_hash_mask) *
1359 HPTES_PER_GROUP)&~0x7UL;
1361 ppc_md.hpte_remove(hpte_group);
1369 #ifdef CONFIG_DEBUG_PAGEALLOC
1370 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1373 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1374 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1375 unsigned long mode = htab_convert_pte_flags(PAGE_KERNEL);
1378 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1380 /* Don't create HPTE entries for bad address */
1384 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1386 mmu_linear_psize, mmu_kernel_ssize);
1389 spin_lock(&linear_map_hash_lock);
1390 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1391 linear_map_hash_slots[lmi] = ret | 0x80;
1392 spin_unlock(&linear_map_hash_lock);
1395 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1397 unsigned long hash, hidx, slot;
1398 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1399 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1401 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1402 spin_lock(&linear_map_hash_lock);
1403 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1404 hidx = linear_map_hash_slots[lmi] & 0x7f;
1405 linear_map_hash_slots[lmi] = 0;
1406 spin_unlock(&linear_map_hash_lock);
1407 if (hidx & _PTEIDX_SECONDARY)
1409 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1410 slot += hidx & _PTEIDX_GROUP_IX;
1411 ppc_md.hpte_invalidate(slot, vpn, mmu_linear_psize, mmu_linear_psize,
1412 mmu_kernel_ssize, 0);
1415 void kernel_map_pages(struct page *page, int numpages, int enable)
1417 unsigned long flags, vaddr, lmi;
1420 local_irq_save(flags);
1421 for (i = 0; i < numpages; i++, page++) {
1422 vaddr = (unsigned long)page_address(page);
1423 lmi = __pa(vaddr) >> PAGE_SHIFT;
1424 if (lmi >= linear_map_hash_count)
1427 kernel_map_linear_page(vaddr, lmi);
1429 kernel_unmap_linear_page(vaddr, lmi);
1431 local_irq_restore(flags);
1433 #endif /* CONFIG_DEBUG_PAGEALLOC */
1435 void setup_initial_memory_limit(phys_addr_t first_memblock_base,
1436 phys_addr_t first_memblock_size)
1438 /* We don't currently support the first MEMBLOCK not mapping 0
1439 * physical on those processors
1441 BUG_ON(first_memblock_base != 0);
1443 /* On LPAR systems, the first entry is our RMA region,
1444 * non-LPAR 64-bit hash MMU systems don't have a limitation
1445 * on real mode access, but using the first entry works well
1446 * enough. We also clamp it to 1G to avoid some funky things
1447 * such as RTAS bugs etc...
1449 ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
1451 /* Finally limit subsequent allocations */
1452 memblock_set_current_limit(ppc64_rma_size);