2 * Low leve TLB miss handlers for Book3E
4 * Copyright (C) 2008-2009
5 * Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
13 #include <asm/processor.h>
17 #include <asm/ppc_asm.h>
18 #include <asm/asm-offsets.h>
19 #include <asm/cputable.h>
20 #include <asm/pgtable.h>
22 #include <asm/exception-64e.h>
23 #include <asm/ppc-opcode.h>
25 #ifdef CONFIG_PPC_64K_PAGES
26 #define VPTE_PMD_SHIFT (PTE_INDEX_SIZE+1)
28 #define VPTE_PMD_SHIFT (PTE_INDEX_SIZE)
30 #define VPTE_PUD_SHIFT (VPTE_PMD_SHIFT + PMD_INDEX_SIZE)
31 #define VPTE_PGD_SHIFT (VPTE_PUD_SHIFT + PUD_INDEX_SIZE)
32 #define VPTE_INDEX_SIZE (VPTE_PGD_SHIFT + PGD_INDEX_SIZE)
35 /**********************************************************************
37 * TLB miss handling for Book3E with TLB reservation and HES support *
39 **********************************************************************/
43 START_EXCEPTION(data_tlb_miss)
46 /* Now we handle the fault proper. We only save DEAR in normal
47 * fault case since that's the only interesting values here.
48 * We could probably also optimize by not saving SRR0/1 in the
49 * linear mapping case but I'll leave that for later
52 mfspr r16,SPRN_DEAR /* get faulting address */
53 srdi r15,r16,60 /* get region */
54 cmpldi cr0,r15,0xc /* linear mapping ? */
55 TLB_MISS_STATS_SAVE_INFO
56 beq tlb_load_linear /* yes -> go to linear map load */
58 /* The page tables are mapped virtually linear. At this point, though,
59 * we don't know whether we are trying to fault in a first level
60 * virtual address or a virtual page table address. We can get that
61 * from bit 0x1 of the region ID which we have set for a page table
64 bne- virt_page_table_tlb_miss
66 std r14,EX_TLB_ESR(r12); /* save ESR */
67 std r16,EX_TLB_DEAR(r12); /* save DEAR */
69 /* We need _PAGE_PRESENT and _PAGE_ACCESSED set */
71 oris r11,r11,_PAGE_ACCESSED@h
73 /* We do the user/kernel test for the PID here along with the RW test
75 cmpldi cr0,r15,0 /* Check for user region */
77 /* We pre-test some combination of permissions to avoid double
80 * We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE
81 * ESR_ST is 0x00800000
82 * _PAGE_BAP_SW is 0x00000010
83 * So the shift is >> 19. This tests for supervisor writeability.
84 * If the page happens to be supervisor writeable and not user
85 * writeable, we will take a new fault later, but that should be
88 * We also move ESR_ST in _PAGE_DIRTY position
89 * _PAGE_DIRTY is 0x00001000 so the shift is >> 11
91 * MAS1 is preset for all we need except for TID that needs to
92 * be cleared for kernel translations
94 rlwimi r11,r14,32-19,27,27
95 rlwimi r11,r14,32-16,19,19
97 /* XXX replace the RMW cycles with immediate loads + writes */
98 1: mfspr r10,SPRN_MAS1
99 cmpldi cr0,r15,8 /* Check for vmalloc region */
100 rlwinm r10,r10,0,16,1 /* Clear TID */
104 /* We got a crappy address, just fault with whatever DEAR and ESR
107 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
108 TLB_MISS_EPILOG_ERROR
109 b exc_data_storage_book3e
111 /* Instruction TLB miss */
112 START_EXCEPTION(instruction_tlb_miss)
115 /* If we take a recursive fault, the second level handler may need
116 * to know whether we are handling a data or instruction fault in
117 * order to get to the right store fault handler. We provide that
118 * info by writing a crazy value in ESR in our exception frame
120 li r14,-1 /* store to exception frame is done later */
122 /* Now we handle the fault proper. We only save DEAR in the non
123 * linear mapping case since we know the linear mapping case will
124 * not re-enter. We could indeed optimize and also not save SRR0/1
125 * in the linear mapping case but I'll leave that for later
127 * Faulting address is SRR0 which is already in r16
129 srdi r15,r16,60 /* get region */
130 cmpldi cr0,r15,0xc /* linear mapping ? */
131 TLB_MISS_STATS_SAVE_INFO
132 beq tlb_load_linear /* yes -> go to linear map load */
134 /* We do the user/kernel test for the PID here along with the RW test
136 li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */
137 oris r11,r11,_PAGE_ACCESSED@h
139 cmpldi cr0,r15,0 /* Check for user region */
140 std r14,EX_TLB_ESR(r12) /* write crazy -1 to frame */
142 /* XXX replace the RMW cycles with immediate loads + writes */
143 1: mfspr r10,SPRN_MAS1
144 cmpldi cr0,r15,8 /* Check for vmalloc region */
145 rlwinm r10,r10,0,16,1 /* Clear TID */
149 /* We got a crappy address, just fault */
150 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
151 TLB_MISS_EPILOG_ERROR
152 b exc_instruction_storage_book3e
155 * This is the guts of the first-level TLB miss handler for direct
156 * misses. We are entered with:
158 * r16 = faulting address
160 * r14 = crap (free to use)
162 * r12 = TLB exception frame in PACA
163 * r11 = PTE permission mask
164 * r10 = crap (free to use)
167 /* So we first construct the page table address. We do that by
168 * shifting the bottom of the address (not the region ID) by
169 * PAGE_SHIFT-3, clearing the bottom 3 bits (get a PTE ptr) and
170 * or'ing the fourth high bit.
172 * NOTE: For 64K pages, we do things slightly differently in
173 * order to handle the weird page table format used by linux
176 #ifdef CONFIG_PPC_64K_PAGES
177 /* For the top bits, 16 bytes per PTE */
178 rldicl r14,r16,64-(PAGE_SHIFT-4),PAGE_SHIFT-4+4
179 /* Now create the bottom bits as 0 in position 0x8000 and
180 * the rest calculated for 8 bytes per PTE
182 rldicl r15,r16,64-(PAGE_SHIFT-3),64-15
183 /* Insert the bottom bits in */
184 rlwimi r14,r15,0,16,31
186 rldicl r14,r16,64-(PAGE_SHIFT-3),PAGE_SHIFT-3+4
192 BEGIN_MMU_FTR_SECTION
193 /* Set the TLB reservation and seach for existing entry. Then load
196 PPC_TLBSRX_DOT(0,r16)
198 beq normal_tlb_miss_done
201 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
203 finish_normal_tlb_miss:
204 /* Check if required permissions are met */
206 bne- normal_tlb_miss_access_fault
208 /* Now we build the MAS:
210 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
211 * MAS 1 : Almost fully setup
212 * - PID already updated by caller if necessary
213 * - TSIZE need change if !base page size, not
214 * yet implemented for now
215 * MAS 2 : Defaults not useful, need to be redone
216 * MAS 3+7 : Needs to be done
218 * TODO: mix up code below for better scheduling
220 clrrdi r11,r16,12 /* Clear low crap in EA */
221 rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */
224 /* Check page size, if not standard, update MAS1 */
225 rldicl r11,r14,64-8,64-8
226 #ifdef CONFIG_PPC_64K_PAGES
227 cmpldi cr0,r11,BOOK3E_PAGESZ_64K
229 cmpldi cr0,r11,BOOK3E_PAGESZ_4K
233 rlwimi r11,r14,31,21,24
234 rlwinm r11,r11,0,21,19
237 /* Move RPN in position */
238 rldicr r11,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT
239 clrldi r15,r11,12 /* Clear crap at the top */
240 rlwimi r15,r14,32-8,22,25 /* Move in U bits */
241 rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */
243 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */
244 andi. r11,r14,_PAGE_DIRTY
246 li r11,MAS3_SW|MAS3_UW
249 BEGIN_MMU_FTR_SECTION
254 mtspr SPRN_MAS7_MAS3,r15
255 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
259 normal_tlb_miss_done:
260 /* We don't bother with restoring DEAR or ESR since we know we are
261 * level 0 and just going back to userland. They are only needed
262 * if you are going to take an access fault
264 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
265 TLB_MISS_EPILOG_SUCCESS
268 normal_tlb_miss_access_fault:
269 /* We need to check if it was an instruction miss */
270 andi. r10,r11,_PAGE_EXEC
272 ld r14,EX_TLB_DEAR(r12)
273 ld r15,EX_TLB_ESR(r12)
276 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
277 TLB_MISS_EPILOG_ERROR
278 b exc_data_storage_book3e
279 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
280 TLB_MISS_EPILOG_ERROR
281 b exc_instruction_storage_book3e
285 * This is the guts of the second-level TLB miss handler for direct
286 * misses. We are entered with:
288 * r16 = virtual page table faulting address
289 * r15 = region (top 4 bits of address)
290 * r14 = crap (free to use)
292 * r12 = TLB exception frame in PACA
293 * r11 = crap (free to use)
294 * r10 = crap (free to use)
296 * Note that this should only ever be called as a second level handler
297 * with the current scheme when using SW load.
298 * That means we can always get the original fault DEAR at
299 * EX_TLB_DEAR-EX_TLB_SIZE(r12)
301 * It can be re-entered by the linear mapping miss handler. However, to
302 * avoid too much complication, it will restart the whole fault at level
303 * 0 so we don't care too much about clobbers
305 * XXX That code was written back when we couldn't clobber r14. We can now,
306 * so we could probably optimize things a bit
308 virt_page_table_tlb_miss:
309 /* Are we hitting a kernel page table ? */
312 /* The cool thing now is that r10 contains 0 for user and 8 for kernel,
313 * and we happen to have the swapper_pg_dir at offset 8 from the user
314 * pgdir in the PACA :-).
318 /* If kernel, we need to clear MAS1 TID */
320 /* XXX replace the RMW cycles with immediate loads + writes */
322 rlwinm r10,r10,0,16,1 /* Clear TID */
325 BEGIN_MMU_FTR_SECTION
326 /* Search if we already have a TLB entry for that virtual address, and
327 * if we do, bail out.
329 PPC_TLBSRX_DOT(0,r16)
330 beq virt_page_table_tlb_miss_done
331 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
333 /* Now, we need to walk the page tables. First check if we are in
336 rldicl. r10,r16,64-(VPTE_INDEX_SIZE+3),VPTE_INDEX_SIZE+3+4
337 bne- virt_page_table_tlb_miss_fault
339 /* Get the PGD pointer */
342 beq- virt_page_table_tlb_miss_fault
344 /* Get to PGD entry */
345 rldicl r11,r16,64-VPTE_PGD_SHIFT,64-PGD_INDEX_SIZE-3
349 beq virt_page_table_tlb_miss_fault
351 #ifndef CONFIG_PPC_64K_PAGES
352 /* Get to PUD entry */
353 rldicl r11,r16,64-VPTE_PUD_SHIFT,64-PUD_INDEX_SIZE-3
357 beq virt_page_table_tlb_miss_fault
358 #endif /* CONFIG_PPC_64K_PAGES */
360 /* Get to PMD entry */
361 rldicl r11,r16,64-VPTE_PMD_SHIFT,64-PMD_INDEX_SIZE-3
365 beq virt_page_table_tlb_miss_fault
367 /* Ok, we're all right, we can now create a kernel translation for
368 * a 4K or 64K page from r16 -> r15.
370 /* Now we build the MAS:
372 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
373 * MAS 1 : Almost fully setup
374 * - PID already updated by caller if necessary
375 * - TSIZE for now is base page size always
376 * MAS 2 : Use defaults
377 * MAS 3+7 : Needs to be done
379 * So we only do MAS 2 and 3 for now...
381 clrldi r11,r15,4 /* remove region ID from RPN */
382 ori r10,r11,1 /* Or-in SR */
384 BEGIN_MMU_FTR_SECTION
389 mtspr SPRN_MAS7_MAS3,r10
390 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
394 BEGIN_MMU_FTR_SECTION
395 virt_page_table_tlb_miss_done:
397 /* We have overriden MAS2:EPN but currently our primary TLB miss
398 * handler will always restore it so that should not be an issue,
399 * if we ever optimize the primary handler to not write MAS2 on
400 * some cases, we'll have to restore MAS2:EPN here based on the
401 * original fault's DEAR. If we do that we have to modify the
402 * ITLB miss handler to also store SRR0 in the exception frame
405 * However, one nasty thing we did is we cleared the reservation
406 * (well, potentially we did). We do a trick here thus if we
407 * are not a level 0 exception (we interrupted the TLB miss) we
408 * offset the return address by -4 in order to replay the tlbsrx
412 cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE
414 ld r11,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13)
416 std r10,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13)
418 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
419 /* Return to caller, normal case */
420 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK);
421 TLB_MISS_EPILOG_SUCCESS
424 virt_page_table_tlb_miss_fault:
425 /* If we fault here, things are a little bit tricky. We need to call
426 * either data or instruction store fault, and we need to retreive
427 * the original fault address and ESR (for data).
429 * The thing is, we know that in normal circumstances, this is
430 * always called as a second level tlb miss for SW load or as a first
431 * level TLB miss for HW load, so we should be able to peek at the
432 * relevant informations in the first exception frame in the PACA.
434 * However, we do need to double check that, because we may just hit
435 * a stray kernel pointer or a userland attack trying to hit those
436 * areas. If that is the case, we do a data fault. (We can't get here
437 * from an instruction tlb miss anyway).
439 * Note also that when going to a fault, we must unwind the previous
440 * level as well. Since we are doing that, we don't need to clear or
441 * restore the TLB reservation neither.
444 cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE
445 bne- virt_page_table_tlb_miss_whacko_fault
447 /* We dig the original DEAR and ESR from slot 0 */
448 ld r15,EX_TLB_DEAR+PACA_EXTLB(r13)
449 ld r16,EX_TLB_ESR+PACA_EXTLB(r13)
451 /* We check for the "special" ESR value for instruction faults */
456 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT);
457 TLB_MISS_EPILOG_ERROR
458 b exc_data_storage_book3e
459 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT);
460 TLB_MISS_EPILOG_ERROR
461 b exc_instruction_storage_book3e
463 virt_page_table_tlb_miss_whacko_fault:
464 /* The linear fault will restart everything so ESR and DEAR will
465 * not have been clobbered, let's just fault with what we have
467 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_FAULT);
468 TLB_MISS_EPILOG_ERROR
469 b exc_data_storage_book3e
472 /**************************************************************
474 * TLB miss handling for Book3E with hw page table support *
476 **************************************************************/
480 START_EXCEPTION(data_tlb_miss_htw)
483 /* Now we handle the fault proper. We only save DEAR in normal
484 * fault case since that's the only interesting values here.
485 * We could probably also optimize by not saving SRR0/1 in the
486 * linear mapping case but I'll leave that for later
489 mfspr r16,SPRN_DEAR /* get faulting address */
490 srdi r11,r16,60 /* get region */
491 cmpldi cr0,r11,0xc /* linear mapping ? */
492 TLB_MISS_STATS_SAVE_INFO
493 beq tlb_load_linear /* yes -> go to linear map load */
495 /* We do the user/kernel test for the PID here along with the RW test
497 cmpldi cr0,r11,0 /* Check for user region */
498 ld r15,PACAPGD(r13) /* Load user pgdir */
501 /* XXX replace the RMW cycles with immediate loads + writes */
502 1: mfspr r10,SPRN_MAS1
503 cmpldi cr0,r11,8 /* Check for vmalloc region */
504 rlwinm r10,r10,0,16,1 /* Clear TID */
506 ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */
509 /* We got a crappy address, just fault with whatever DEAR and ESR
512 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
513 TLB_MISS_EPILOG_ERROR
514 b exc_data_storage_book3e
516 /* Instruction TLB miss */
517 START_EXCEPTION(instruction_tlb_miss_htw)
520 /* If we take a recursive fault, the second level handler may need
521 * to know whether we are handling a data or instruction fault in
522 * order to get to the right store fault handler. We provide that
523 * info by keeping a crazy value for ESR in r14
525 li r14,-1 /* store to exception frame is done later */
527 /* Now we handle the fault proper. We only save DEAR in the non
528 * linear mapping case since we know the linear mapping case will
529 * not re-enter. We could indeed optimize and also not save SRR0/1
530 * in the linear mapping case but I'll leave that for later
532 * Faulting address is SRR0 which is already in r16
534 srdi r11,r16,60 /* get region */
535 cmpldi cr0,r11,0xc /* linear mapping ? */
536 TLB_MISS_STATS_SAVE_INFO
537 beq tlb_load_linear /* yes -> go to linear map load */
539 /* We do the user/kernel test for the PID here along with the RW test
541 cmpldi cr0,r11,0 /* Check for user region */
542 ld r15,PACAPGD(r13) /* Load user pgdir */
545 /* XXX replace the RMW cycles with immediate loads + writes */
546 1: mfspr r10,SPRN_MAS1
547 cmpldi cr0,r11,8 /* Check for vmalloc region */
548 rlwinm r10,r10,0,16,1 /* Clear TID */
550 ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */
553 /* We got a crappy address, just fault */
554 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
555 TLB_MISS_EPILOG_ERROR
556 b exc_instruction_storage_book3e
560 * This is the guts of the second-level TLB miss handler for direct
561 * misses. We are entered with:
563 * r16 = virtual page table faulting address
567 * r12 = TLB exception frame in PACA
568 * r11 = crap (free to use)
569 * r10 = crap (free to use)
571 * It can be re-entered by the linear mapping miss handler. However, to
572 * avoid too much complication, it will save/restore things for us
575 /* Search if we already have a TLB entry for that virtual address, and
576 * if we do, bail out.
578 * MAS1:IND should be already set based on MAS4
580 PPC_TLBSRX_DOT(0,r16)
581 beq htw_tlb_miss_done
583 /* Now, we need to walk the page tables. First check if we are in
586 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
587 bne- htw_tlb_miss_fault
589 /* Get the PGD pointer */
591 beq- htw_tlb_miss_fault
593 /* Get to PGD entry */
594 rldicl r11,r16,64-(PGDIR_SHIFT-3),64-PGD_INDEX_SIZE-3
598 beq htw_tlb_miss_fault
600 #ifndef CONFIG_PPC_64K_PAGES
601 /* Get to PUD entry */
602 rldicl r11,r16,64-(PUD_SHIFT-3),64-PUD_INDEX_SIZE-3
606 beq htw_tlb_miss_fault
607 #endif /* CONFIG_PPC_64K_PAGES */
609 /* Get to PMD entry */
610 rldicl r11,r16,64-(PMD_SHIFT-3),64-PMD_INDEX_SIZE-3
614 beq htw_tlb_miss_fault
616 /* Ok, we're all right, we can now create an indirect entry for
619 * The last trick is now that because we use "half" pages for
620 * the HTW (1M IND is 2K and 256M IND is 32K) we need to account
621 * for an added LSB bit to the RPN. For 64K pages, there is no
622 * problem as we already use 32K arrays (half PTE pages), but for
623 * 4K page we need to extract a bit from the virtual address and
624 * insert it into the "PA52" bit of the RPN.
626 #ifndef CONFIG_PPC_64K_PAGES
627 rlwimi r15,r16,32-9,20,20
629 /* Now we build the MAS:
631 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
632 * MAS 1 : Almost fully setup
633 * - PID already updated by caller if necessary
634 * - TSIZE for now is base ind page size always
635 * MAS 2 : Use defaults
636 * MAS 3+7 : Needs to be done
638 #ifdef CONFIG_PPC_64K_PAGES
639 ori r10,r15,(BOOK3E_PAGESZ_64K << MAS3_SPSIZE_SHIFT)
641 ori r10,r15,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT)
644 BEGIN_MMU_FTR_SECTION
649 mtspr SPRN_MAS7_MAS3,r10
650 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
655 /* We don't bother with restoring DEAR or ESR since we know we are
656 * level 0 and just going back to userland. They are only needed
657 * if you are going to take an access fault
659 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK)
660 TLB_MISS_EPILOG_SUCCESS
664 /* We need to check if it was an instruction miss. We know this
665 * though because r14 would contain -1
671 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT)
672 TLB_MISS_EPILOG_ERROR
673 b exc_data_storage_book3e
674 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT)
675 TLB_MISS_EPILOG_ERROR
676 b exc_instruction_storage_book3e
679 * This is the guts of "any" level TLB miss handler for kernel linear
680 * mapping misses. We are entered with:
683 * r16 = faulting address
684 * r15 = crap (free to use)
685 * r14 = ESR (data) or -1 (instruction)
687 * r12 = TLB exception frame in PACA
688 * r11 = crap (free to use)
689 * r10 = crap (free to use)
691 * In addition we know that we will not re-enter, so in theory, we could
692 * use a simpler epilog not restoring SRR0/1 etc.. but we'll do that later.
694 * We also need to be careful about MAS registers here & TLB reservation,
695 * as we know we'll have clobbered them if we interrupt the main TLB miss
696 * handlers in which case we probably want to do a full restart at level
697 * 0 rather than saving / restoring the MAS.
699 * Note: If we care about performance of that core, we can easily shuffle
700 * a few things around
703 /* For now, we assume the linear mapping is contiguous and stops at
704 * linear_map_top. We also assume the size is a multiple of 1G, thus
705 * we only use 1G pages for now. That might have to be changed in a
706 * final implementation, especially when dealing with hypervisors
709 ld r11,linear_map_top@got(r11)
712 bge tlb_load_linear_fault
714 /* MAS1 need whole new setup. */
715 li r15,(BOOK3E_PAGESZ_1GB<<MAS1_TSIZE_SHIFT)
716 oris r15,r15,MAS1_VALID@h /* MAS1 needs V and TSIZE */
719 /* Already somebody there ? */
720 PPC_TLBSRX_DOT(0,r16)
721 beq tlb_load_linear_done
723 /* Now we build the remaining MAS. MAS0 and 2 should be fine
724 * with their defaults, which leaves us with MAS 3 and 7. The
725 * mapping is linear, so we just take the address, clear the
726 * region bits, and or in the permission bits which are currently
729 clrrdi r10,r16,30 /* 1G page index */
730 clrldi r10,r10,4 /* clear region bits */
731 ori r10,r10,MAS3_SR|MAS3_SW|MAS3_SX
733 BEGIN_MMU_FTR_SECTION
738 mtspr SPRN_MAS7_MAS3,r10
739 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
743 tlb_load_linear_done:
744 /* We use the "error" epilog for success as we do want to
745 * restore to the initial faulting context, whatever it was.
746 * We do that because we can't resume a fault within a TLB
747 * miss handler, due to MAS and TLB reservation being clobbered.
749 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_LINEAR)
750 TLB_MISS_EPILOG_ERROR
753 tlb_load_linear_fault:
754 /* We keep the DEAR and ESR around, this shouldn't have happened */
757 TLB_MISS_EPILOG_ERROR_SPECIAL
758 b exc_data_storage_book3e
759 1: TLB_MISS_EPILOG_ERROR_SPECIAL
760 b exc_instruction_storage_book3e
763 #ifdef CONFIG_BOOK3E_MMU_TLB_STATS