2 * This file contains the routines for TLB flushing.
3 * On machines where the MMU does not use a hash table to store virtual to
4 * physical translations (ie, SW loaded TLBs or Book3E compilant processors,
5 * this does -not- include 603 however which shares the implementation with
6 * hash based processors)
10 * Copyright 2008,2009 Ben Herrenschmidt <benh@kernel.crashing.org>
13 * Derived from arch/ppc/mm/init.c:
14 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
16 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
17 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
18 * Copyright (C) 1996 Paul Mackerras
20 * Derived from "arch/i386/mm/init.c"
21 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version
26 * 2 of the License, or (at your option) any later version.
30 #include <linux/kernel.h>
32 #include <linux/init.h>
33 #include <linux/highmem.h>
34 #include <linux/pagemap.h>
35 #include <linux/preempt.h>
36 #include <linux/spinlock.h>
37 #include <linux/memblock.h>
38 #include <linux/of_fdt.h>
40 #include <asm/tlbflush.h>
42 #include <asm/code-patching.h>
46 #ifdef CONFIG_PPC_BOOK3E
47 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
51 .enc = BOOK3E_PAGESZ_4K,
55 .enc = BOOK3E_PAGESZ_16K,
60 .enc = BOOK3E_PAGESZ_64K,
64 .enc = BOOK3E_PAGESZ_1M,
69 .enc = BOOK3E_PAGESZ_16M,
73 .enc = BOOK3E_PAGESZ_256M,
77 .enc = BOOK3E_PAGESZ_1GB,
80 static inline int mmu_get_tsize(int psize)
82 return mmu_psize_defs[psize].enc;
85 static inline int mmu_get_tsize(int psize)
87 /* This isn't used on !Book3E for now */
92 /* The variables below are currently only used on 64-bit Book3E
93 * though this will probably be made common with other nohash
94 * implementations at some point
98 int mmu_linear_psize; /* Page size used for the linear mapping */
99 int mmu_pte_psize; /* Page size used for PTE pages */
100 int mmu_vmemmap_psize; /* Page size used for the virtual mem map */
101 int book3e_htw_enabled; /* Is HW tablewalk enabled ? */
102 unsigned long linear_map_top; /* Top of linear mapping */
104 #endif /* CONFIG_PPC64 */
106 #ifdef CONFIG_PPC_FSL_BOOK3E
107 /* next_tlbcam_idx is used to round-robin tlbcam entry assignment */
108 DEFINE_PER_CPU(int, next_tlbcam_idx);
109 EXPORT_PER_CPU_SYMBOL(next_tlbcam_idx);
113 * Base TLB flushing operations:
115 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
116 * - flush_tlb_page(vma, vmaddr) flushes one page
117 * - flush_tlb_range(vma, start, end) flushes a range of pages
118 * - flush_tlb_kernel_range(start, end) flushes kernel pages
120 * - local_* variants of page and mm only apply to the current
125 * These are the base non-SMP variants of page and mm flushing
127 void local_flush_tlb_mm(struct mm_struct *mm)
132 pid = mm->context.id;
133 if (pid != MMU_NO_CONTEXT)
137 EXPORT_SYMBOL(local_flush_tlb_mm);
139 void __local_flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
145 pid = mm ? mm->context.id : 0;
146 if (pid != MMU_NO_CONTEXT)
147 _tlbil_va(vmaddr, pid, tsize, ind);
151 void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
153 __local_flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
154 mmu_get_tsize(mmu_virtual_psize), 0);
156 EXPORT_SYMBOL(local_flush_tlb_page);
159 * And here are the SMP non-local implementations
163 static DEFINE_RAW_SPINLOCK(tlbivax_lock);
165 static int mm_is_core_local(struct mm_struct *mm)
167 return cpumask_subset(mm_cpumask(mm),
168 topology_thread_cpumask(smp_processor_id()));
171 struct tlb_flush_param {
178 static void do_flush_tlb_mm_ipi(void *param)
180 struct tlb_flush_param *p = param;
182 _tlbil_pid(p ? p->pid : 0);
185 static void do_flush_tlb_page_ipi(void *param)
187 struct tlb_flush_param *p = param;
189 _tlbil_va(p->addr, p->pid, p->tsize, p->ind);
193 /* Note on invalidations and PID:
195 * We snapshot the PID with preempt disabled. At this point, it can still
196 * change either because:
197 * - our context is being stolen (PID -> NO_CONTEXT) on another CPU
198 * - we are invaliating some target that isn't currently running here
199 * and is concurrently acquiring a new PID on another CPU
200 * - some other CPU is re-acquiring a lost PID for this mm
203 * However, this shouldn't be a problem as we only guarantee
204 * invalidation of TLB entries present prior to this call, so we
205 * don't care about the PID changing, and invalidating a stale PID
206 * is generally harmless.
209 void flush_tlb_mm(struct mm_struct *mm)
214 pid = mm->context.id;
215 if (unlikely(pid == MMU_NO_CONTEXT))
217 if (!mm_is_core_local(mm)) {
218 struct tlb_flush_param p = { .pid = pid };
219 /* Ignores smp_processor_id() even if set. */
220 smp_call_function_many(mm_cpumask(mm),
221 do_flush_tlb_mm_ipi, &p, 1);
227 EXPORT_SYMBOL(flush_tlb_mm);
229 void __flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
232 struct cpumask *cpu_mask;
236 pid = mm ? mm->context.id : 0;
237 if (unlikely(pid == MMU_NO_CONTEXT))
239 cpu_mask = mm_cpumask(mm);
240 if (!mm_is_core_local(mm)) {
241 /* If broadcast tlbivax is supported, use it */
242 if (mmu_has_feature(MMU_FTR_USE_TLBIVAX_BCAST)) {
243 int lock = mmu_has_feature(MMU_FTR_LOCK_BCAST_INVAL);
245 raw_spin_lock(&tlbivax_lock);
246 _tlbivax_bcast(vmaddr, pid, tsize, ind);
248 raw_spin_unlock(&tlbivax_lock);
251 struct tlb_flush_param p = {
257 /* Ignores smp_processor_id() even if set in cpu_mask */
258 smp_call_function_many(cpu_mask,
259 do_flush_tlb_page_ipi, &p, 1);
262 _tlbil_va(vmaddr, pid, tsize, ind);
267 void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
269 __flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
270 mmu_get_tsize(mmu_virtual_psize), 0);
272 EXPORT_SYMBOL(flush_tlb_page);
274 #endif /* CONFIG_SMP */
276 #ifdef CONFIG_PPC_47x
277 void __init early_init_mmu_47x(void)
280 unsigned long root = of_get_flat_dt_root();
281 if (of_get_flat_dt_prop(root, "cooperative-partition", NULL))
282 mmu_clear_feature(MMU_FTR_USE_TLBIVAX_BCAST);
283 #endif /* CONFIG_SMP */
285 #endif /* CONFIG_PPC_47x */
288 * Flush kernel TLB entries in the given range
290 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
294 smp_call_function(do_flush_tlb_mm_ipi, NULL, 1);
301 EXPORT_SYMBOL(flush_tlb_kernel_range);
304 * Currently, for range flushing, we just do a full mm flush. This should
305 * be optimized based on a threshold on the size of the range, since
306 * some implementation can stack multiple tlbivax before a tlbsync but
307 * for now, we keep it that way
309 void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
313 flush_tlb_mm(vma->vm_mm);
315 EXPORT_SYMBOL(flush_tlb_range);
317 void tlb_flush(struct mmu_gather *tlb)
319 flush_tlb_mm(tlb->mm);
323 * Below are functions specific to the 64-bit variant of Book3E though that
324 * may change in the future
330 * Handling of virtual linear page tables or indirect TLB entries
331 * flushing when PTE pages are freed
333 void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address)
335 int tsize = mmu_psize_defs[mmu_pte_psize].enc;
337 if (book3e_htw_enabled) {
338 unsigned long start = address & PMD_MASK;
339 unsigned long end = address + PMD_SIZE;
340 unsigned long size = 1UL << mmu_psize_defs[mmu_pte_psize].shift;
342 /* This isn't the most optimal, ideally we would factor out the
343 * while preempt & CPU mask mucking around, or even the IPI but
346 while (start < end) {
347 __flush_tlb_page(tlb->mm, start, tsize, 1);
351 unsigned long rmask = 0xf000000000000000ul;
352 unsigned long rid = (address & rmask) | 0x1000000000000000ul;
353 unsigned long vpte = address & ~rmask;
355 #ifdef CONFIG_PPC_64K_PAGES
356 vpte = (vpte >> (PAGE_SHIFT - 4)) & ~0xfffful;
358 vpte = (vpte >> (PAGE_SHIFT - 3)) & ~0xffful;
361 __flush_tlb_page(tlb->mm, vpte, tsize, 0);
365 static void setup_page_sizes(void)
367 unsigned int tlb0cfg;
372 #ifdef CONFIG_PPC_FSL_BOOK3E
373 unsigned int mmucfg = mfspr(SPRN_MMUCFG);
375 if (((mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) &&
376 (mmu_has_feature(MMU_FTR_TYPE_FSL_E))) {
377 unsigned int tlb1cfg = mfspr(SPRN_TLB1CFG);
378 unsigned int min_pg, max_pg;
380 min_pg = (tlb1cfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
381 max_pg = (tlb1cfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
383 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
384 struct mmu_psize_def *def;
387 def = &mmu_psize_defs[psize];
393 /* adjust to be in terms of 4^shift Kb */
394 shift = (shift - 10) >> 1;
396 if ((shift >= min_pg) && (shift <= max_pg))
397 def->flags |= MMU_PAGE_SIZE_DIRECT;
404 tlb0cfg = mfspr(SPRN_TLB0CFG);
405 tlb0ps = mfspr(SPRN_TLB0PS);
406 eptcfg = mfspr(SPRN_EPTCFG);
408 /* Look for supported direct sizes */
409 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
410 struct mmu_psize_def *def = &mmu_psize_defs[psize];
412 if (tlb0ps & (1U << (def->shift - 10)))
413 def->flags |= MMU_PAGE_SIZE_DIRECT;
416 /* Indirect page sizes supported ? */
417 if ((tlb0cfg & TLBnCFG_IND) == 0)
420 /* Now, we only deal with one IND page size for each
421 * direct size. Hopefully all implementations today are
422 * unambiguous, but we might want to be careful in the
425 for (i = 0; i < 3; i++) {
426 unsigned int ps, sps;
434 for (psize = 0; psize < MMU_PAGE_COUNT; psize++) {
435 struct mmu_psize_def *def = &mmu_psize_defs[psize];
437 if (ps == (def->shift - 10))
438 def->flags |= MMU_PAGE_SIZE_INDIRECT;
439 if (sps == (def->shift - 10))
445 /* Cleanup array and print summary */
446 pr_info("MMU: Supported page sizes\n");
447 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
448 struct mmu_psize_def *def = &mmu_psize_defs[psize];
449 const char *__page_type_names[] = {
455 if (def->flags == 0) {
459 pr_info(" %8ld KB as %s\n", 1ul << (def->shift - 10),
460 __page_type_names[def->flags & 0x3]);
464 static void __patch_exception(int exc, unsigned long addr)
466 extern unsigned int interrupt_base_book3e;
467 unsigned int *ibase = &interrupt_base_book3e;
469 /* Our exceptions vectors start with a NOP and -then- a branch
470 * to deal with single stepping from userspace which stops on
471 * the second instruction. Thus we need to patch the second
472 * instruction of the exception, not the first one
475 patch_branch(ibase + (exc / 4) + 1, addr, 0);
478 #define patch_exception(exc, name) do { \
479 extern unsigned int name; \
480 __patch_exception((exc), (unsigned long)&name); \
483 static void setup_mmu_htw(void)
485 /* Check if HW tablewalk is present, and if yes, enable it by:
487 * - patching the TLB miss handlers to branch to the
488 * one dedicates to it
490 * - setting the global book3e_htw_enabled
492 unsigned int tlb0cfg = mfspr(SPRN_TLB0CFG);
494 if ((tlb0cfg & TLBnCFG_IND) &&
495 (tlb0cfg & TLBnCFG_PT)) {
496 patch_exception(0x1c0, exc_data_tlb_miss_htw_book3e);
497 patch_exception(0x1e0, exc_instruction_tlb_miss_htw_book3e);
498 book3e_htw_enabled = 1;
500 pr_info("MMU: Book3E HW tablewalk %s\n",
501 book3e_htw_enabled ? "enabled" : "not supported");
505 * Early initialization of the MMU TLB code
507 static void __early_init_mmu(int boot_cpu)
511 /* XXX This will have to be decided at runtime, but right
512 * now our boot and TLB miss code hard wires it. Ideally
513 * we should find out a suitable page size and patch the
514 * TLB miss code (either that or use the PACA to store
517 mmu_linear_psize = MMU_PAGE_1G;
519 /* XXX This should be decided at runtime based on supported
520 * page sizes in the TLB, but for now let's assume 16M is
521 * always there and a good fit (which it probably is)
523 mmu_vmemmap_psize = MMU_PAGE_16M;
525 /* XXX This code only checks for TLB 0 capabilities and doesn't
526 * check what page size combos are supported by the HW. It
527 * also doesn't handle the case where a separate array holds
528 * the IND entries from the array loaded by the PT.
531 /* Look for supported page sizes */
534 /* Look for HW tablewalk support */
538 /* Set MAS4 based on page table setting */
540 mas4 = 0x4 << MAS4_WIMGED_SHIFT;
541 if (book3e_htw_enabled) {
542 mas4 |= mas4 | MAS4_INDD;
543 #ifdef CONFIG_PPC_64K_PAGES
544 mas4 |= BOOK3E_PAGESZ_256M << MAS4_TSIZED_SHIFT;
545 mmu_pte_psize = MMU_PAGE_256M;
547 mas4 |= BOOK3E_PAGESZ_1M << MAS4_TSIZED_SHIFT;
548 mmu_pte_psize = MMU_PAGE_1M;
551 #ifdef CONFIG_PPC_64K_PAGES
552 mas4 |= BOOK3E_PAGESZ_64K << MAS4_TSIZED_SHIFT;
554 mas4 |= BOOK3E_PAGESZ_4K << MAS4_TSIZED_SHIFT;
556 mmu_pte_psize = mmu_virtual_psize;
558 mtspr(SPRN_MAS4, mas4);
560 /* Set the global containing the top of the linear mapping
561 * for use by the TLB miss code
563 linear_map_top = memblock_end_of_DRAM();
565 #ifdef CONFIG_PPC_FSL_BOOK3E
566 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
567 unsigned int num_cams;
569 /* use a quarter of the TLBCAM for bolted linear map */
570 num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4;
571 linear_map_top = map_mem_in_cams(linear_map_top, num_cams);
573 /* limit memory so we dont have linear faults */
574 memblock_enforce_memory_limit(linear_map_top);
577 patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
578 patch_exception(0x1e0, exc_instruction_tlb_miss_bolted_book3e);
582 /* A sync won't hurt us after mucking around with
583 * the MMU configuration
587 memblock_set_current_limit(linear_map_top);
590 void __init early_init_mmu(void)
595 void __cpuinit early_init_mmu_secondary(void)
600 void setup_initial_memory_limit(phys_addr_t first_memblock_base,
601 phys_addr_t first_memblock_size)
603 /* On Embedded 64-bit, we adjust the RMA size to match
604 * the bolted TLB entry. We know for now that only 1G
605 * entries are supported though that may eventually
606 * change. We crop it to the size of the first MEMBLOCK to
607 * avoid going over total available memory just in case...
609 ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
611 /* Finally limit subsequent allocations */
612 memblock_set_current_limit(first_memblock_base + ppc64_rma_size);
614 #else /* ! CONFIG_PPC64 */
615 void __init early_init_mmu(void)
617 #ifdef CONFIG_PPC_47x
618 early_init_mmu_47x();
621 #endif /* CONFIG_PPC64 */