2 * This file contains the routines for TLB flushing.
3 * On machines where the MMU does not use a hash table to store virtual to
4 * physical translations (ie, SW loaded TLBs or Book3E compilant processors,
5 * this does -not- include 603 however which shares the implementation with
6 * hash based processors)
10 * Copyright 2008,2009 Ben Herrenschmidt <benh@kernel.crashing.org>
13 * Derived from arch/ppc/mm/init.c:
14 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
16 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
17 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
18 * Copyright (C) 1996 Paul Mackerras
20 * Derived from "arch/i386/mm/init.c"
21 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version
26 * 2 of the License, or (at your option) any later version.
30 #include <linux/kernel.h>
32 #include <linux/init.h>
33 #include <linux/highmem.h>
34 #include <linux/pagemap.h>
35 #include <linux/preempt.h>
36 #include <linux/spinlock.h>
37 #include <linux/memblock.h>
39 #include <asm/tlbflush.h>
41 #include <asm/code-patching.h>
45 #ifdef CONFIG_PPC_BOOK3E
46 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
50 .enc = BOOK3E_PAGESZ_4K,
54 .enc = BOOK3E_PAGESZ_16K,
59 .enc = BOOK3E_PAGESZ_64K,
63 .enc = BOOK3E_PAGESZ_1M,
68 .enc = BOOK3E_PAGESZ_16M,
72 .enc = BOOK3E_PAGESZ_256M,
76 .enc = BOOK3E_PAGESZ_1GB,
79 static inline int mmu_get_tsize(int psize)
81 return mmu_psize_defs[psize].enc;
84 static inline int mmu_get_tsize(int psize)
86 /* This isn't used on !Book3E for now */
91 /* The variables below are currently only used on 64-bit Book3E
92 * though this will probably be made common with other nohash
93 * implementations at some point
97 int mmu_linear_psize; /* Page size used for the linear mapping */
98 int mmu_pte_psize; /* Page size used for PTE pages */
99 int mmu_vmemmap_psize; /* Page size used for the virtual mem map */
100 int book3e_htw_enabled; /* Is HW tablewalk enabled ? */
101 unsigned long linear_map_top; /* Top of linear mapping */
103 #endif /* CONFIG_PPC64 */
106 * Base TLB flushing operations:
108 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
109 * - flush_tlb_page(vma, vmaddr) flushes one page
110 * - flush_tlb_range(vma, start, end) flushes a range of pages
111 * - flush_tlb_kernel_range(start, end) flushes kernel pages
113 * - local_* variants of page and mm only apply to the current
118 * These are the base non-SMP variants of page and mm flushing
120 void local_flush_tlb_mm(struct mm_struct *mm)
125 pid = mm->context.id;
126 if (pid != MMU_NO_CONTEXT)
130 EXPORT_SYMBOL(local_flush_tlb_mm);
132 void __local_flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
138 pid = mm ? mm->context.id : 0;
139 if (pid != MMU_NO_CONTEXT)
140 _tlbil_va(vmaddr, pid, tsize, ind);
144 void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
146 __local_flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
147 mmu_get_tsize(mmu_virtual_psize), 0);
149 EXPORT_SYMBOL(local_flush_tlb_page);
152 * And here are the SMP non-local implementations
156 static DEFINE_RAW_SPINLOCK(tlbivax_lock);
158 static int mm_is_core_local(struct mm_struct *mm)
160 return cpumask_subset(mm_cpumask(mm),
161 topology_thread_cpumask(smp_processor_id()));
164 struct tlb_flush_param {
171 static void do_flush_tlb_mm_ipi(void *param)
173 struct tlb_flush_param *p = param;
175 _tlbil_pid(p ? p->pid : 0);
178 static void do_flush_tlb_page_ipi(void *param)
180 struct tlb_flush_param *p = param;
182 _tlbil_va(p->addr, p->pid, p->tsize, p->ind);
186 /* Note on invalidations and PID:
188 * We snapshot the PID with preempt disabled. At this point, it can still
189 * change either because:
190 * - our context is being stolen (PID -> NO_CONTEXT) on another CPU
191 * - we are invaliating some target that isn't currently running here
192 * and is concurrently acquiring a new PID on another CPU
193 * - some other CPU is re-acquiring a lost PID for this mm
196 * However, this shouldn't be a problem as we only guarantee
197 * invalidation of TLB entries present prior to this call, so we
198 * don't care about the PID changing, and invalidating a stale PID
199 * is generally harmless.
202 void flush_tlb_mm(struct mm_struct *mm)
207 pid = mm->context.id;
208 if (unlikely(pid == MMU_NO_CONTEXT))
210 if (!mm_is_core_local(mm)) {
211 struct tlb_flush_param p = { .pid = pid };
212 /* Ignores smp_processor_id() even if set. */
213 smp_call_function_many(mm_cpumask(mm),
214 do_flush_tlb_mm_ipi, &p, 1);
220 EXPORT_SYMBOL(flush_tlb_mm);
222 void __flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
225 struct cpumask *cpu_mask;
229 pid = mm ? mm->context.id : 0;
230 if (unlikely(pid == MMU_NO_CONTEXT))
232 cpu_mask = mm_cpumask(mm);
233 if (!mm_is_core_local(mm)) {
234 /* If broadcast tlbivax is supported, use it */
235 if (mmu_has_feature(MMU_FTR_USE_TLBIVAX_BCAST)) {
236 int lock = mmu_has_feature(MMU_FTR_LOCK_BCAST_INVAL);
238 raw_spin_lock(&tlbivax_lock);
239 _tlbivax_bcast(vmaddr, pid, tsize, ind);
241 raw_spin_unlock(&tlbivax_lock);
244 struct tlb_flush_param p = {
250 /* Ignores smp_processor_id() even if set in cpu_mask */
251 smp_call_function_many(cpu_mask,
252 do_flush_tlb_page_ipi, &p, 1);
255 _tlbil_va(vmaddr, pid, tsize, ind);
260 void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
262 __flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
263 mmu_get_tsize(mmu_virtual_psize), 0);
265 EXPORT_SYMBOL(flush_tlb_page);
267 #endif /* CONFIG_SMP */
270 * Flush kernel TLB entries in the given range
272 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
276 smp_call_function(do_flush_tlb_mm_ipi, NULL, 1);
283 EXPORT_SYMBOL(flush_tlb_kernel_range);
286 * Currently, for range flushing, we just do a full mm flush. This should
287 * be optimized based on a threshold on the size of the range, since
288 * some implementation can stack multiple tlbivax before a tlbsync but
289 * for now, we keep it that way
291 void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
295 flush_tlb_mm(vma->vm_mm);
297 EXPORT_SYMBOL(flush_tlb_range);
299 void tlb_flush(struct mmu_gather *tlb)
301 flush_tlb_mm(tlb->mm);
303 /* Push out batch of freed page tables */
308 * Below are functions specific to the 64-bit variant of Book3E though that
309 * may change in the future
315 * Handling of virtual linear page tables or indirect TLB entries
316 * flushing when PTE pages are freed
318 void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address)
320 int tsize = mmu_psize_defs[mmu_pte_psize].enc;
322 if (book3e_htw_enabled) {
323 unsigned long start = address & PMD_MASK;
324 unsigned long end = address + PMD_SIZE;
325 unsigned long size = 1UL << mmu_psize_defs[mmu_pte_psize].shift;
327 /* This isn't the most optimal, ideally we would factor out the
328 * while preempt & CPU mask mucking around, or even the IPI but
331 while (start < end) {
332 __flush_tlb_page(tlb->mm, start, tsize, 1);
336 unsigned long rmask = 0xf000000000000000ul;
337 unsigned long rid = (address & rmask) | 0x1000000000000000ul;
338 unsigned long vpte = address & ~rmask;
340 #ifdef CONFIG_PPC_64K_PAGES
341 vpte = (vpte >> (PAGE_SHIFT - 4)) & ~0xfffful;
343 vpte = (vpte >> (PAGE_SHIFT - 3)) & ~0xffful;
346 __flush_tlb_page(tlb->mm, vpte, tsize, 0);
350 static void setup_page_sizes(void)
352 unsigned int tlb0cfg = mfspr(SPRN_TLB0CFG);
353 unsigned int tlb0ps = mfspr(SPRN_TLB0PS);
354 unsigned int eptcfg = mfspr(SPRN_EPTCFG);
357 /* Look for supported direct sizes */
358 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
359 struct mmu_psize_def *def = &mmu_psize_defs[psize];
361 if (tlb0ps & (1U << (def->shift - 10)))
362 def->flags |= MMU_PAGE_SIZE_DIRECT;
365 /* Indirect page sizes supported ? */
366 if ((tlb0cfg & TLBnCFG_IND) == 0)
369 /* Now, we only deal with one IND page size for each
370 * direct size. Hopefully all implementations today are
371 * unambiguous, but we might want to be careful in the
374 for (i = 0; i < 3; i++) {
375 unsigned int ps, sps;
383 for (psize = 0; psize < MMU_PAGE_COUNT; psize++) {
384 struct mmu_psize_def *def = &mmu_psize_defs[psize];
386 if (ps == (def->shift - 10))
387 def->flags |= MMU_PAGE_SIZE_INDIRECT;
388 if (sps == (def->shift - 10))
394 /* Cleanup array and print summary */
395 pr_info("MMU: Supported page sizes\n");
396 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
397 struct mmu_psize_def *def = &mmu_psize_defs[psize];
398 const char *__page_type_names[] = {
404 if (def->flags == 0) {
408 pr_info(" %8ld KB as %s\n", 1ul << (def->shift - 10),
409 __page_type_names[def->flags & 0x3]);
413 static void setup_mmu_htw(void)
415 extern unsigned int interrupt_base_book3e;
416 extern unsigned int exc_data_tlb_miss_htw_book3e;
417 extern unsigned int exc_instruction_tlb_miss_htw_book3e;
419 unsigned int *ibase = &interrupt_base_book3e;
421 /* Check if HW tablewalk is present, and if yes, enable it by:
423 * - patching the TLB miss handlers to branch to the
424 * one dedicates to it
426 * - setting the global book3e_htw_enabled
428 unsigned int tlb0cfg = mfspr(SPRN_TLB0CFG);
430 if ((tlb0cfg & TLBnCFG_IND) &&
431 (tlb0cfg & TLBnCFG_PT)) {
432 /* Our exceptions vectors start with a NOP and -then- a branch
433 * to deal with single stepping from userspace which stops on
434 * the second instruction. Thus we need to patch the second
435 * instruction of the exception, not the first one
437 patch_branch(ibase + (0x1c0 / 4) + 1,
438 (unsigned long)&exc_data_tlb_miss_htw_book3e, 0);
439 patch_branch(ibase + (0x1e0 / 4) + 1,
440 (unsigned long)&exc_instruction_tlb_miss_htw_book3e, 0);
441 book3e_htw_enabled = 1;
443 pr_info("MMU: Book3E Page Tables %s\n",
444 book3e_htw_enabled ? "Enabled" : "Disabled");
448 * Early initialization of the MMU TLB code
450 static void __early_init_mmu(int boot_cpu)
454 /* XXX This will have to be decided at runtime, but right
455 * now our boot and TLB miss code hard wires it. Ideally
456 * we should find out a suitable page size and patch the
457 * TLB miss code (either that or use the PACA to store
460 mmu_linear_psize = MMU_PAGE_1G;
462 /* XXX This should be decided at runtime based on supported
463 * page sizes in the TLB, but for now let's assume 16M is
464 * always there and a good fit (which it probably is)
466 mmu_vmemmap_psize = MMU_PAGE_16M;
468 /* XXX This code only checks for TLB 0 capabilities and doesn't
469 * check what page size combos are supported by the HW. It
470 * also doesn't handle the case where a separate array holds
471 * the IND entries from the array loaded by the PT.
474 /* Look for supported page sizes */
477 /* Look for HW tablewalk support */
481 /* Set MAS4 based on page table setting */
483 mas4 = 0x4 << MAS4_WIMGED_SHIFT;
484 if (book3e_htw_enabled) {
485 mas4 |= mas4 | MAS4_INDD;
486 #ifdef CONFIG_PPC_64K_PAGES
487 mas4 |= BOOK3E_PAGESZ_256M << MAS4_TSIZED_SHIFT;
488 mmu_pte_psize = MMU_PAGE_256M;
490 mas4 |= BOOK3E_PAGESZ_1M << MAS4_TSIZED_SHIFT;
491 mmu_pte_psize = MMU_PAGE_1M;
494 #ifdef CONFIG_PPC_64K_PAGES
495 mas4 |= BOOK3E_PAGESZ_64K << MAS4_TSIZED_SHIFT;
497 mas4 |= BOOK3E_PAGESZ_4K << MAS4_TSIZED_SHIFT;
499 mmu_pte_psize = mmu_virtual_psize;
501 mtspr(SPRN_MAS4, mas4);
503 /* Set the global containing the top of the linear mapping
504 * for use by the TLB miss code
506 linear_map_top = memblock_end_of_DRAM();
508 /* A sync won't hurt us after mucking around with
509 * the MMU configuration
514 void __init early_init_mmu(void)
519 void __cpuinit early_init_mmu_secondary(void)
524 #endif /* CONFIG_PPC64 */