2 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 #include <linux/oprofile.h>
11 #include <linux/smp.h>
12 #include <asm/ptrace.h>
13 #include <asm/processor.h>
14 #include <asm/cputable.h>
15 #include <asm/oprofile_impl.h>
19 static void ctrl_write(unsigned int i, unsigned int val)
22 unsigned long shift = 0, mask = 0;
24 dbg("ctrl_write %d %x\n", i, val);
28 tmp = mfspr(SPRN_MMCR0);
33 tmp = mfspr(SPRN_MMCR0);
38 tmp = mfspr(SPRN_MMCR1);
43 tmp = mfspr(SPRN_MMCR1);
48 tmp = mfspr(SPRN_MMCR1);
53 tmp = mfspr(SPRN_MMCR1);
58 tmp = mfspr(SPRN_MMCR1);
63 tmp = mfspr(SPRN_MMCR1);
69 tmp = tmp & ~(mask << shift);
75 mtspr(SPRN_MMCR0, tmp);
78 mtspr(SPRN_MMCR1, tmp);
81 dbg("ctrl_write mmcr0 %lx mmcr1 %lx\n", mfspr(SPRN_MMCR0),
85 static unsigned long reset_value[OP_MAX_COUNTER];
87 static int num_counters;
89 static int rs64_reg_setup(struct op_counter_config *ctr,
90 struct op_system_config *sys,
95 num_counters = num_ctrs;
97 for (i = 0; i < num_counters; ++i)
98 reset_value[i] = 0x80000000UL - ctr[i].count;
100 /* XXX setup user and kernel profiling */
104 static int rs64_cpu_setup(struct op_counter_config *ctr)
108 /* reset MMCR0 and set the freeze bit */
110 mtspr(SPRN_MMCR0, mmcr0);
112 /* reset MMCR1, MMCRA */
113 mtspr(SPRN_MMCR1, 0);
115 if (cpu_has_feature(CPU_FTR_MMCRA))
116 mtspr(SPRN_MMCRA, 0);
118 mmcr0 |= MMCR0_FCM1|MMCR0_PMXE|MMCR0_FCECE;
119 /* Only applies to POWER3, but should be safe on RS64 */
120 mmcr0 |= MMCR0_PMC1CE|MMCR0_PMCjCE;
121 mtspr(SPRN_MMCR0, mmcr0);
123 dbg("setup on cpu %d, mmcr0 %lx\n", smp_processor_id(),
125 dbg("setup on cpu %d, mmcr1 %lx\n", smp_processor_id(),
131 static int rs64_start(struct op_counter_config *ctr)
136 /* set the PMM bit (see comment below) */
137 mtmsrd(mfmsr() | MSR_PMM);
139 for (i = 0; i < num_counters; ++i) {
140 if (ctr[i].enabled) {
141 classic_ctr_write(i, reset_value[i]);
142 ctrl_write(i, ctr[i].event);
144 classic_ctr_write(i, 0);
148 mmcr0 = mfspr(SPRN_MMCR0);
151 * now clear the freeze bit, counting will not start until we
152 * rfid from this excetion, because only at that point will
153 * the PMM bit be cleared
156 mtspr(SPRN_MMCR0, mmcr0);
158 dbg("start on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
162 static void rs64_stop(void)
166 /* freeze counters */
167 mmcr0 = mfspr(SPRN_MMCR0);
169 mtspr(SPRN_MMCR0, mmcr0);
171 dbg("stop on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
176 static void rs64_handle_interrupt(struct pt_regs *regs,
177 struct op_counter_config *ctr)
183 unsigned long pc = mfspr(SPRN_SIAR);
185 is_kernel = is_kernel_addr(pc);
187 /* set the PMM bit (see comment below) */
188 mtmsrd(mfmsr() | MSR_PMM);
190 for (i = 0; i < num_counters; ++i) {
191 val = classic_ctr_read(i);
193 if (ctr[i].enabled) {
194 oprofile_add_ext_sample(pc, regs, i, is_kernel);
195 classic_ctr_write(i, reset_value[i]);
197 classic_ctr_write(i, 0);
202 mmcr0 = mfspr(SPRN_MMCR0);
204 /* reset the perfmon trigger */
208 * now clear the freeze bit, counting will not start until we
209 * rfid from this exception, because only at that point will
210 * the PMM bit be cleared
213 mtspr(SPRN_MMCR0, mmcr0);
216 struct op_powerpc_model op_model_rs64 = {
217 .reg_setup = rs64_reg_setup,
218 .cpu_setup = rs64_cpu_setup,
221 .handle_interrupt = rs64_handle_interrupt,