2 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 #include <linux/oprofile.h>
11 #include <linux/init.h>
12 #include <linux/smp.h>
13 #include <asm/ptrace.h>
14 #include <asm/processor.h>
15 #include <asm/cputable.h>
16 #include <asm/oprofile_impl.h>
20 static void ctrl_write(unsigned int i, unsigned int val)
23 unsigned long shift = 0, mask = 0;
25 dbg("ctrl_write %d %x\n", i, val);
29 tmp = mfspr(SPRN_MMCR0);
34 tmp = mfspr(SPRN_MMCR0);
39 tmp = mfspr(SPRN_MMCR1);
44 tmp = mfspr(SPRN_MMCR1);
49 tmp = mfspr(SPRN_MMCR1);
54 tmp = mfspr(SPRN_MMCR1);
59 tmp = mfspr(SPRN_MMCR1);
64 tmp = mfspr(SPRN_MMCR1);
70 tmp = tmp & ~(mask << shift);
76 mtspr(SPRN_MMCR0, tmp);
79 mtspr(SPRN_MMCR1, tmp);
82 dbg("ctrl_write mmcr0 %lx mmcr1 %lx\n", mfspr(SPRN_MMCR0),
86 static unsigned long reset_value[OP_MAX_COUNTER];
88 static int num_counters;
90 static int rs64_reg_setup(struct op_counter_config *ctr,
91 struct op_system_config *sys,
96 num_counters = num_ctrs;
98 for (i = 0; i < num_counters; ++i)
99 reset_value[i] = 0x80000000UL - ctr[i].count;
101 /* XXX setup user and kernel profiling */
105 static int rs64_cpu_setup(struct op_counter_config *ctr)
109 /* reset MMCR0 and set the freeze bit */
111 mtspr(SPRN_MMCR0, mmcr0);
113 /* reset MMCR1, MMCRA */
114 mtspr(SPRN_MMCR1, 0);
116 if (cpu_has_feature(CPU_FTR_MMCRA))
117 mtspr(SPRN_MMCRA, 0);
119 mmcr0 |= MMCR0_FCM1|MMCR0_PMXE|MMCR0_FCECE;
120 /* Only applies to POWER3, but should be safe on RS64 */
121 mmcr0 |= MMCR0_PMC1CE|MMCR0_PMCjCE;
122 mtspr(SPRN_MMCR0, mmcr0);
124 dbg("setup on cpu %d, mmcr0 %lx\n", smp_processor_id(),
126 dbg("setup on cpu %d, mmcr1 %lx\n", smp_processor_id(),
132 static int rs64_start(struct op_counter_config *ctr)
137 /* set the PMM bit (see comment below) */
138 mtmsrd(mfmsr() | MSR_PMM);
140 for (i = 0; i < num_counters; ++i) {
141 if (ctr[i].enabled) {
142 classic_ctr_write(i, reset_value[i]);
143 ctrl_write(i, ctr[i].event);
145 classic_ctr_write(i, 0);
149 mmcr0 = mfspr(SPRN_MMCR0);
152 * now clear the freeze bit, counting will not start until we
153 * rfid from this excetion, because only at that point will
154 * the PMM bit be cleared
157 mtspr(SPRN_MMCR0, mmcr0);
159 dbg("start on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
163 static void rs64_stop(void)
167 /* freeze counters */
168 mmcr0 = mfspr(SPRN_MMCR0);
170 mtspr(SPRN_MMCR0, mmcr0);
172 dbg("stop on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
177 static void rs64_handle_interrupt(struct pt_regs *regs,
178 struct op_counter_config *ctr)
184 unsigned long pc = mfspr(SPRN_SIAR);
186 is_kernel = is_kernel_addr(pc);
188 /* set the PMM bit (see comment below) */
189 mtmsrd(mfmsr() | MSR_PMM);
191 for (i = 0; i < num_counters; ++i) {
192 val = classic_ctr_read(i);
194 if (ctr[i].enabled) {
195 oprofile_add_ext_sample(pc, regs, i, is_kernel);
196 classic_ctr_write(i, reset_value[i]);
198 classic_ctr_write(i, 0);
203 mmcr0 = mfspr(SPRN_MMCR0);
205 /* reset the perfmon trigger */
209 * now clear the freeze bit, counting will not start until we
210 * rfid from this exception, because only at that point will
211 * the PMM bit be cleared
214 mtspr(SPRN_MMCR0, mmcr0);
217 struct op_powerpc_model op_model_rs64 = {
218 .reg_setup = rs64_reg_setup,
219 .cpu_setup = rs64_cpu_setup,
222 .handle_interrupt = rs64_handle_interrupt,