2 * Performance event support - powerpc architecture code
4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 #include <linux/kernel.h>
12 #include <linux/sched.h>
13 #include <linux/perf_event.h>
14 #include <linux/percpu.h>
15 #include <linux/hardirq.h>
16 #include <linux/uaccess.h>
19 #include <asm/machdep.h>
20 #include <asm/firmware.h>
21 #include <asm/ptrace.h>
22 #include <asm/code-patching.h>
24 #define BHRB_MAX_ENTRIES 32
25 #define BHRB_TARGET 0x0000000000000002
26 #define BHRB_PREDICTION 0x0000000000000001
27 #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL
29 struct cpu_hw_events {
36 struct perf_event *event[MAX_HWEVENTS];
37 u64 events[MAX_HWEVENTS];
38 unsigned int flags[MAX_HWEVENTS];
40 * The order of the MMCR array is:
41 * - 64-bit, MMCR0, MMCR1, MMCRA, MMCR2
42 * - 32-bit, MMCR0, MMCR1, MMCR2
44 unsigned long mmcr[4];
45 struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS];
46 u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS];
47 u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
48 unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
49 unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
51 unsigned int txn_flags;
55 u64 bhrb_filter; /* BHRB HW branch filter */
56 unsigned int bhrb_users;
58 struct perf_branch_stack bhrb_stack;
59 struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES];
63 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
65 static struct power_pmu *ppmu;
68 * Normally, to ignore kernel events we set the FCS (freeze counters
69 * in supervisor mode) bit in MMCR0, but if the kernel runs with the
70 * hypervisor bit set in the MSR, or if we are running on a processor
71 * where the hypervisor bit is forced to 1 (as on Apple G5 processors),
72 * then we need to use the FCHV bit to ignore kernel events.
74 static unsigned int freeze_events_kernel = MMCR0_FCS;
77 * 32-bit doesn't have MMCRA but does have an MMCR2,
78 * and a few other names are different.
83 #define MMCR0_PMCjCE MMCR0_PMCnCE
89 #define MMCR0_PMCC_U6 0
91 #define SPRN_MMCRA SPRN_MMCR2
92 #define MMCRA_SAMPLE_ENABLE 0
94 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
98 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { }
99 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
103 static inline void perf_read_regs(struct pt_regs *regs)
107 static inline int perf_intr_is_nmi(struct pt_regs *regs)
112 static inline int siar_valid(struct pt_regs *regs)
117 static bool is_ebb_event(struct perf_event *event) { return false; }
118 static int ebb_event_check(struct perf_event *event) { return 0; }
119 static void ebb_event_add(struct perf_event *event) { }
120 static void ebb_switch_out(unsigned long mmcr0) { }
121 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)
123 return cpuhw->mmcr[0];
126 static inline void power_pmu_bhrb_enable(struct perf_event *event) {}
127 static inline void power_pmu_bhrb_disable(struct perf_event *event) {}
128 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {}
129 static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {}
130 static void pmao_restore_workaround(bool ebb) { }
131 static bool use_ic(u64 event)
135 #endif /* CONFIG_PPC32 */
137 static bool regs_use_siar(struct pt_regs *regs)
140 * When we take a performance monitor exception the regs are setup
141 * using perf_read_regs() which overloads some fields, in particular
142 * regs->result to tell us whether to use SIAR.
144 * However if the regs are from another exception, eg. a syscall, then
145 * they have not been setup using perf_read_regs() and so regs->result
146 * is something random.
148 return ((TRAP(regs) == 0xf00) && regs->result);
152 * Things that are specific to 64-bit implementations.
156 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
158 unsigned long mmcra = regs->dsisr;
160 if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) {
161 unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT;
163 return 4 * (slot - 1);
170 * The user wants a data address recorded.
171 * If we're not doing instruction sampling, give them the SDAR
172 * (sampled data address). If we are doing instruction sampling, then
173 * only give them the SDAR if it corresponds to the instruction
174 * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the
175 * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER.
177 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp)
179 unsigned long mmcra = regs->dsisr;
182 if (ppmu->flags & PPMU_HAS_SIER)
183 sdar_valid = regs->dar & SIER_SDAR_VALID;
185 unsigned long sdsync;
187 if (ppmu->flags & PPMU_SIAR_VALID)
188 sdsync = POWER7P_MMCRA_SDAR_VALID;
189 else if (ppmu->flags & PPMU_ALT_SIPR)
190 sdsync = POWER6_MMCRA_SDSYNC;
192 sdsync = MMCRA_SDSYNC;
194 sdar_valid = mmcra & sdsync;
197 if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid)
198 *addrp = mfspr(SPRN_SDAR);
201 static bool regs_sihv(struct pt_regs *regs)
203 unsigned long sihv = MMCRA_SIHV;
205 if (ppmu->flags & PPMU_HAS_SIER)
206 return !!(regs->dar & SIER_SIHV);
208 if (ppmu->flags & PPMU_ALT_SIPR)
209 sihv = POWER6_MMCRA_SIHV;
211 return !!(regs->dsisr & sihv);
214 static bool regs_sipr(struct pt_regs *regs)
216 unsigned long sipr = MMCRA_SIPR;
218 if (ppmu->flags & PPMU_HAS_SIER)
219 return !!(regs->dar & SIER_SIPR);
221 if (ppmu->flags & PPMU_ALT_SIPR)
222 sipr = POWER6_MMCRA_SIPR;
224 return !!(regs->dsisr & sipr);
227 static inline u32 perf_flags_from_msr(struct pt_regs *regs)
229 if (regs->msr & MSR_PR)
230 return PERF_RECORD_MISC_USER;
231 if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV)
232 return PERF_RECORD_MISC_HYPERVISOR;
233 return PERF_RECORD_MISC_KERNEL;
236 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
238 bool use_siar = regs_use_siar(regs);
241 return perf_flags_from_msr(regs);
244 * If we don't have flags in MMCRA, rather than using
245 * the MSR, we intuit the flags from the address in
246 * SIAR which should give slightly more reliable
249 if (ppmu->flags & PPMU_NO_SIPR) {
250 unsigned long siar = mfspr(SPRN_SIAR);
251 if (is_kernel_addr(siar))
252 return PERF_RECORD_MISC_KERNEL;
253 return PERF_RECORD_MISC_USER;
256 /* PR has priority over HV, so order below is important */
258 return PERF_RECORD_MISC_USER;
260 if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV))
261 return PERF_RECORD_MISC_HYPERVISOR;
263 return PERF_RECORD_MISC_KERNEL;
267 * Overload regs->dsisr to store MMCRA so we only need to read it once
269 * Overload regs->dar to store SIER if we have it.
270 * Overload regs->result to specify whether we should use the MSR (result
271 * is zero) or the SIAR (result is non zero).
273 static inline void perf_read_regs(struct pt_regs *regs)
275 unsigned long mmcra = mfspr(SPRN_MMCRA);
276 int marked = mmcra & MMCRA_SAMPLE_ENABLE;
281 if (ppmu->flags & PPMU_HAS_SIER)
282 regs->dar = mfspr(SPRN_SIER);
285 * If this isn't a PMU exception (eg a software event) the SIAR is
286 * not valid. Use pt_regs.
288 * If it is a marked event use the SIAR.
290 * If the PMU doesn't update the SIAR for non marked events use
293 * If the PMU has HV/PR flags then check to see if they
294 * place the exception in userspace. If so, use pt_regs. In
295 * continuous sampling mode the SIAR and the PMU exception are
296 * not synchronised, so they may be many instructions apart.
297 * This can result in confusing backtraces. We still want
298 * hypervisor samples as well as samples in the kernel with
299 * interrupts off hence the userspace check.
301 if (TRAP(regs) != 0xf00)
303 else if ((ppmu->flags & PPMU_NO_SIAR))
307 else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING))
309 else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs))
314 regs->result = use_siar;
318 * If interrupts were soft-disabled when a PMU interrupt occurs, treat
321 static inline int perf_intr_is_nmi(struct pt_regs *regs)
327 * On processors like P7+ that have the SIAR-Valid bit, marked instructions
328 * must be sampled only if the SIAR-valid bit is set.
330 * For unmarked instructions and for processors that don't have the SIAR-Valid
331 * bit, assume that SIAR is valid.
333 static inline int siar_valid(struct pt_regs *regs)
335 unsigned long mmcra = regs->dsisr;
336 int marked = mmcra & MMCRA_SAMPLE_ENABLE;
339 if (ppmu->flags & PPMU_HAS_SIER)
340 return regs->dar & SIER_SIAR_VALID;
342 if (ppmu->flags & PPMU_SIAR_VALID)
343 return mmcra & POWER7P_MMCRA_SIAR_VALID;
350 /* Reset all possible BHRB entries */
351 static void power_pmu_bhrb_reset(void)
353 asm volatile(PPC_CLRBHRB);
356 static void power_pmu_bhrb_enable(struct perf_event *event)
358 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
363 /* Clear BHRB if we changed task context to avoid data leaks */
364 if (event->ctx->task && cpuhw->bhrb_context != event->ctx) {
365 power_pmu_bhrb_reset();
366 cpuhw->bhrb_context = event->ctx;
369 perf_sched_cb_inc(event->ctx->pmu);
372 static void power_pmu_bhrb_disable(struct perf_event *event)
374 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
379 WARN_ON_ONCE(!cpuhw->bhrb_users);
381 perf_sched_cb_dec(event->ctx->pmu);
383 if (!cpuhw->disabled && !cpuhw->bhrb_users) {
384 /* BHRB cannot be turned off when other
385 * events are active on the PMU.
388 /* avoid stale pointer */
389 cpuhw->bhrb_context = NULL;
393 /* Called from ctxsw to prevent one process's branch entries to
394 * mingle with the other process's entries during context switch.
396 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
402 power_pmu_bhrb_reset();
404 /* Calculate the to address for a branch */
405 static __u64 power_pmu_bhrb_to(u64 addr)
411 if (is_kernel_addr(addr))
412 return branch_target((unsigned int *)addr);
414 /* Userspace: need copy instruction here then translate it */
416 ret = __get_user_inatomic(instr, (unsigned int __user *)addr);
423 target = branch_target(&instr);
424 if ((!target) || (instr & BRANCH_ABSOLUTE))
427 /* Translate relative branch target from kernel to user address */
428 return target - (unsigned long)&instr + addr;
431 /* Processing BHRB entries */
432 static void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw)
436 int r_index, u_index, pred;
440 while (r_index < ppmu->bhrb_nr) {
441 /* Assembly read function */
442 val = read_bhrb(r_index++);
444 /* Terminal marker: End of valid BHRB entries */
447 addr = val & BHRB_EA;
448 pred = val & BHRB_PREDICTION;
454 /* Branches are read most recent first (ie. mfbhrb 0 is
455 * the most recent branch).
456 * There are two types of valid entries:
457 * 1) a target entry which is the to address of a
458 * computed goto like a blr,bctr,btar. The next
459 * entry read from the bhrb will be branch
460 * corresponding to this target (ie. the actual
461 * blr/bctr/btar instruction).
462 * 2) a from address which is an actual branch. If a
463 * target entry proceeds this, then this is the
464 * matching branch for that target. If this is not
465 * following a target entry, then this is a branch
466 * where the target is given as an immediate field
467 * in the instruction (ie. an i or b form branch).
468 * In this case we need to read the instruction from
469 * memory to determine the target/to address.
472 if (val & BHRB_TARGET) {
473 /* Target branches use two entries
474 * (ie. computed gotos/XL form)
476 cpuhw->bhrb_entries[u_index].to = addr;
477 cpuhw->bhrb_entries[u_index].mispred = pred;
478 cpuhw->bhrb_entries[u_index].predicted = ~pred;
480 /* Get from address in next entry */
481 val = read_bhrb(r_index++);
482 addr = val & BHRB_EA;
483 if (val & BHRB_TARGET) {
484 /* Shouldn't have two targets in a
485 row.. Reset index and try again */
489 cpuhw->bhrb_entries[u_index].from = addr;
491 /* Branches to immediate field
493 cpuhw->bhrb_entries[u_index].from = addr;
494 cpuhw->bhrb_entries[u_index].to =
495 power_pmu_bhrb_to(addr);
496 cpuhw->bhrb_entries[u_index].mispred = pred;
497 cpuhw->bhrb_entries[u_index].predicted = ~pred;
503 cpuhw->bhrb_stack.nr = u_index;
507 static bool is_ebb_event(struct perf_event *event)
510 * This could be a per-PMU callback, but we'd rather avoid the cost. We
511 * check that the PMU supports EBB, meaning those that don't can still
512 * use bit 63 of the event code for something else if they wish.
514 return (ppmu->flags & PPMU_ARCH_207S) &&
515 ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1);
518 static int ebb_event_check(struct perf_event *event)
520 struct perf_event *leader = event->group_leader;
522 /* Event and group leader must agree on EBB */
523 if (is_ebb_event(leader) != is_ebb_event(event))
526 if (is_ebb_event(event)) {
527 if (!(event->attach_state & PERF_ATTACH_TASK))
530 if (!leader->attr.pinned || !leader->attr.exclusive)
533 if (event->attr.freq ||
534 event->attr.inherit ||
535 event->attr.sample_type ||
536 event->attr.sample_period ||
537 event->attr.enable_on_exec)
544 static void ebb_event_add(struct perf_event *event)
546 if (!is_ebb_event(event) || current->thread.used_ebb)
550 * IFF this is the first time we've added an EBB event, set
551 * PMXE in the user MMCR0 so we can detect when it's cleared by
552 * userspace. We need this so that we can context switch while
553 * userspace is in the EBB handler (where PMXE is 0).
555 current->thread.used_ebb = 1;
556 current->thread.mmcr0 |= MMCR0_PMXE;
559 static void ebb_switch_out(unsigned long mmcr0)
561 if (!(mmcr0 & MMCR0_EBE))
564 current->thread.siar = mfspr(SPRN_SIAR);
565 current->thread.sier = mfspr(SPRN_SIER);
566 current->thread.sdar = mfspr(SPRN_SDAR);
567 current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK;
568 current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK;
571 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)
573 unsigned long mmcr0 = cpuhw->mmcr[0];
578 /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */
579 mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6;
582 * Add any bits from the user MMCR0, FC or PMAO. This is compatible
583 * with pmao_restore_workaround() because we may add PMAO but we never
586 mmcr0 |= current->thread.mmcr0;
589 * Be careful not to set PMXE if userspace had it cleared. This is also
590 * compatible with pmao_restore_workaround() because it has already
591 * cleared PMXE and we leave PMAO alone.
593 if (!(current->thread.mmcr0 & MMCR0_PMXE))
594 mmcr0 &= ~MMCR0_PMXE;
596 mtspr(SPRN_SIAR, current->thread.siar);
597 mtspr(SPRN_SIER, current->thread.sier);
598 mtspr(SPRN_SDAR, current->thread.sdar);
601 * Merge the kernel & user values of MMCR2. The semantics we implement
602 * are that the user MMCR2 can set bits, ie. cause counters to freeze,
603 * but not clear bits. If a task wants to be able to clear bits, ie.
604 * unfreeze counters, it should not set exclude_xxx in its events and
605 * instead manage the MMCR2 entirely by itself.
607 mtspr(SPRN_MMCR2, cpuhw->mmcr[3] | current->thread.mmcr2);
612 static void pmao_restore_workaround(bool ebb)
616 if (!cpu_has_feature(CPU_FTR_PMAO_BUG))
620 * On POWER8E there is a hardware defect which affects the PMU context
621 * switch logic, ie. power_pmu_disable/enable().
623 * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0
624 * by the hardware. Sometime later the actual PMU exception is
627 * If we context switch, or simply disable/enable, the PMU prior to the
628 * exception arriving, the exception will be lost when we clear PMAO.
630 * When we reenable the PMU, we will write the saved MMCR0 with PMAO
631 * set, and this _should_ generate an exception. However because of the
632 * defect no exception is generated when we write PMAO, and we get
633 * stuck with no counters counting but no exception delivered.
635 * The workaround is to detect this case and tweak the hardware to
636 * create another pending PMU exception.
638 * We do that by setting up PMC6 (cycles) for an imminent overflow and
639 * enabling the PMU. That causes a new exception to be generated in the
640 * chip, but we don't take it yet because we have interrupts hard
641 * disabled. We then write back the PMU state as we want it to be seen
642 * by the exception handler. When we reenable interrupts the exception
643 * handler will be called and see the correct state.
645 * The logic is the same for EBB, except that the exception is gated by
646 * us having interrupts hard disabled as well as the fact that we are
647 * not in userspace. The exception is finally delivered when we return
651 /* Only if PMAO is set and PMAO_SYNC is clear */
652 if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO)
655 /* If we're doing EBB, only if BESCR[GE] is set */
656 if (ebb && !(current->thread.bescr & BESCR_GE))
660 * We are already soft-disabled in power_pmu_enable(). We need to hard
661 * disable to actually prevent the PMU exception from firing.
666 * This is a bit gross, but we know we're on POWER8E and have 6 PMCs.
667 * Using read/write_pmc() in a for loop adds 12 function calls and
668 * almost doubles our code size.
670 pmcs[0] = mfspr(SPRN_PMC1);
671 pmcs[1] = mfspr(SPRN_PMC2);
672 pmcs[2] = mfspr(SPRN_PMC3);
673 pmcs[3] = mfspr(SPRN_PMC4);
674 pmcs[4] = mfspr(SPRN_PMC5);
675 pmcs[5] = mfspr(SPRN_PMC6);
677 /* Ensure all freeze bits are unset */
678 mtspr(SPRN_MMCR2, 0);
680 /* Set up PMC6 to overflow in one cycle */
681 mtspr(SPRN_PMC6, 0x7FFFFFFE);
683 /* Enable exceptions and unfreeze PMC6 */
684 mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO);
686 /* Now we need to refreeze and restore the PMCs */
687 mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO);
689 mtspr(SPRN_PMC1, pmcs[0]);
690 mtspr(SPRN_PMC2, pmcs[1]);
691 mtspr(SPRN_PMC3, pmcs[2]);
692 mtspr(SPRN_PMC4, pmcs[3]);
693 mtspr(SPRN_PMC5, pmcs[4]);
694 mtspr(SPRN_PMC6, pmcs[5]);
697 static bool use_ic(u64 event)
699 if (cpu_has_feature(CPU_FTR_POWER9_DD1) &&
700 (event == 0x200f2 || event == 0x300f2))
705 #endif /* CONFIG_PPC64 */
707 static void perf_event_interrupt(struct pt_regs *regs);
710 * Read one performance monitor counter (PMC).
712 static unsigned long read_pmc(int idx)
718 val = mfspr(SPRN_PMC1);
721 val = mfspr(SPRN_PMC2);
724 val = mfspr(SPRN_PMC3);
727 val = mfspr(SPRN_PMC4);
730 val = mfspr(SPRN_PMC5);
733 val = mfspr(SPRN_PMC6);
737 val = mfspr(SPRN_PMC7);
740 val = mfspr(SPRN_PMC8);
742 #endif /* CONFIG_PPC64 */
744 printk(KERN_ERR "oops trying to read PMC%d\n", idx);
753 static void write_pmc(int idx, unsigned long val)
757 mtspr(SPRN_PMC1, val);
760 mtspr(SPRN_PMC2, val);
763 mtspr(SPRN_PMC3, val);
766 mtspr(SPRN_PMC4, val);
769 mtspr(SPRN_PMC5, val);
772 mtspr(SPRN_PMC6, val);
776 mtspr(SPRN_PMC7, val);
779 mtspr(SPRN_PMC8, val);
781 #endif /* CONFIG_PPC64 */
783 printk(KERN_ERR "oops trying to write PMC%d\n", idx);
787 /* Called from sysrq_handle_showregs() */
788 void perf_event_print_debug(void)
790 unsigned long sdar, sier, flags;
791 u32 pmcs[MAX_HWEVENTS];
794 if (!ppmu->n_counter)
797 local_irq_save(flags);
799 pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d",
800 smp_processor_id(), ppmu->name, ppmu->n_counter);
802 for (i = 0; i < ppmu->n_counter; i++)
803 pmcs[i] = read_pmc(i + 1);
805 for (; i < MAX_HWEVENTS; i++)
806 pmcs[i] = 0xdeadbeef;
808 pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n",
809 pmcs[0], pmcs[1], pmcs[2], pmcs[3]);
811 if (ppmu->n_counter > 4)
812 pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n",
813 pmcs[4], pmcs[5], pmcs[6], pmcs[7]);
815 pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n",
816 mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA));
820 sdar = mfspr(SPRN_SDAR);
822 if (ppmu->flags & PPMU_HAS_SIER)
823 sier = mfspr(SPRN_SIER);
825 if (ppmu->flags & PPMU_ARCH_207S) {
826 pr_info("MMCR2: %016lx EBBHR: %016lx\n",
827 mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR));
828 pr_info("EBBRR: %016lx BESCR: %016lx\n",
829 mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR));
832 pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n",
833 mfspr(SPRN_SIAR), sdar, sier);
835 local_irq_restore(flags);
839 * Check if a set of events can all go on the PMU at once.
840 * If they can't, this will look at alternative codes for the events
841 * and see if any combination of alternative codes is feasible.
842 * The feasible set is returned in event_id[].
844 static int power_check_constraints(struct cpu_hw_events *cpuhw,
845 u64 event_id[], unsigned int cflags[],
848 unsigned long mask, value, nv;
849 unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS];
850 int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS];
852 unsigned long addf = ppmu->add_fields;
853 unsigned long tadd = ppmu->test_adder;
855 if (n_ev > ppmu->n_counter)
858 /* First see if the events will go on as-is */
859 for (i = 0; i < n_ev; ++i) {
860 if ((cflags[i] & PPMU_LIMITED_PMC_REQD)
861 && !ppmu->limited_pmc_event(event_id[i])) {
862 ppmu->get_alternatives(event_id[i], cflags[i],
863 cpuhw->alternatives[i]);
864 event_id[i] = cpuhw->alternatives[i][0];
866 if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0],
867 &cpuhw->avalues[i][0]))
871 for (i = 0; i < n_ev; ++i) {
872 nv = (value | cpuhw->avalues[i][0]) +
873 (value & cpuhw->avalues[i][0] & addf);
874 if ((((nv + tadd) ^ value) & mask) != 0 ||
875 (((nv + tadd) ^ cpuhw->avalues[i][0]) &
876 cpuhw->amasks[i][0]) != 0)
879 mask |= cpuhw->amasks[i][0];
882 return 0; /* all OK */
884 /* doesn't work, gather alternatives... */
885 if (!ppmu->get_alternatives)
887 for (i = 0; i < n_ev; ++i) {
889 n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i],
890 cpuhw->alternatives[i]);
891 for (j = 1; j < n_alt[i]; ++j)
892 ppmu->get_constraint(cpuhw->alternatives[i][j],
893 &cpuhw->amasks[i][j],
894 &cpuhw->avalues[i][j]);
897 /* enumerate all possibilities and see if any will work */
900 value = mask = nv = 0;
903 /* we're backtracking, restore context */
909 * See if any alternative k for event_id i,
910 * where k > j, will satisfy the constraints.
912 while (++j < n_alt[i]) {
913 nv = (value | cpuhw->avalues[i][j]) +
914 (value & cpuhw->avalues[i][j] & addf);
915 if ((((nv + tadd) ^ value) & mask) == 0 &&
916 (((nv + tadd) ^ cpuhw->avalues[i][j])
917 & cpuhw->amasks[i][j]) == 0)
922 * No feasible alternative, backtrack
923 * to event_id i-1 and continue enumerating its
924 * alternatives from where we got up to.
930 * Found a feasible alternative for event_id i,
931 * remember where we got up to with this event_id,
932 * go on to the next event_id, and start with
933 * the first alternative for it.
939 mask |= cpuhw->amasks[i][j];
945 /* OK, we have a feasible combination, tell the caller the solution */
946 for (i = 0; i < n_ev; ++i)
947 event_id[i] = cpuhw->alternatives[i][choice[i]];
952 * Check if newly-added events have consistent settings for
953 * exclude_{user,kernel,hv} with each other and any previously
956 static int check_excludes(struct perf_event **ctrs, unsigned int cflags[],
957 int n_prev, int n_new)
959 int eu = 0, ek = 0, eh = 0;
961 struct perf_event *event;
964 * If the PMU we're on supports per event exclude settings then we
965 * don't need to do any of this logic. NB. This assumes no PMU has both
966 * per event exclude and limited PMCs.
968 if (ppmu->flags & PPMU_ARCH_207S)
976 for (i = 0; i < n; ++i) {
977 if (cflags[i] & PPMU_LIMITED_PMC_OK) {
978 cflags[i] &= ~PPMU_LIMITED_PMC_REQD;
983 eu = event->attr.exclude_user;
984 ek = event->attr.exclude_kernel;
985 eh = event->attr.exclude_hv;
987 } else if (event->attr.exclude_user != eu ||
988 event->attr.exclude_kernel != ek ||
989 event->attr.exclude_hv != eh) {
995 for (i = 0; i < n; ++i)
996 if (cflags[i] & PPMU_LIMITED_PMC_OK)
997 cflags[i] |= PPMU_LIMITED_PMC_REQD;
1002 static u64 check_and_compute_delta(u64 prev, u64 val)
1004 u64 delta = (val - prev) & 0xfffffffful;
1007 * POWER7 can roll back counter values, if the new value is smaller
1008 * than the previous value it will cause the delta and the counter to
1009 * have bogus values unless we rolled a counter over. If a coutner is
1010 * rolled back, it will be smaller, but within 256, which is the maximum
1011 * number of events to rollback at once. If we detect a rollback
1012 * return 0. This can lead to a small lack of precision in the
1015 if (prev > val && (prev - val) < 256)
1021 static void power_pmu_read(struct perf_event *event)
1023 s64 val, delta, prev;
1024 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1026 if (event->hw.state & PERF_HES_STOPPED)
1032 if (is_ebb_event(event)) {
1033 val = read_pmc(event->hw.idx);
1034 if (use_ic(event->attr.config)) {
1035 val = mfspr(SPRN_IC);
1036 if (val > cpuhw->ic_init)
1037 val = val - cpuhw->ic_init;
1039 val = val + (0 - cpuhw->ic_init);
1041 local64_set(&event->hw.prev_count, val);
1046 * Performance monitor interrupts come even when interrupts
1047 * are soft-disabled, as long as interrupts are hard-enabled.
1048 * Therefore we treat them like NMIs.
1051 prev = local64_read(&event->hw.prev_count);
1053 val = read_pmc(event->hw.idx);
1054 if (use_ic(event->attr.config)) {
1055 val = mfspr(SPRN_IC);
1056 if (val > cpuhw->ic_init)
1057 val = val - cpuhw->ic_init;
1059 val = val + (0 - cpuhw->ic_init);
1061 delta = check_and_compute_delta(prev, val);
1064 } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
1066 local64_add(delta, &event->count);
1069 * A number of places program the PMC with (0x80000000 - period_left).
1070 * We never want period_left to be less than 1 because we will program
1071 * the PMC with a value >= 0x800000000 and an edge detected PMC will
1072 * roll around to 0 before taking an exception. We have seen this
1075 * To fix this, clamp the minimum value of period_left to 1.
1078 prev = local64_read(&event->hw.period_left);
1082 } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev);
1086 * On some machines, PMC5 and PMC6 can't be written, don't respect
1087 * the freeze conditions, and don't generate interrupts. This tells
1088 * us if `event' is using such a PMC.
1090 static int is_limited_pmc(int pmcnum)
1092 return (ppmu->flags & PPMU_LIMITED_PMC5_6)
1093 && (pmcnum == 5 || pmcnum == 6);
1096 static void freeze_limited_counters(struct cpu_hw_events *cpuhw,
1097 unsigned long pmc5, unsigned long pmc6)
1099 struct perf_event *event;
1100 u64 val, prev, delta;
1103 for (i = 0; i < cpuhw->n_limited; ++i) {
1104 event = cpuhw->limited_counter[i];
1107 val = (event->hw.idx == 5) ? pmc5 : pmc6;
1108 prev = local64_read(&event->hw.prev_count);
1110 delta = check_and_compute_delta(prev, val);
1112 local64_add(delta, &event->count);
1116 static void thaw_limited_counters(struct cpu_hw_events *cpuhw,
1117 unsigned long pmc5, unsigned long pmc6)
1119 struct perf_event *event;
1123 for (i = 0; i < cpuhw->n_limited; ++i) {
1124 event = cpuhw->limited_counter[i];
1125 event->hw.idx = cpuhw->limited_hwidx[i];
1126 val = (event->hw.idx == 5) ? pmc5 : pmc6;
1127 prev = local64_read(&event->hw.prev_count);
1128 if (check_and_compute_delta(prev, val))
1129 local64_set(&event->hw.prev_count, val);
1130 perf_event_update_userpage(event);
1135 * Since limited events don't respect the freeze conditions, we
1136 * have to read them immediately after freezing or unfreezing the
1137 * other events. We try to keep the values from the limited
1138 * events as consistent as possible by keeping the delay (in
1139 * cycles and instructions) between freezing/unfreezing and reading
1140 * the limited events as small and consistent as possible.
1141 * Therefore, if any limited events are in use, we read them
1142 * both, and always in the same order, to minimize variability,
1143 * and do it inside the same asm that writes MMCR0.
1145 static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0)
1147 unsigned long pmc5, pmc6;
1149 if (!cpuhw->n_limited) {
1150 mtspr(SPRN_MMCR0, mmcr0);
1155 * Write MMCR0, then read PMC5 and PMC6 immediately.
1156 * To ensure we don't get a performance monitor interrupt
1157 * between writing MMCR0 and freezing/thawing the limited
1158 * events, we first write MMCR0 with the event overflow
1159 * interrupt enable bits turned off.
1161 asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5"
1162 : "=&r" (pmc5), "=&r" (pmc6)
1163 : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)),
1165 "i" (SPRN_PMC5), "i" (SPRN_PMC6));
1167 if (mmcr0 & MMCR0_FC)
1168 freeze_limited_counters(cpuhw, pmc5, pmc6);
1170 thaw_limited_counters(cpuhw, pmc5, pmc6);
1173 * Write the full MMCR0 including the event overflow interrupt
1174 * enable bits, if necessary.
1176 if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE))
1177 mtspr(SPRN_MMCR0, mmcr0);
1181 * Disable all events to prevent PMU interrupts and to allow
1182 * events to be added or removed.
1184 static void power_pmu_disable(struct pmu *pmu)
1186 struct cpu_hw_events *cpuhw;
1187 unsigned long flags, mmcr0, val;
1191 local_irq_save(flags);
1192 cpuhw = this_cpu_ptr(&cpu_hw_events);
1194 if (!cpuhw->disabled) {
1196 * Check if we ever enabled the PMU on this cpu.
1198 if (!cpuhw->pmcs_enabled) {
1200 cpuhw->pmcs_enabled = 1;
1204 * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56
1206 val = mmcr0 = mfspr(SPRN_MMCR0);
1208 val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO |
1212 * The barrier is to make sure the mtspr has been
1213 * executed and the PMU has frozen the events etc.
1216 write_mmcr0(cpuhw, val);
1220 * Disable instruction sampling if it was enabled
1222 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
1224 cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1228 cpuhw->disabled = 1;
1231 ebb_switch_out(mmcr0);
1234 local_irq_restore(flags);
1238 * Re-enable all events if disable == 0.
1239 * If we were previously disabled and events were added, then
1240 * put the new config on the PMU.
1242 static void power_pmu_enable(struct pmu *pmu)
1244 struct perf_event *event;
1245 struct cpu_hw_events *cpuhw;
1246 unsigned long flags;
1248 unsigned long val, mmcr0;
1250 unsigned int hwc_index[MAX_HWEVENTS];
1257 local_irq_save(flags);
1259 cpuhw = this_cpu_ptr(&cpu_hw_events);
1260 if (!cpuhw->disabled)
1263 if (cpuhw->n_events == 0) {
1264 ppc_set_pmu_inuse(0);
1268 cpuhw->disabled = 0;
1271 * EBB requires an exclusive group and all events must have the EBB
1272 * flag set, or not set, so we can just check a single event. Also we
1273 * know we have at least one event.
1275 ebb = is_ebb_event(cpuhw->event[0]);
1278 * If we didn't change anything, or only removed events,
1279 * no need to recalculate MMCR* settings and reset the PMCs.
1280 * Just reenable the PMU with the current MMCR* settings
1281 * (possibly updated for removal of events).
1283 if (!cpuhw->n_added) {
1284 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1285 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
1290 * Clear all MMCR settings and recompute them for the new set of events.
1292 memset(cpuhw->mmcr, 0, sizeof(cpuhw->mmcr));
1294 if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index,
1295 cpuhw->mmcr, cpuhw->event)) {
1296 /* shouldn't ever get here */
1297 printk(KERN_ERR "oops compute_mmcr failed\n");
1301 if (!(ppmu->flags & PPMU_ARCH_207S)) {
1303 * Add in MMCR0 freeze bits corresponding to the attr.exclude_*
1304 * bits for the first event. We have already checked that all
1305 * events have the same value for these bits as the first event.
1307 event = cpuhw->event[0];
1308 if (event->attr.exclude_user)
1309 cpuhw->mmcr[0] |= MMCR0_FCP;
1310 if (event->attr.exclude_kernel)
1311 cpuhw->mmcr[0] |= freeze_events_kernel;
1312 if (event->attr.exclude_hv)
1313 cpuhw->mmcr[0] |= MMCR0_FCHV;
1317 * Write the new configuration to MMCR* with the freeze
1318 * bit set and set the hardware events to their initial values.
1319 * Then unfreeze the events.
1321 ppc_set_pmu_inuse(1);
1322 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1323 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
1324 mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
1326 if (ppmu->flags & PPMU_ARCH_207S)
1327 mtspr(SPRN_MMCR2, cpuhw->mmcr[3]);
1330 * Read off any pre-existing events that need to move
1333 for (i = 0; i < cpuhw->n_events; ++i) {
1334 event = cpuhw->event[i];
1335 if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) {
1336 power_pmu_read(event);
1337 write_pmc(event->hw.idx, 0);
1343 * Initialize the PMCs for all the new and moved events.
1345 cpuhw->n_limited = n_lim = 0;
1346 for (i = 0; i < cpuhw->n_events; ++i) {
1347 event = cpuhw->event[i];
1350 idx = hwc_index[i] + 1;
1351 if (is_limited_pmc(idx)) {
1352 cpuhw->limited_counter[n_lim] = event;
1353 cpuhw->limited_hwidx[n_lim] = idx;
1359 val = local64_read(&event->hw.prev_count);
1362 if (event->hw.sample_period) {
1363 left = local64_read(&event->hw.period_left);
1364 if (left < 0x80000000L)
1365 val = 0x80000000L - left;
1367 local64_set(&event->hw.prev_count, val);
1370 event->hw.idx = idx;
1371 if (event->hw.state & PERF_HES_STOPPED)
1373 write_pmc(idx, val);
1375 perf_event_update_userpage(event);
1377 cpuhw->n_limited = n_lim;
1378 cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE;
1381 pmao_restore_workaround(ebb);
1383 mmcr0 = ebb_switch_in(ebb, cpuhw);
1386 if (cpuhw->bhrb_users)
1387 ppmu->config_bhrb(cpuhw->bhrb_filter);
1389 write_mmcr0(cpuhw, mmcr0);
1392 * Enable instruction sampling if necessary
1394 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
1396 mtspr(SPRN_MMCRA, cpuhw->mmcr[2]);
1401 local_irq_restore(flags);
1404 static int collect_events(struct perf_event *group, int max_count,
1405 struct perf_event *ctrs[], u64 *events,
1406 unsigned int *flags)
1409 struct perf_event *event;
1411 if (!is_software_event(group)) {
1415 flags[n] = group->hw.event_base;
1416 events[n++] = group->hw.config;
1418 list_for_each_entry(event, &group->sibling_list, group_entry) {
1419 if (!is_software_event(event) &&
1420 event->state != PERF_EVENT_STATE_OFF) {
1424 flags[n] = event->hw.event_base;
1425 events[n++] = event->hw.config;
1432 * Add a event to the PMU.
1433 * If all events are not already frozen, then we disable and
1434 * re-enable the PMU in order to get hw_perf_enable to do the
1435 * actual work of reconfiguring the PMU.
1437 static int power_pmu_add(struct perf_event *event, int ef_flags)
1439 struct cpu_hw_events *cpuhw;
1440 unsigned long flags;
1444 local_irq_save(flags);
1445 perf_pmu_disable(event->pmu);
1448 * Add the event to the list (if there is room)
1449 * and check whether the total set is still feasible.
1451 cpuhw = this_cpu_ptr(&cpu_hw_events);
1452 n0 = cpuhw->n_events;
1453 if (n0 >= ppmu->n_counter)
1455 cpuhw->event[n0] = event;
1456 cpuhw->events[n0] = event->hw.config;
1457 cpuhw->flags[n0] = event->hw.event_base;
1460 * This event may have been disabled/stopped in record_and_restart()
1461 * because we exceeded the ->event_limit. If re-starting the event,
1462 * clear the ->hw.state (STOPPED and UPTODATE flags), so the user
1463 * notification is re-enabled.
1465 if (!(ef_flags & PERF_EF_START))
1466 event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
1468 event->hw.state = 0;
1471 * If group events scheduling transaction was started,
1472 * skip the schedulability test here, it will be performed
1473 * at commit time(->commit_txn) as a whole
1475 if (cpuhw->txn_flags & PERF_PMU_TXN_ADD)
1478 if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1))
1480 if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1))
1482 event->hw.config = cpuhw->events[n0];
1485 ebb_event_add(event);
1492 if (has_branch_stack(event)) {
1493 power_pmu_bhrb_enable(event);
1494 cpuhw->bhrb_filter = ppmu->bhrb_filter_map(
1495 event->attr.branch_sample_type);
1499 * Workaround for POWER9 DD1 to use the Instruction Counter
1500 * register value for instruction counting
1502 if (use_ic(event->attr.config))
1503 cpuhw->ic_init = mfspr(SPRN_IC);
1505 perf_pmu_enable(event->pmu);
1506 local_irq_restore(flags);
1511 * Remove a event from the PMU.
1513 static void power_pmu_del(struct perf_event *event, int ef_flags)
1515 struct cpu_hw_events *cpuhw;
1517 unsigned long flags;
1519 local_irq_save(flags);
1520 perf_pmu_disable(event->pmu);
1522 power_pmu_read(event);
1524 cpuhw = this_cpu_ptr(&cpu_hw_events);
1525 for (i = 0; i < cpuhw->n_events; ++i) {
1526 if (event == cpuhw->event[i]) {
1527 while (++i < cpuhw->n_events) {
1528 cpuhw->event[i-1] = cpuhw->event[i];
1529 cpuhw->events[i-1] = cpuhw->events[i];
1530 cpuhw->flags[i-1] = cpuhw->flags[i];
1533 ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr);
1534 if (event->hw.idx) {
1535 write_pmc(event->hw.idx, 0);
1538 perf_event_update_userpage(event);
1542 for (i = 0; i < cpuhw->n_limited; ++i)
1543 if (event == cpuhw->limited_counter[i])
1545 if (i < cpuhw->n_limited) {
1546 while (++i < cpuhw->n_limited) {
1547 cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i];
1548 cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i];
1552 if (cpuhw->n_events == 0) {
1553 /* disable exceptions if no events are running */
1554 cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE);
1557 if (has_branch_stack(event))
1558 power_pmu_bhrb_disable(event);
1560 perf_pmu_enable(event->pmu);
1561 local_irq_restore(flags);
1565 * POWER-PMU does not support disabling individual counters, hence
1566 * program their cycle counter to their max value and ignore the interrupts.
1569 static void power_pmu_start(struct perf_event *event, int ef_flags)
1571 unsigned long flags;
1575 if (!event->hw.idx || !event->hw.sample_period)
1578 if (!(event->hw.state & PERF_HES_STOPPED))
1581 if (ef_flags & PERF_EF_RELOAD)
1582 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1584 local_irq_save(flags);
1585 perf_pmu_disable(event->pmu);
1587 event->hw.state = 0;
1588 left = local64_read(&event->hw.period_left);
1591 if (left < 0x80000000L)
1592 val = 0x80000000L - left;
1594 write_pmc(event->hw.idx, val);
1596 perf_event_update_userpage(event);
1597 perf_pmu_enable(event->pmu);
1598 local_irq_restore(flags);
1601 static void power_pmu_stop(struct perf_event *event, int ef_flags)
1603 unsigned long flags;
1605 if (!event->hw.idx || !event->hw.sample_period)
1608 if (event->hw.state & PERF_HES_STOPPED)
1611 local_irq_save(flags);
1612 perf_pmu_disable(event->pmu);
1614 power_pmu_read(event);
1615 event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
1616 write_pmc(event->hw.idx, 0);
1618 perf_event_update_userpage(event);
1619 perf_pmu_enable(event->pmu);
1620 local_irq_restore(flags);
1624 * Start group events scheduling transaction
1625 * Set the flag to make pmu::enable() not perform the
1626 * schedulability test, it will be performed at commit time
1628 * We only support PERF_PMU_TXN_ADD transactions. Save the
1629 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1632 static void power_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1634 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1636 WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */
1638 cpuhw->txn_flags = txn_flags;
1639 if (txn_flags & ~PERF_PMU_TXN_ADD)
1642 perf_pmu_disable(pmu);
1643 cpuhw->n_txn_start = cpuhw->n_events;
1647 * Stop group events scheduling transaction
1648 * Clear the flag and pmu::enable() will perform the
1649 * schedulability test.
1651 static void power_pmu_cancel_txn(struct pmu *pmu)
1653 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1654 unsigned int txn_flags;
1656 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */
1658 txn_flags = cpuhw->txn_flags;
1659 cpuhw->txn_flags = 0;
1660 if (txn_flags & ~PERF_PMU_TXN_ADD)
1663 perf_pmu_enable(pmu);
1667 * Commit group events scheduling transaction
1668 * Perform the group schedulability test as a whole
1669 * Return 0 if success
1671 static int power_pmu_commit_txn(struct pmu *pmu)
1673 struct cpu_hw_events *cpuhw;
1679 cpuhw = this_cpu_ptr(&cpu_hw_events);
1680 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */
1682 if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) {
1683 cpuhw->txn_flags = 0;
1687 n = cpuhw->n_events;
1688 if (check_excludes(cpuhw->event, cpuhw->flags, 0, n))
1690 i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n);
1694 for (i = cpuhw->n_txn_start; i < n; ++i)
1695 cpuhw->event[i]->hw.config = cpuhw->events[i];
1697 cpuhw->txn_flags = 0;
1698 perf_pmu_enable(pmu);
1703 * Return 1 if we might be able to put event on a limited PMC,
1705 * A event can only go on a limited PMC if it counts something
1706 * that a limited PMC can count, doesn't require interrupts, and
1707 * doesn't exclude any processor mode.
1709 static int can_go_on_limited_pmc(struct perf_event *event, u64 ev,
1713 u64 alt[MAX_EVENT_ALTERNATIVES];
1715 if (event->attr.exclude_user
1716 || event->attr.exclude_kernel
1717 || event->attr.exclude_hv
1718 || event->attr.sample_period)
1721 if (ppmu->limited_pmc_event(ev))
1725 * The requested event_id isn't on a limited PMC already;
1726 * see if any alternative code goes on a limited PMC.
1728 if (!ppmu->get_alternatives)
1731 flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD;
1732 n = ppmu->get_alternatives(ev, flags, alt);
1738 * Find an alternative event_id that goes on a normal PMC, if possible,
1739 * and return the event_id code, or 0 if there is no such alternative.
1740 * (Note: event_id code 0 is "don't count" on all machines.)
1742 static u64 normal_pmc_alternative(u64 ev, unsigned long flags)
1744 u64 alt[MAX_EVENT_ALTERNATIVES];
1747 flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD);
1748 n = ppmu->get_alternatives(ev, flags, alt);
1754 /* Number of perf_events counting hardware events */
1755 static atomic_t num_events;
1756 /* Used to avoid races in calling reserve/release_pmc_hardware */
1757 static DEFINE_MUTEX(pmc_reserve_mutex);
1760 * Release the PMU if this is the last perf_event.
1762 static void hw_perf_event_destroy(struct perf_event *event)
1764 if (!atomic_add_unless(&num_events, -1, 1)) {
1765 mutex_lock(&pmc_reserve_mutex);
1766 if (atomic_dec_return(&num_events) == 0)
1767 release_pmc_hardware();
1768 mutex_unlock(&pmc_reserve_mutex);
1773 * Translate a generic cache event_id config to a raw event_id code.
1775 static int hw_perf_cache_event(u64 config, u64 *eventp)
1777 unsigned long type, op, result;
1780 if (!ppmu->cache_events)
1784 type = config & 0xff;
1785 op = (config >> 8) & 0xff;
1786 result = (config >> 16) & 0xff;
1788 if (type >= PERF_COUNT_HW_CACHE_MAX ||
1789 op >= PERF_COUNT_HW_CACHE_OP_MAX ||
1790 result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
1793 ev = (*ppmu->cache_events)[type][op][result];
1802 static int power_pmu_event_init(struct perf_event *event)
1805 unsigned long flags;
1806 struct perf_event *ctrs[MAX_HWEVENTS];
1807 u64 events[MAX_HWEVENTS];
1808 unsigned int cflags[MAX_HWEVENTS];
1811 struct cpu_hw_events *cpuhw;
1816 if (has_branch_stack(event)) {
1817 /* PMU has BHRB enabled */
1818 if (!(ppmu->flags & PPMU_ARCH_207S))
1822 switch (event->attr.type) {
1823 case PERF_TYPE_HARDWARE:
1824 ev = event->attr.config;
1825 if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)
1827 ev = ppmu->generic_events[ev];
1829 case PERF_TYPE_HW_CACHE:
1830 err = hw_perf_cache_event(event->attr.config, &ev);
1835 ev = event->attr.config;
1841 event->hw.config_base = ev;
1845 * If we are not running on a hypervisor, force the
1846 * exclude_hv bit to 0 so that we don't care what
1847 * the user set it to.
1849 if (!firmware_has_feature(FW_FEATURE_LPAR))
1850 event->attr.exclude_hv = 0;
1853 * If this is a per-task event, then we can use
1854 * PM_RUN_* events interchangeably with their non RUN_*
1855 * equivalents, e.g. PM_RUN_CYC instead of PM_CYC.
1856 * XXX we should check if the task is an idle task.
1859 if (event->attach_state & PERF_ATTACH_TASK)
1860 flags |= PPMU_ONLY_COUNT_RUN;
1863 * If this machine has limited events, check whether this
1864 * event_id could go on a limited event.
1866 if (ppmu->flags & PPMU_LIMITED_PMC5_6) {
1867 if (can_go_on_limited_pmc(event, ev, flags)) {
1868 flags |= PPMU_LIMITED_PMC_OK;
1869 } else if (ppmu->limited_pmc_event(ev)) {
1871 * The requested event_id is on a limited PMC,
1872 * but we can't use a limited PMC; see if any
1873 * alternative goes on a normal PMC.
1875 ev = normal_pmc_alternative(ev, flags);
1881 /* Extra checks for EBB */
1882 err = ebb_event_check(event);
1887 * If this is in a group, check if it can go on with all the
1888 * other hardware events in the group. We assume the event
1889 * hasn't been linked into its leader's sibling list at this point.
1892 if (event->group_leader != event) {
1893 n = collect_events(event->group_leader, ppmu->n_counter - 1,
1894 ctrs, events, cflags);
1901 if (check_excludes(ctrs, cflags, n, 1))
1904 cpuhw = &get_cpu_var(cpu_hw_events);
1905 err = power_check_constraints(cpuhw, events, cflags, n + 1);
1907 if (has_branch_stack(event)) {
1908 cpuhw->bhrb_filter = ppmu->bhrb_filter_map(
1909 event->attr.branch_sample_type);
1911 if (cpuhw->bhrb_filter == -1) {
1912 put_cpu_var(cpu_hw_events);
1917 put_cpu_var(cpu_hw_events);
1921 event->hw.config = events[n];
1922 event->hw.event_base = cflags[n];
1923 event->hw.last_period = event->hw.sample_period;
1924 local64_set(&event->hw.period_left, event->hw.last_period);
1927 * For EBB events we just context switch the PMC value, we don't do any
1928 * of the sample_period logic. We use hw.prev_count for this.
1930 if (is_ebb_event(event))
1931 local64_set(&event->hw.prev_count, 0);
1934 * See if we need to reserve the PMU.
1935 * If no events are currently in use, then we have to take a
1936 * mutex to ensure that we don't race with another task doing
1937 * reserve_pmc_hardware or release_pmc_hardware.
1940 if (!atomic_inc_not_zero(&num_events)) {
1941 mutex_lock(&pmc_reserve_mutex);
1942 if (atomic_read(&num_events) == 0 &&
1943 reserve_pmc_hardware(perf_event_interrupt))
1946 atomic_inc(&num_events);
1947 mutex_unlock(&pmc_reserve_mutex);
1949 event->destroy = hw_perf_event_destroy;
1954 static int power_pmu_event_idx(struct perf_event *event)
1956 return event->hw.idx;
1959 ssize_t power_events_sysfs_show(struct device *dev,
1960 struct device_attribute *attr, char *page)
1962 struct perf_pmu_events_attr *pmu_attr;
1964 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
1966 return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
1969 static struct pmu power_pmu = {
1970 .pmu_enable = power_pmu_enable,
1971 .pmu_disable = power_pmu_disable,
1972 .event_init = power_pmu_event_init,
1973 .add = power_pmu_add,
1974 .del = power_pmu_del,
1975 .start = power_pmu_start,
1976 .stop = power_pmu_stop,
1977 .read = power_pmu_read,
1978 .start_txn = power_pmu_start_txn,
1979 .cancel_txn = power_pmu_cancel_txn,
1980 .commit_txn = power_pmu_commit_txn,
1981 .event_idx = power_pmu_event_idx,
1982 .sched_task = power_pmu_sched_task,
1986 * A counter has overflowed; update its count and record
1987 * things if requested. Note that interrupts are hard-disabled
1988 * here so there is no possibility of being interrupted.
1990 static void record_and_restart(struct perf_event *event, unsigned long val,
1991 struct pt_regs *regs)
1993 u64 period = event->hw.sample_period;
1994 s64 prev, delta, left;
1997 if (event->hw.state & PERF_HES_STOPPED) {
1998 write_pmc(event->hw.idx, 0);
2002 /* we don't have to worry about interrupts here */
2003 prev = local64_read(&event->hw.prev_count);
2004 delta = check_and_compute_delta(prev, val);
2005 local64_add(delta, &event->count);
2008 * See if the total period for this event has expired,
2009 * and update for the next period.
2012 left = local64_read(&event->hw.period_left) - delta;
2020 record = siar_valid(regs);
2021 event->hw.last_period = event->hw.sample_period;
2023 if (left < 0x80000000LL)
2024 val = 0x80000000LL - left;
2027 write_pmc(event->hw.idx, val);
2028 local64_set(&event->hw.prev_count, val);
2029 local64_set(&event->hw.period_left, left);
2030 perf_event_update_userpage(event);
2033 * Finally record data if requested.
2036 struct perf_sample_data data;
2038 perf_sample_data_init(&data, ~0ULL, event->hw.last_period);
2040 if (event->attr.sample_type & PERF_SAMPLE_ADDR)
2041 perf_get_data_addr(regs, &data.addr);
2043 if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) {
2044 struct cpu_hw_events *cpuhw;
2045 cpuhw = this_cpu_ptr(&cpu_hw_events);
2046 power_pmu_bhrb_read(cpuhw);
2047 data.br_stack = &cpuhw->bhrb_stack;
2050 if (perf_event_overflow(event, &data, regs))
2051 power_pmu_stop(event, 0);
2056 * Called from generic code to get the misc flags (i.e. processor mode)
2059 unsigned long perf_misc_flags(struct pt_regs *regs)
2061 u32 flags = perf_get_misc_flags(regs);
2065 return user_mode(regs) ? PERF_RECORD_MISC_USER :
2066 PERF_RECORD_MISC_KERNEL;
2070 * Called from generic code to get the instruction pointer
2073 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2075 bool use_siar = regs_use_siar(regs);
2077 if (use_siar && siar_valid(regs))
2078 return mfspr(SPRN_SIAR) + perf_ip_adjust(regs);
2080 return 0; // no valid instruction pointer
2085 static bool pmc_overflow_power7(unsigned long val)
2088 * Events on POWER7 can roll back if a speculative event doesn't
2089 * eventually complete. Unfortunately in some rare cases they will
2090 * raise a performance monitor exception. We need to catch this to
2091 * ensure we reset the PMC. In all cases the PMC will be 256 or less
2092 * cycles from overflow.
2094 * We only do this if the first pass fails to find any overflowing
2095 * PMCs because a user might set a period of less than 256 and we
2096 * don't want to mistakenly reset them.
2098 if ((0x80000000 - val) <= 256)
2104 static bool pmc_overflow(unsigned long val)
2113 * Performance monitor interrupt stuff
2115 static void perf_event_interrupt(struct pt_regs *regs)
2118 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
2119 struct perf_event *event;
2120 unsigned long val[8];
2124 if (cpuhw->n_limited)
2125 freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5),
2128 perf_read_regs(regs);
2130 nmi = perf_intr_is_nmi(regs);
2136 /* Read all the PMCs since we'll need them a bunch of times */
2137 for (i = 0; i < ppmu->n_counter; ++i)
2138 val[i] = read_pmc(i + 1);
2140 /* Try to find what caused the IRQ */
2142 for (i = 0; i < ppmu->n_counter; ++i) {
2143 if (!pmc_overflow(val[i]))
2145 if (is_limited_pmc(i + 1))
2146 continue; /* these won't generate IRQs */
2148 * We've found one that's overflowed. For active
2149 * counters we need to log this. For inactive
2150 * counters, we need to reset it anyway
2154 for (j = 0; j < cpuhw->n_events; ++j) {
2155 event = cpuhw->event[j];
2156 if (event->hw.idx == (i + 1)) {
2158 record_and_restart(event, val[i], regs);
2163 /* reset non active counters that have overflowed */
2164 write_pmc(i + 1, 0);
2166 if (!found && pvr_version_is(PVR_POWER7)) {
2167 /* check active counters for special buggy p7 overflow */
2168 for (i = 0; i < cpuhw->n_events; ++i) {
2169 event = cpuhw->event[i];
2170 if (!event->hw.idx || is_limited_pmc(event->hw.idx))
2172 if (pmc_overflow_power7(val[event->hw.idx - 1])) {
2173 /* event has overflowed in a buggy way*/
2175 record_and_restart(event,
2176 val[event->hw.idx - 1],
2181 if (!found && !nmi && printk_ratelimit())
2182 printk(KERN_WARNING "Can't find PMC that caused IRQ\n");
2185 * Reset MMCR0 to its normal value. This will set PMXE and
2186 * clear FC (freeze counters) and PMAO (perf mon alert occurred)
2187 * and thus allow interrupts to occur again.
2188 * XXX might want to use MSR.PM to keep the events frozen until
2189 * we get back out of this interrupt.
2191 write_mmcr0(cpuhw, cpuhw->mmcr[0]);
2199 static int power_pmu_prepare_cpu(unsigned int cpu)
2201 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
2204 memset(cpuhw, 0, sizeof(*cpuhw));
2205 cpuhw->mmcr[0] = MMCR0_FC;
2210 int register_power_pmu(struct power_pmu *pmu)
2213 return -EBUSY; /* something's already registered */
2216 pr_info("%s performance monitor hardware support registered\n",
2219 power_pmu.attr_groups = ppmu->attr_groups;
2223 * Use FCHV to ignore kernel events if MSR.HV is set.
2225 if (mfmsr() & MSR_HV)
2226 freeze_events_kernel = MMCR0_FCHV;
2227 #endif /* CONFIG_PPC64 */
2229 perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW);
2230 cpuhp_setup_state(CPUHP_PERF_POWER, "perf/powerpc:prepare",
2231 power_pmu_prepare_cpu, NULL);