2 * Performance event support - powerpc architecture code
4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 #include <linux/kernel.h>
12 #include <linux/sched.h>
13 #include <linux/perf_event.h>
14 #include <linux/percpu.h>
15 #include <linux/hardirq.h>
16 #include <linux/uaccess.h>
19 #include <asm/machdep.h>
20 #include <asm/firmware.h>
21 #include <asm/ptrace.h>
22 #include <asm/code-patching.h>
24 #define BHRB_MAX_ENTRIES 32
25 #define BHRB_TARGET 0x0000000000000002
26 #define BHRB_PREDICTION 0x0000000000000001
27 #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL
29 struct cpu_hw_events {
36 struct perf_event *event[MAX_HWEVENTS];
37 u64 events[MAX_HWEVENTS];
38 unsigned int flags[MAX_HWEVENTS];
39 unsigned long mmcr[3];
40 struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS];
41 u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS];
42 u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
43 unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
44 unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
46 unsigned int group_flag;
50 u64 bhrb_filter; /* BHRB HW branch filter */
53 struct perf_branch_stack bhrb_stack;
54 struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES];
57 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
59 struct power_pmu *ppmu;
62 * Normally, to ignore kernel events we set the FCS (freeze counters
63 * in supervisor mode) bit in MMCR0, but if the kernel runs with the
64 * hypervisor bit set in the MSR, or if we are running on a processor
65 * where the hypervisor bit is forced to 1 (as on Apple G5 processors),
66 * then we need to use the FCHV bit to ignore kernel events.
68 static unsigned int freeze_events_kernel = MMCR0_FCS;
71 * 32-bit doesn't have MMCRA but does have an MMCR2,
72 * and a few other names are different.
77 #define MMCR0_PMCjCE MMCR0_PMCnCE
83 #define MMCR0_PMCC_U6 0
85 #define SPRN_MMCRA SPRN_MMCR2
86 #define MMCRA_SAMPLE_ENABLE 0
88 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
92 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { }
93 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
97 static inline void perf_read_regs(struct pt_regs *regs)
101 static inline int perf_intr_is_nmi(struct pt_regs *regs)
106 static inline int siar_valid(struct pt_regs *regs)
111 static bool is_ebb_event(struct perf_event *event) { return false; }
112 static int ebb_event_check(struct perf_event *event) { return 0; }
113 static void ebb_event_add(struct perf_event *event) { }
114 static void ebb_switch_out(unsigned long mmcr0) { }
115 static unsigned long ebb_switch_in(bool ebb, unsigned long mmcr0)
120 static inline void power_pmu_bhrb_enable(struct perf_event *event) {}
121 static inline void power_pmu_bhrb_disable(struct perf_event *event) {}
122 void power_pmu_flush_branch_stack(void) {}
123 static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {}
124 static void pmao_restore_workaround(bool ebb) { }
125 #endif /* CONFIG_PPC32 */
127 static bool regs_use_siar(struct pt_regs *regs)
129 return !!regs->result;
133 * Things that are specific to 64-bit implementations.
137 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
139 unsigned long mmcra = regs->dsisr;
141 if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) {
142 unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT;
144 return 4 * (slot - 1);
151 * The user wants a data address recorded.
152 * If we're not doing instruction sampling, give them the SDAR
153 * (sampled data address). If we are doing instruction sampling, then
154 * only give them the SDAR if it corresponds to the instruction
155 * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the
156 * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER.
158 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp)
160 unsigned long mmcra = regs->dsisr;
163 if (ppmu->flags & PPMU_HAS_SIER)
164 sdar_valid = regs->dar & SIER_SDAR_VALID;
166 unsigned long sdsync;
168 if (ppmu->flags & PPMU_SIAR_VALID)
169 sdsync = POWER7P_MMCRA_SDAR_VALID;
170 else if (ppmu->flags & PPMU_ALT_SIPR)
171 sdsync = POWER6_MMCRA_SDSYNC;
173 sdsync = MMCRA_SDSYNC;
175 sdar_valid = mmcra & sdsync;
178 if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid)
179 *addrp = mfspr(SPRN_SDAR);
182 static bool regs_sihv(struct pt_regs *regs)
184 unsigned long sihv = MMCRA_SIHV;
186 if (ppmu->flags & PPMU_HAS_SIER)
187 return !!(regs->dar & SIER_SIHV);
189 if (ppmu->flags & PPMU_ALT_SIPR)
190 sihv = POWER6_MMCRA_SIHV;
192 return !!(regs->dsisr & sihv);
195 static bool regs_sipr(struct pt_regs *regs)
197 unsigned long sipr = MMCRA_SIPR;
199 if (ppmu->flags & PPMU_HAS_SIER)
200 return !!(regs->dar & SIER_SIPR);
202 if (ppmu->flags & PPMU_ALT_SIPR)
203 sipr = POWER6_MMCRA_SIPR;
205 return !!(regs->dsisr & sipr);
208 static inline u32 perf_flags_from_msr(struct pt_regs *regs)
210 if (regs->msr & MSR_PR)
211 return PERF_RECORD_MISC_USER;
212 if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV)
213 return PERF_RECORD_MISC_HYPERVISOR;
214 return PERF_RECORD_MISC_KERNEL;
217 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
219 bool use_siar = regs_use_siar(regs);
222 return perf_flags_from_msr(regs);
225 * If we don't have flags in MMCRA, rather than using
226 * the MSR, we intuit the flags from the address in
227 * SIAR which should give slightly more reliable
230 if (ppmu->flags & PPMU_NO_SIPR) {
231 unsigned long siar = mfspr(SPRN_SIAR);
232 if (siar >= PAGE_OFFSET)
233 return PERF_RECORD_MISC_KERNEL;
234 return PERF_RECORD_MISC_USER;
237 /* PR has priority over HV, so order below is important */
239 return PERF_RECORD_MISC_USER;
241 if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV))
242 return PERF_RECORD_MISC_HYPERVISOR;
244 return PERF_RECORD_MISC_KERNEL;
248 * Overload regs->dsisr to store MMCRA so we only need to read it once
250 * Overload regs->dar to store SIER if we have it.
251 * Overload regs->result to specify whether we should use the MSR (result
252 * is zero) or the SIAR (result is non zero).
254 static inline void perf_read_regs(struct pt_regs *regs)
256 unsigned long mmcra = mfspr(SPRN_MMCRA);
257 int marked = mmcra & MMCRA_SAMPLE_ENABLE;
262 if (ppmu->flags & PPMU_HAS_SIER)
263 regs->dar = mfspr(SPRN_SIER);
266 * If this isn't a PMU exception (eg a software event) the SIAR is
267 * not valid. Use pt_regs.
269 * If it is a marked event use the SIAR.
271 * If the PMU doesn't update the SIAR for non marked events use
274 * If the PMU has HV/PR flags then check to see if they
275 * place the exception in userspace. If so, use pt_regs. In
276 * continuous sampling mode the SIAR and the PMU exception are
277 * not synchronised, so they may be many instructions apart.
278 * This can result in confusing backtraces. We still want
279 * hypervisor samples as well as samples in the kernel with
280 * interrupts off hence the userspace check.
282 if (TRAP(regs) != 0xf00)
286 else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING))
288 else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs))
293 regs->result = use_siar;
297 * If interrupts were soft-disabled when a PMU interrupt occurs, treat
300 static inline int perf_intr_is_nmi(struct pt_regs *regs)
306 * On processors like P7+ that have the SIAR-Valid bit, marked instructions
307 * must be sampled only if the SIAR-valid bit is set.
309 * For unmarked instructions and for processors that don't have the SIAR-Valid
310 * bit, assume that SIAR is valid.
312 static inline int siar_valid(struct pt_regs *regs)
314 unsigned long mmcra = regs->dsisr;
315 int marked = mmcra & MMCRA_SAMPLE_ENABLE;
318 if (ppmu->flags & PPMU_HAS_SIER)
319 return regs->dar & SIER_SIAR_VALID;
321 if (ppmu->flags & PPMU_SIAR_VALID)
322 return mmcra & POWER7P_MMCRA_SIAR_VALID;
329 /* Reset all possible BHRB entries */
330 static void power_pmu_bhrb_reset(void)
332 asm volatile(PPC_CLRBHRB);
335 static void power_pmu_bhrb_enable(struct perf_event *event)
337 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
342 /* Clear BHRB if we changed task context to avoid data leaks */
343 if (event->ctx->task && cpuhw->bhrb_context != event->ctx) {
344 power_pmu_bhrb_reset();
345 cpuhw->bhrb_context = event->ctx;
350 static void power_pmu_bhrb_disable(struct perf_event *event)
352 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
358 WARN_ON_ONCE(cpuhw->bhrb_users < 0);
360 if (!cpuhw->disabled && !cpuhw->bhrb_users) {
361 /* BHRB cannot be turned off when other
362 * events are active on the PMU.
365 /* avoid stale pointer */
366 cpuhw->bhrb_context = NULL;
370 /* Called from ctxsw to prevent one process's branch entries to
371 * mingle with the other process's entries during context switch.
373 void power_pmu_flush_branch_stack(void)
376 power_pmu_bhrb_reset();
378 /* Calculate the to address for a branch */
379 static __u64 power_pmu_bhrb_to(u64 addr)
385 if (is_kernel_addr(addr))
386 return branch_target((unsigned int *)addr);
388 /* Userspace: need copy instruction here then translate it */
390 ret = __get_user_inatomic(instr, (unsigned int __user *)addr);
397 target = branch_target(&instr);
398 if ((!target) || (instr & BRANCH_ABSOLUTE))
401 /* Translate relative branch target from kernel to user address */
402 return target - (unsigned long)&instr + addr;
405 /* Processing BHRB entries */
406 void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw)
410 int r_index, u_index, pred;
414 while (r_index < ppmu->bhrb_nr) {
415 /* Assembly read function */
416 val = read_bhrb(r_index++);
418 /* Terminal marker: End of valid BHRB entries */
421 addr = val & BHRB_EA;
422 pred = val & BHRB_PREDICTION;
428 /* Branches are read most recent first (ie. mfbhrb 0 is
429 * the most recent branch).
430 * There are two types of valid entries:
431 * 1) a target entry which is the to address of a
432 * computed goto like a blr,bctr,btar. The next
433 * entry read from the bhrb will be branch
434 * corresponding to this target (ie. the actual
435 * blr/bctr/btar instruction).
436 * 2) a from address which is an actual branch. If a
437 * target entry proceeds this, then this is the
438 * matching branch for that target. If this is not
439 * following a target entry, then this is a branch
440 * where the target is given as an immediate field
441 * in the instruction (ie. an i or b form branch).
442 * In this case we need to read the instruction from
443 * memory to determine the target/to address.
446 if (val & BHRB_TARGET) {
447 /* Target branches use two entries
448 * (ie. computed gotos/XL form)
450 cpuhw->bhrb_entries[u_index].to = addr;
451 cpuhw->bhrb_entries[u_index].mispred = pred;
452 cpuhw->bhrb_entries[u_index].predicted = ~pred;
454 /* Get from address in next entry */
455 val = read_bhrb(r_index++);
456 addr = val & BHRB_EA;
457 if (val & BHRB_TARGET) {
458 /* Shouldn't have two targets in a
459 row.. Reset index and try again */
463 cpuhw->bhrb_entries[u_index].from = addr;
465 /* Branches to immediate field
467 cpuhw->bhrb_entries[u_index].from = addr;
468 cpuhw->bhrb_entries[u_index].to =
469 power_pmu_bhrb_to(addr);
470 cpuhw->bhrb_entries[u_index].mispred = pred;
471 cpuhw->bhrb_entries[u_index].predicted = ~pred;
477 cpuhw->bhrb_stack.nr = u_index;
481 static bool is_ebb_event(struct perf_event *event)
484 * This could be a per-PMU callback, but we'd rather avoid the cost. We
485 * check that the PMU supports EBB, meaning those that don't can still
486 * use bit 63 of the event code for something else if they wish.
488 return (ppmu->flags & PPMU_ARCH_207S) &&
489 ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1);
492 static int ebb_event_check(struct perf_event *event)
494 struct perf_event *leader = event->group_leader;
496 /* Event and group leader must agree on EBB */
497 if (is_ebb_event(leader) != is_ebb_event(event))
500 if (is_ebb_event(event)) {
501 if (!(event->attach_state & PERF_ATTACH_TASK))
504 if (!leader->attr.pinned || !leader->attr.exclusive)
507 if (event->attr.freq ||
508 event->attr.inherit ||
509 event->attr.sample_type ||
510 event->attr.sample_period ||
511 event->attr.enable_on_exec)
518 static void ebb_event_add(struct perf_event *event)
520 if (!is_ebb_event(event) || current->thread.used_ebb)
524 * IFF this is the first time we've added an EBB event, set
525 * PMXE in the user MMCR0 so we can detect when it's cleared by
526 * userspace. We need this so that we can context switch while
527 * userspace is in the EBB handler (where PMXE is 0).
529 current->thread.used_ebb = 1;
530 current->thread.mmcr0 |= MMCR0_PMXE;
533 static void ebb_switch_out(unsigned long mmcr0)
535 if (!(mmcr0 & MMCR0_EBE))
538 current->thread.siar = mfspr(SPRN_SIAR);
539 current->thread.sier = mfspr(SPRN_SIER);
540 current->thread.sdar = mfspr(SPRN_SDAR);
541 current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK;
542 current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK;
545 static unsigned long ebb_switch_in(bool ebb, unsigned long mmcr0)
550 /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */
551 mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6;
554 * Add any bits from the user MMCR0, FC or PMAO. This is compatible
555 * with pmao_restore_workaround() because we may add PMAO but we never
558 mmcr0 |= current->thread.mmcr0;
561 * Be careful not to set PMXE if userspace had it cleared. This is also
562 * compatible with pmao_restore_workaround() because it has already
563 * cleared PMXE and we leave PMAO alone.
565 if (!(current->thread.mmcr0 & MMCR0_PMXE))
566 mmcr0 &= ~MMCR0_PMXE;
568 mtspr(SPRN_SIAR, current->thread.siar);
569 mtspr(SPRN_SIER, current->thread.sier);
570 mtspr(SPRN_SDAR, current->thread.sdar);
571 mtspr(SPRN_MMCR2, current->thread.mmcr2);
576 static void pmao_restore_workaround(bool ebb)
580 if (!cpu_has_feature(CPU_FTR_PMAO_BUG))
584 * On POWER8E there is a hardware defect which affects the PMU context
585 * switch logic, ie. power_pmu_disable/enable().
587 * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0
588 * by the hardware. Sometime later the actual PMU exception is
591 * If we context switch, or simply disable/enable, the PMU prior to the
592 * exception arriving, the exception will be lost when we clear PMAO.
594 * When we reenable the PMU, we will write the saved MMCR0 with PMAO
595 * set, and this _should_ generate an exception. However because of the
596 * defect no exception is generated when we write PMAO, and we get
597 * stuck with no counters counting but no exception delivered.
599 * The workaround is to detect this case and tweak the hardware to
600 * create another pending PMU exception.
602 * We do that by setting up PMC6 (cycles) for an imminent overflow and
603 * enabling the PMU. That causes a new exception to be generated in the
604 * chip, but we don't take it yet because we have interrupts hard
605 * disabled. We then write back the PMU state as we want it to be seen
606 * by the exception handler. When we reenable interrupts the exception
607 * handler will be called and see the correct state.
609 * The logic is the same for EBB, except that the exception is gated by
610 * us having interrupts hard disabled as well as the fact that we are
611 * not in userspace. The exception is finally delivered when we return
615 /* Only if PMAO is set and PMAO_SYNC is clear */
616 if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO)
619 /* If we're doing EBB, only if BESCR[GE] is set */
620 if (ebb && !(current->thread.bescr & BESCR_GE))
624 * We are already soft-disabled in power_pmu_enable(). We need to hard
625 * enable to actually prevent the PMU exception from firing.
630 * This is a bit gross, but we know we're on POWER8E and have 6 PMCs.
631 * Using read/write_pmc() in a for loop adds 12 function calls and
632 * almost doubles our code size.
634 pmcs[0] = mfspr(SPRN_PMC1);
635 pmcs[1] = mfspr(SPRN_PMC2);
636 pmcs[2] = mfspr(SPRN_PMC3);
637 pmcs[3] = mfspr(SPRN_PMC4);
638 pmcs[4] = mfspr(SPRN_PMC5);
639 pmcs[5] = mfspr(SPRN_PMC6);
641 /* Ensure all freeze bits are unset */
642 mtspr(SPRN_MMCR2, 0);
644 /* Set up PMC6 to overflow in one cycle */
645 mtspr(SPRN_PMC6, 0x7FFFFFFE);
647 /* Enable exceptions and unfreeze PMC6 */
648 mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO);
650 /* Now we need to refreeze and restore the PMCs */
651 mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO);
653 mtspr(SPRN_PMC1, pmcs[0]);
654 mtspr(SPRN_PMC2, pmcs[1]);
655 mtspr(SPRN_PMC3, pmcs[2]);
656 mtspr(SPRN_PMC4, pmcs[3]);
657 mtspr(SPRN_PMC5, pmcs[4]);
658 mtspr(SPRN_PMC6, pmcs[5]);
660 #endif /* CONFIG_PPC64 */
662 static void perf_event_interrupt(struct pt_regs *regs);
665 * Read one performance monitor counter (PMC).
667 static unsigned long read_pmc(int idx)
673 val = mfspr(SPRN_PMC1);
676 val = mfspr(SPRN_PMC2);
679 val = mfspr(SPRN_PMC3);
682 val = mfspr(SPRN_PMC4);
685 val = mfspr(SPRN_PMC5);
688 val = mfspr(SPRN_PMC6);
692 val = mfspr(SPRN_PMC7);
695 val = mfspr(SPRN_PMC8);
697 #endif /* CONFIG_PPC64 */
699 printk(KERN_ERR "oops trying to read PMC%d\n", idx);
708 static void write_pmc(int idx, unsigned long val)
712 mtspr(SPRN_PMC1, val);
715 mtspr(SPRN_PMC2, val);
718 mtspr(SPRN_PMC3, val);
721 mtspr(SPRN_PMC4, val);
724 mtspr(SPRN_PMC5, val);
727 mtspr(SPRN_PMC6, val);
731 mtspr(SPRN_PMC7, val);
734 mtspr(SPRN_PMC8, val);
736 #endif /* CONFIG_PPC64 */
738 printk(KERN_ERR "oops trying to write PMC%d\n", idx);
742 /* Called from sysrq_handle_showregs() */
743 void perf_event_print_debug(void)
745 unsigned long sdar, sier, flags;
746 u32 pmcs[MAX_HWEVENTS];
749 if (!ppmu->n_counter)
752 local_irq_save(flags);
754 pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d",
755 smp_processor_id(), ppmu->name, ppmu->n_counter);
757 for (i = 0; i < ppmu->n_counter; i++)
758 pmcs[i] = read_pmc(i + 1);
760 for (; i < MAX_HWEVENTS; i++)
761 pmcs[i] = 0xdeadbeef;
763 pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n",
764 pmcs[0], pmcs[1], pmcs[2], pmcs[3]);
766 if (ppmu->n_counter > 4)
767 pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n",
768 pmcs[4], pmcs[5], pmcs[6], pmcs[7]);
770 pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n",
771 mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA));
775 sdar = mfspr(SPRN_SDAR);
777 if (ppmu->flags & PPMU_HAS_SIER)
778 sier = mfspr(SPRN_SIER);
780 if (ppmu->flags & PPMU_ARCH_207S) {
781 pr_info("MMCR2: %016lx EBBHR: %016lx\n",
782 mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR));
783 pr_info("EBBRR: %016lx BESCR: %016lx\n",
784 mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR));
787 pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n",
788 mfspr(SPRN_SIAR), sdar, sier);
790 local_irq_restore(flags);
794 * Check if a set of events can all go on the PMU at once.
795 * If they can't, this will look at alternative codes for the events
796 * and see if any combination of alternative codes is feasible.
797 * The feasible set is returned in event_id[].
799 static int power_check_constraints(struct cpu_hw_events *cpuhw,
800 u64 event_id[], unsigned int cflags[],
803 unsigned long mask, value, nv;
804 unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS];
805 int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS];
807 unsigned long addf = ppmu->add_fields;
808 unsigned long tadd = ppmu->test_adder;
810 if (n_ev > ppmu->n_counter)
813 /* First see if the events will go on as-is */
814 for (i = 0; i < n_ev; ++i) {
815 if ((cflags[i] & PPMU_LIMITED_PMC_REQD)
816 && !ppmu->limited_pmc_event(event_id[i])) {
817 ppmu->get_alternatives(event_id[i], cflags[i],
818 cpuhw->alternatives[i]);
819 event_id[i] = cpuhw->alternatives[i][0];
821 if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0],
822 &cpuhw->avalues[i][0]))
826 for (i = 0; i < n_ev; ++i) {
827 nv = (value | cpuhw->avalues[i][0]) +
828 (value & cpuhw->avalues[i][0] & addf);
829 if ((((nv + tadd) ^ value) & mask) != 0 ||
830 (((nv + tadd) ^ cpuhw->avalues[i][0]) &
831 cpuhw->amasks[i][0]) != 0)
834 mask |= cpuhw->amasks[i][0];
837 return 0; /* all OK */
839 /* doesn't work, gather alternatives... */
840 if (!ppmu->get_alternatives)
842 for (i = 0; i < n_ev; ++i) {
844 n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i],
845 cpuhw->alternatives[i]);
846 for (j = 1; j < n_alt[i]; ++j)
847 ppmu->get_constraint(cpuhw->alternatives[i][j],
848 &cpuhw->amasks[i][j],
849 &cpuhw->avalues[i][j]);
852 /* enumerate all possibilities and see if any will work */
855 value = mask = nv = 0;
858 /* we're backtracking, restore context */
864 * See if any alternative k for event_id i,
865 * where k > j, will satisfy the constraints.
867 while (++j < n_alt[i]) {
868 nv = (value | cpuhw->avalues[i][j]) +
869 (value & cpuhw->avalues[i][j] & addf);
870 if ((((nv + tadd) ^ value) & mask) == 0 &&
871 (((nv + tadd) ^ cpuhw->avalues[i][j])
872 & cpuhw->amasks[i][j]) == 0)
877 * No feasible alternative, backtrack
878 * to event_id i-1 and continue enumerating its
879 * alternatives from where we got up to.
885 * Found a feasible alternative for event_id i,
886 * remember where we got up to with this event_id,
887 * go on to the next event_id, and start with
888 * the first alternative for it.
894 mask |= cpuhw->amasks[i][j];
900 /* OK, we have a feasible combination, tell the caller the solution */
901 for (i = 0; i < n_ev; ++i)
902 event_id[i] = cpuhw->alternatives[i][choice[i]];
907 * Check if newly-added events have consistent settings for
908 * exclude_{user,kernel,hv} with each other and any previously
911 static int check_excludes(struct perf_event **ctrs, unsigned int cflags[],
912 int n_prev, int n_new)
914 int eu = 0, ek = 0, eh = 0;
916 struct perf_event *event;
923 for (i = 0; i < n; ++i) {
924 if (cflags[i] & PPMU_LIMITED_PMC_OK) {
925 cflags[i] &= ~PPMU_LIMITED_PMC_REQD;
930 eu = event->attr.exclude_user;
931 ek = event->attr.exclude_kernel;
932 eh = event->attr.exclude_hv;
934 } else if (event->attr.exclude_user != eu ||
935 event->attr.exclude_kernel != ek ||
936 event->attr.exclude_hv != eh) {
942 for (i = 0; i < n; ++i)
943 if (cflags[i] & PPMU_LIMITED_PMC_OK)
944 cflags[i] |= PPMU_LIMITED_PMC_REQD;
949 static u64 check_and_compute_delta(u64 prev, u64 val)
951 u64 delta = (val - prev) & 0xfffffffful;
954 * POWER7 can roll back counter values, if the new value is smaller
955 * than the previous value it will cause the delta and the counter to
956 * have bogus values unless we rolled a counter over. If a coutner is
957 * rolled back, it will be smaller, but within 256, which is the maximum
958 * number of events to rollback at once. If we dectect a rollback
959 * return 0. This can lead to a small lack of precision in the
962 if (prev > val && (prev - val) < 256)
968 static void power_pmu_read(struct perf_event *event)
970 s64 val, delta, prev;
972 if (event->hw.state & PERF_HES_STOPPED)
978 if (is_ebb_event(event)) {
979 val = read_pmc(event->hw.idx);
980 local64_set(&event->hw.prev_count, val);
985 * Performance monitor interrupts come even when interrupts
986 * are soft-disabled, as long as interrupts are hard-enabled.
987 * Therefore we treat them like NMIs.
990 prev = local64_read(&event->hw.prev_count);
992 val = read_pmc(event->hw.idx);
993 delta = check_and_compute_delta(prev, val);
996 } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
998 local64_add(delta, &event->count);
1001 * A number of places program the PMC with (0x80000000 - period_left).
1002 * We never want period_left to be less than 1 because we will program
1003 * the PMC with a value >= 0x800000000 and an edge detected PMC will
1004 * roll around to 0 before taking an exception. We have seen this
1007 * To fix this, clamp the minimum value of period_left to 1.
1010 prev = local64_read(&event->hw.period_left);
1014 } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev);
1018 * On some machines, PMC5 and PMC6 can't be written, don't respect
1019 * the freeze conditions, and don't generate interrupts. This tells
1020 * us if `event' is using such a PMC.
1022 static int is_limited_pmc(int pmcnum)
1024 return (ppmu->flags & PPMU_LIMITED_PMC5_6)
1025 && (pmcnum == 5 || pmcnum == 6);
1028 static void freeze_limited_counters(struct cpu_hw_events *cpuhw,
1029 unsigned long pmc5, unsigned long pmc6)
1031 struct perf_event *event;
1032 u64 val, prev, delta;
1035 for (i = 0; i < cpuhw->n_limited; ++i) {
1036 event = cpuhw->limited_counter[i];
1039 val = (event->hw.idx == 5) ? pmc5 : pmc6;
1040 prev = local64_read(&event->hw.prev_count);
1042 delta = check_and_compute_delta(prev, val);
1044 local64_add(delta, &event->count);
1048 static void thaw_limited_counters(struct cpu_hw_events *cpuhw,
1049 unsigned long pmc5, unsigned long pmc6)
1051 struct perf_event *event;
1055 for (i = 0; i < cpuhw->n_limited; ++i) {
1056 event = cpuhw->limited_counter[i];
1057 event->hw.idx = cpuhw->limited_hwidx[i];
1058 val = (event->hw.idx == 5) ? pmc5 : pmc6;
1059 prev = local64_read(&event->hw.prev_count);
1060 if (check_and_compute_delta(prev, val))
1061 local64_set(&event->hw.prev_count, val);
1062 perf_event_update_userpage(event);
1067 * Since limited events don't respect the freeze conditions, we
1068 * have to read them immediately after freezing or unfreezing the
1069 * other events. We try to keep the values from the limited
1070 * events as consistent as possible by keeping the delay (in
1071 * cycles and instructions) between freezing/unfreezing and reading
1072 * the limited events as small and consistent as possible.
1073 * Therefore, if any limited events are in use, we read them
1074 * both, and always in the same order, to minimize variability,
1075 * and do it inside the same asm that writes MMCR0.
1077 static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0)
1079 unsigned long pmc5, pmc6;
1081 if (!cpuhw->n_limited) {
1082 mtspr(SPRN_MMCR0, mmcr0);
1087 * Write MMCR0, then read PMC5 and PMC6 immediately.
1088 * To ensure we don't get a performance monitor interrupt
1089 * between writing MMCR0 and freezing/thawing the limited
1090 * events, we first write MMCR0 with the event overflow
1091 * interrupt enable bits turned off.
1093 asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5"
1094 : "=&r" (pmc5), "=&r" (pmc6)
1095 : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)),
1097 "i" (SPRN_PMC5), "i" (SPRN_PMC6));
1099 if (mmcr0 & MMCR0_FC)
1100 freeze_limited_counters(cpuhw, pmc5, pmc6);
1102 thaw_limited_counters(cpuhw, pmc5, pmc6);
1105 * Write the full MMCR0 including the event overflow interrupt
1106 * enable bits, if necessary.
1108 if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE))
1109 mtspr(SPRN_MMCR0, mmcr0);
1113 * Disable all events to prevent PMU interrupts and to allow
1114 * events to be added or removed.
1116 static void power_pmu_disable(struct pmu *pmu)
1118 struct cpu_hw_events *cpuhw;
1119 unsigned long flags, mmcr0, val;
1123 local_irq_save(flags);
1124 cpuhw = &__get_cpu_var(cpu_hw_events);
1126 if (!cpuhw->disabled) {
1128 * Check if we ever enabled the PMU on this cpu.
1130 if (!cpuhw->pmcs_enabled) {
1132 cpuhw->pmcs_enabled = 1;
1136 * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56
1138 val = mmcr0 = mfspr(SPRN_MMCR0);
1140 val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO |
1144 * The barrier is to make sure the mtspr has been
1145 * executed and the PMU has frozen the events etc.
1148 write_mmcr0(cpuhw, val);
1152 * Disable instruction sampling if it was enabled
1154 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
1156 cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1160 cpuhw->disabled = 1;
1163 ebb_switch_out(mmcr0);
1166 local_irq_restore(flags);
1170 * Re-enable all events if disable == 0.
1171 * If we were previously disabled and events were added, then
1172 * put the new config on the PMU.
1174 static void power_pmu_enable(struct pmu *pmu)
1176 struct perf_event *event;
1177 struct cpu_hw_events *cpuhw;
1178 unsigned long flags;
1180 unsigned long val, mmcr0;
1182 unsigned int hwc_index[MAX_HWEVENTS];
1189 local_irq_save(flags);
1191 cpuhw = &__get_cpu_var(cpu_hw_events);
1192 if (!cpuhw->disabled)
1195 if (cpuhw->n_events == 0) {
1196 ppc_set_pmu_inuse(0);
1200 cpuhw->disabled = 0;
1203 * EBB requires an exclusive group and all events must have the EBB
1204 * flag set, or not set, so we can just check a single event. Also we
1205 * know we have at least one event.
1207 ebb = is_ebb_event(cpuhw->event[0]);
1210 * If we didn't change anything, or only removed events,
1211 * no need to recalculate MMCR* settings and reset the PMCs.
1212 * Just reenable the PMU with the current MMCR* settings
1213 * (possibly updated for removal of events).
1215 if (!cpuhw->n_added) {
1216 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1217 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
1222 * Compute MMCR* values for the new set of events
1224 if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index,
1226 /* shouldn't ever get here */
1227 printk(KERN_ERR "oops compute_mmcr failed\n");
1232 * Add in MMCR0 freeze bits corresponding to the
1233 * attr.exclude_* bits for the first event.
1234 * We have already checked that all events have the
1235 * same values for these bits as the first event.
1237 event = cpuhw->event[0];
1238 if (event->attr.exclude_user)
1239 cpuhw->mmcr[0] |= MMCR0_FCP;
1240 if (event->attr.exclude_kernel)
1241 cpuhw->mmcr[0] |= freeze_events_kernel;
1242 if (event->attr.exclude_hv)
1243 cpuhw->mmcr[0] |= MMCR0_FCHV;
1246 * Write the new configuration to MMCR* with the freeze
1247 * bit set and set the hardware events to their initial values.
1248 * Then unfreeze the events.
1250 ppc_set_pmu_inuse(1);
1251 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1252 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
1253 mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
1257 * Read off any pre-existing events that need to move
1260 for (i = 0; i < cpuhw->n_events; ++i) {
1261 event = cpuhw->event[i];
1262 if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) {
1263 power_pmu_read(event);
1264 write_pmc(event->hw.idx, 0);
1270 * Initialize the PMCs for all the new and moved events.
1272 cpuhw->n_limited = n_lim = 0;
1273 for (i = 0; i < cpuhw->n_events; ++i) {
1274 event = cpuhw->event[i];
1277 idx = hwc_index[i] + 1;
1278 if (is_limited_pmc(idx)) {
1279 cpuhw->limited_counter[n_lim] = event;
1280 cpuhw->limited_hwidx[n_lim] = idx;
1286 val = local64_read(&event->hw.prev_count);
1289 if (event->hw.sample_period) {
1290 left = local64_read(&event->hw.period_left);
1291 if (left < 0x80000000L)
1292 val = 0x80000000L - left;
1294 local64_set(&event->hw.prev_count, val);
1297 event->hw.idx = idx;
1298 if (event->hw.state & PERF_HES_STOPPED)
1300 write_pmc(idx, val);
1302 perf_event_update_userpage(event);
1304 cpuhw->n_limited = n_lim;
1305 cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE;
1308 pmao_restore_workaround(ebb);
1310 if (ppmu->flags & PPMU_ARCH_207S)
1311 mtspr(SPRN_MMCR2, 0);
1313 mmcr0 = ebb_switch_in(ebb, cpuhw->mmcr[0]);
1316 if (cpuhw->bhrb_users)
1317 ppmu->config_bhrb(cpuhw->bhrb_filter);
1319 write_mmcr0(cpuhw, mmcr0);
1322 * Enable instruction sampling if necessary
1324 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
1326 mtspr(SPRN_MMCRA, cpuhw->mmcr[2]);
1331 local_irq_restore(flags);
1334 static int collect_events(struct perf_event *group, int max_count,
1335 struct perf_event *ctrs[], u64 *events,
1336 unsigned int *flags)
1339 struct perf_event *event;
1341 if (!is_software_event(group)) {
1345 flags[n] = group->hw.event_base;
1346 events[n++] = group->hw.config;
1348 list_for_each_entry(event, &group->sibling_list, group_entry) {
1349 if (!is_software_event(event) &&
1350 event->state != PERF_EVENT_STATE_OFF) {
1354 flags[n] = event->hw.event_base;
1355 events[n++] = event->hw.config;
1362 * Add a event to the PMU.
1363 * If all events are not already frozen, then we disable and
1364 * re-enable the PMU in order to get hw_perf_enable to do the
1365 * actual work of reconfiguring the PMU.
1367 static int power_pmu_add(struct perf_event *event, int ef_flags)
1369 struct cpu_hw_events *cpuhw;
1370 unsigned long flags;
1374 local_irq_save(flags);
1375 perf_pmu_disable(event->pmu);
1378 * Add the event to the list (if there is room)
1379 * and check whether the total set is still feasible.
1381 cpuhw = &__get_cpu_var(cpu_hw_events);
1382 n0 = cpuhw->n_events;
1383 if (n0 >= ppmu->n_counter)
1385 cpuhw->event[n0] = event;
1386 cpuhw->events[n0] = event->hw.config;
1387 cpuhw->flags[n0] = event->hw.event_base;
1390 * This event may have been disabled/stopped in record_and_restart()
1391 * because we exceeded the ->event_limit. If re-starting the event,
1392 * clear the ->hw.state (STOPPED and UPTODATE flags), so the user
1393 * notification is re-enabled.
1395 if (!(ef_flags & PERF_EF_START))
1396 event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
1398 event->hw.state = 0;
1401 * If group events scheduling transaction was started,
1402 * skip the schedulability test here, it will be performed
1403 * at commit time(->commit_txn) as a whole
1405 if (cpuhw->group_flag & PERF_EVENT_TXN)
1408 if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1))
1410 if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1))
1412 event->hw.config = cpuhw->events[n0];
1415 ebb_event_add(event);
1422 if (has_branch_stack(event)) {
1423 power_pmu_bhrb_enable(event);
1424 cpuhw->bhrb_filter = ppmu->bhrb_filter_map(
1425 event->attr.branch_sample_type);
1428 perf_pmu_enable(event->pmu);
1429 local_irq_restore(flags);
1434 * Remove a event from the PMU.
1436 static void power_pmu_del(struct perf_event *event, int ef_flags)
1438 struct cpu_hw_events *cpuhw;
1440 unsigned long flags;
1442 local_irq_save(flags);
1443 perf_pmu_disable(event->pmu);
1445 power_pmu_read(event);
1447 cpuhw = &__get_cpu_var(cpu_hw_events);
1448 for (i = 0; i < cpuhw->n_events; ++i) {
1449 if (event == cpuhw->event[i]) {
1450 while (++i < cpuhw->n_events) {
1451 cpuhw->event[i-1] = cpuhw->event[i];
1452 cpuhw->events[i-1] = cpuhw->events[i];
1453 cpuhw->flags[i-1] = cpuhw->flags[i];
1456 ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr);
1457 if (event->hw.idx) {
1458 write_pmc(event->hw.idx, 0);
1461 perf_event_update_userpage(event);
1465 for (i = 0; i < cpuhw->n_limited; ++i)
1466 if (event == cpuhw->limited_counter[i])
1468 if (i < cpuhw->n_limited) {
1469 while (++i < cpuhw->n_limited) {
1470 cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i];
1471 cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i];
1475 if (cpuhw->n_events == 0) {
1476 /* disable exceptions if no events are running */
1477 cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE);
1480 if (has_branch_stack(event))
1481 power_pmu_bhrb_disable(event);
1483 perf_pmu_enable(event->pmu);
1484 local_irq_restore(flags);
1488 * POWER-PMU does not support disabling individual counters, hence
1489 * program their cycle counter to their max value and ignore the interrupts.
1492 static void power_pmu_start(struct perf_event *event, int ef_flags)
1494 unsigned long flags;
1498 if (!event->hw.idx || !event->hw.sample_period)
1501 if (!(event->hw.state & PERF_HES_STOPPED))
1504 if (ef_flags & PERF_EF_RELOAD)
1505 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1507 local_irq_save(flags);
1508 perf_pmu_disable(event->pmu);
1510 event->hw.state = 0;
1511 left = local64_read(&event->hw.period_left);
1514 if (left < 0x80000000L)
1515 val = 0x80000000L - left;
1517 write_pmc(event->hw.idx, val);
1519 perf_event_update_userpage(event);
1520 perf_pmu_enable(event->pmu);
1521 local_irq_restore(flags);
1524 static void power_pmu_stop(struct perf_event *event, int ef_flags)
1526 unsigned long flags;
1528 if (!event->hw.idx || !event->hw.sample_period)
1531 if (event->hw.state & PERF_HES_STOPPED)
1534 local_irq_save(flags);
1535 perf_pmu_disable(event->pmu);
1537 power_pmu_read(event);
1538 event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
1539 write_pmc(event->hw.idx, 0);
1541 perf_event_update_userpage(event);
1542 perf_pmu_enable(event->pmu);
1543 local_irq_restore(flags);
1547 * Start group events scheduling transaction
1548 * Set the flag to make pmu::enable() not perform the
1549 * schedulability test, it will be performed at commit time
1551 void power_pmu_start_txn(struct pmu *pmu)
1553 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1555 perf_pmu_disable(pmu);
1556 cpuhw->group_flag |= PERF_EVENT_TXN;
1557 cpuhw->n_txn_start = cpuhw->n_events;
1561 * Stop group events scheduling transaction
1562 * Clear the flag and pmu::enable() will perform the
1563 * schedulability test.
1565 void power_pmu_cancel_txn(struct pmu *pmu)
1567 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1569 cpuhw->group_flag &= ~PERF_EVENT_TXN;
1570 perf_pmu_enable(pmu);
1574 * Commit group events scheduling transaction
1575 * Perform the group schedulability test as a whole
1576 * Return 0 if success
1578 int power_pmu_commit_txn(struct pmu *pmu)
1580 struct cpu_hw_events *cpuhw;
1585 cpuhw = &__get_cpu_var(cpu_hw_events);
1586 n = cpuhw->n_events;
1587 if (check_excludes(cpuhw->event, cpuhw->flags, 0, n))
1589 i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n);
1593 for (i = cpuhw->n_txn_start; i < n; ++i)
1594 cpuhw->event[i]->hw.config = cpuhw->events[i];
1596 cpuhw->group_flag &= ~PERF_EVENT_TXN;
1597 perf_pmu_enable(pmu);
1602 * Return 1 if we might be able to put event on a limited PMC,
1604 * A event can only go on a limited PMC if it counts something
1605 * that a limited PMC can count, doesn't require interrupts, and
1606 * doesn't exclude any processor mode.
1608 static int can_go_on_limited_pmc(struct perf_event *event, u64 ev,
1612 u64 alt[MAX_EVENT_ALTERNATIVES];
1614 if (event->attr.exclude_user
1615 || event->attr.exclude_kernel
1616 || event->attr.exclude_hv
1617 || event->attr.sample_period)
1620 if (ppmu->limited_pmc_event(ev))
1624 * The requested event_id isn't on a limited PMC already;
1625 * see if any alternative code goes on a limited PMC.
1627 if (!ppmu->get_alternatives)
1630 flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD;
1631 n = ppmu->get_alternatives(ev, flags, alt);
1637 * Find an alternative event_id that goes on a normal PMC, if possible,
1638 * and return the event_id code, or 0 if there is no such alternative.
1639 * (Note: event_id code 0 is "don't count" on all machines.)
1641 static u64 normal_pmc_alternative(u64 ev, unsigned long flags)
1643 u64 alt[MAX_EVENT_ALTERNATIVES];
1646 flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD);
1647 n = ppmu->get_alternatives(ev, flags, alt);
1653 /* Number of perf_events counting hardware events */
1654 static atomic_t num_events;
1655 /* Used to avoid races in calling reserve/release_pmc_hardware */
1656 static DEFINE_MUTEX(pmc_reserve_mutex);
1659 * Release the PMU if this is the last perf_event.
1661 static void hw_perf_event_destroy(struct perf_event *event)
1663 if (!atomic_add_unless(&num_events, -1, 1)) {
1664 mutex_lock(&pmc_reserve_mutex);
1665 if (atomic_dec_return(&num_events) == 0)
1666 release_pmc_hardware();
1667 mutex_unlock(&pmc_reserve_mutex);
1672 * Translate a generic cache event_id config to a raw event_id code.
1674 static int hw_perf_cache_event(u64 config, u64 *eventp)
1676 unsigned long type, op, result;
1679 if (!ppmu->cache_events)
1683 type = config & 0xff;
1684 op = (config >> 8) & 0xff;
1685 result = (config >> 16) & 0xff;
1687 if (type >= PERF_COUNT_HW_CACHE_MAX ||
1688 op >= PERF_COUNT_HW_CACHE_OP_MAX ||
1689 result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
1692 ev = (*ppmu->cache_events)[type][op][result];
1701 static int power_pmu_event_init(struct perf_event *event)
1704 unsigned long flags;
1705 struct perf_event *ctrs[MAX_HWEVENTS];
1706 u64 events[MAX_HWEVENTS];
1707 unsigned int cflags[MAX_HWEVENTS];
1710 struct cpu_hw_events *cpuhw;
1715 if (has_branch_stack(event)) {
1716 /* PMU has BHRB enabled */
1717 if (!(ppmu->flags & PPMU_ARCH_207S))
1721 switch (event->attr.type) {
1722 case PERF_TYPE_HARDWARE:
1723 ev = event->attr.config;
1724 if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)
1726 ev = ppmu->generic_events[ev];
1728 case PERF_TYPE_HW_CACHE:
1729 err = hw_perf_cache_event(event->attr.config, &ev);
1734 ev = event->attr.config;
1740 event->hw.config_base = ev;
1744 * If we are not running on a hypervisor, force the
1745 * exclude_hv bit to 0 so that we don't care what
1746 * the user set it to.
1748 if (!firmware_has_feature(FW_FEATURE_LPAR))
1749 event->attr.exclude_hv = 0;
1752 * If this is a per-task event, then we can use
1753 * PM_RUN_* events interchangeably with their non RUN_*
1754 * equivalents, e.g. PM_RUN_CYC instead of PM_CYC.
1755 * XXX we should check if the task is an idle task.
1758 if (event->attach_state & PERF_ATTACH_TASK)
1759 flags |= PPMU_ONLY_COUNT_RUN;
1762 * If this machine has limited events, check whether this
1763 * event_id could go on a limited event.
1765 if (ppmu->flags & PPMU_LIMITED_PMC5_6) {
1766 if (can_go_on_limited_pmc(event, ev, flags)) {
1767 flags |= PPMU_LIMITED_PMC_OK;
1768 } else if (ppmu->limited_pmc_event(ev)) {
1770 * The requested event_id is on a limited PMC,
1771 * but we can't use a limited PMC; see if any
1772 * alternative goes on a normal PMC.
1774 ev = normal_pmc_alternative(ev, flags);
1780 /* Extra checks for EBB */
1781 err = ebb_event_check(event);
1786 * If this is in a group, check if it can go on with all the
1787 * other hardware events in the group. We assume the event
1788 * hasn't been linked into its leader's sibling list at this point.
1791 if (event->group_leader != event) {
1792 n = collect_events(event->group_leader, ppmu->n_counter - 1,
1793 ctrs, events, cflags);
1800 if (check_excludes(ctrs, cflags, n, 1))
1803 cpuhw = &get_cpu_var(cpu_hw_events);
1804 err = power_check_constraints(cpuhw, events, cflags, n + 1);
1806 if (has_branch_stack(event)) {
1807 cpuhw->bhrb_filter = ppmu->bhrb_filter_map(
1808 event->attr.branch_sample_type);
1810 if(cpuhw->bhrb_filter == -1)
1814 put_cpu_var(cpu_hw_events);
1818 event->hw.config = events[n];
1819 event->hw.event_base = cflags[n];
1820 event->hw.last_period = event->hw.sample_period;
1821 local64_set(&event->hw.period_left, event->hw.last_period);
1824 * For EBB events we just context switch the PMC value, we don't do any
1825 * of the sample_period logic. We use hw.prev_count for this.
1827 if (is_ebb_event(event))
1828 local64_set(&event->hw.prev_count, 0);
1831 * See if we need to reserve the PMU.
1832 * If no events are currently in use, then we have to take a
1833 * mutex to ensure that we don't race with another task doing
1834 * reserve_pmc_hardware or release_pmc_hardware.
1837 if (!atomic_inc_not_zero(&num_events)) {
1838 mutex_lock(&pmc_reserve_mutex);
1839 if (atomic_read(&num_events) == 0 &&
1840 reserve_pmc_hardware(perf_event_interrupt))
1843 atomic_inc(&num_events);
1844 mutex_unlock(&pmc_reserve_mutex);
1846 event->destroy = hw_perf_event_destroy;
1851 static int power_pmu_event_idx(struct perf_event *event)
1853 return event->hw.idx;
1856 ssize_t power_events_sysfs_show(struct device *dev,
1857 struct device_attribute *attr, char *page)
1859 struct perf_pmu_events_attr *pmu_attr;
1861 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
1863 return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
1866 struct pmu power_pmu = {
1867 .pmu_enable = power_pmu_enable,
1868 .pmu_disable = power_pmu_disable,
1869 .event_init = power_pmu_event_init,
1870 .add = power_pmu_add,
1871 .del = power_pmu_del,
1872 .start = power_pmu_start,
1873 .stop = power_pmu_stop,
1874 .read = power_pmu_read,
1875 .start_txn = power_pmu_start_txn,
1876 .cancel_txn = power_pmu_cancel_txn,
1877 .commit_txn = power_pmu_commit_txn,
1878 .event_idx = power_pmu_event_idx,
1879 .flush_branch_stack = power_pmu_flush_branch_stack,
1883 * A counter has overflowed; update its count and record
1884 * things if requested. Note that interrupts are hard-disabled
1885 * here so there is no possibility of being interrupted.
1887 static void record_and_restart(struct perf_event *event, unsigned long val,
1888 struct pt_regs *regs)
1890 u64 period = event->hw.sample_period;
1891 s64 prev, delta, left;
1894 if (event->hw.state & PERF_HES_STOPPED) {
1895 write_pmc(event->hw.idx, 0);
1899 /* we don't have to worry about interrupts here */
1900 prev = local64_read(&event->hw.prev_count);
1901 delta = check_and_compute_delta(prev, val);
1902 local64_add(delta, &event->count);
1905 * See if the total period for this event has expired,
1906 * and update for the next period.
1909 left = local64_read(&event->hw.period_left) - delta;
1917 record = siar_valid(regs);
1918 event->hw.last_period = event->hw.sample_period;
1920 if (left < 0x80000000LL)
1921 val = 0x80000000LL - left;
1924 write_pmc(event->hw.idx, val);
1925 local64_set(&event->hw.prev_count, val);
1926 local64_set(&event->hw.period_left, left);
1927 perf_event_update_userpage(event);
1930 * Finally record data if requested.
1933 struct perf_sample_data data;
1935 perf_sample_data_init(&data, ~0ULL, event->hw.last_period);
1937 if (event->attr.sample_type & PERF_SAMPLE_ADDR)
1938 perf_get_data_addr(regs, &data.addr);
1940 if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) {
1941 struct cpu_hw_events *cpuhw;
1942 cpuhw = &__get_cpu_var(cpu_hw_events);
1943 power_pmu_bhrb_read(cpuhw);
1944 data.br_stack = &cpuhw->bhrb_stack;
1947 if (perf_event_overflow(event, &data, regs))
1948 power_pmu_stop(event, 0);
1953 * Called from generic code to get the misc flags (i.e. processor mode)
1956 unsigned long perf_misc_flags(struct pt_regs *regs)
1958 u32 flags = perf_get_misc_flags(regs);
1962 return user_mode(regs) ? PERF_RECORD_MISC_USER :
1963 PERF_RECORD_MISC_KERNEL;
1967 * Called from generic code to get the instruction pointer
1970 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1972 bool use_siar = regs_use_siar(regs);
1974 if (use_siar && siar_valid(regs))
1975 return mfspr(SPRN_SIAR) + perf_ip_adjust(regs);
1977 return 0; // no valid instruction pointer
1982 static bool pmc_overflow_power7(unsigned long val)
1985 * Events on POWER7 can roll back if a speculative event doesn't
1986 * eventually complete. Unfortunately in some rare cases they will
1987 * raise a performance monitor exception. We need to catch this to
1988 * ensure we reset the PMC. In all cases the PMC will be 256 or less
1989 * cycles from overflow.
1991 * We only do this if the first pass fails to find any overflowing
1992 * PMCs because a user might set a period of less than 256 and we
1993 * don't want to mistakenly reset them.
1995 if ((0x80000000 - val) <= 256)
2001 static bool pmc_overflow(unsigned long val)
2010 * Performance monitor interrupt stuff
2012 static void perf_event_interrupt(struct pt_regs *regs)
2015 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
2016 struct perf_event *event;
2017 unsigned long val[8];
2021 if (cpuhw->n_limited)
2022 freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5),
2025 perf_read_regs(regs);
2027 nmi = perf_intr_is_nmi(regs);
2033 /* Read all the PMCs since we'll need them a bunch of times */
2034 for (i = 0; i < ppmu->n_counter; ++i)
2035 val[i] = read_pmc(i + 1);
2037 /* Try to find what caused the IRQ */
2039 for (i = 0; i < ppmu->n_counter; ++i) {
2040 if (!pmc_overflow(val[i]))
2042 if (is_limited_pmc(i + 1))
2043 continue; /* these won't generate IRQs */
2045 * We've found one that's overflowed. For active
2046 * counters we need to log this. For inactive
2047 * counters, we need to reset it anyway
2051 for (j = 0; j < cpuhw->n_events; ++j) {
2052 event = cpuhw->event[j];
2053 if (event->hw.idx == (i + 1)) {
2055 record_and_restart(event, val[i], regs);
2060 /* reset non active counters that have overflowed */
2061 write_pmc(i + 1, 0);
2063 if (!found && pvr_version_is(PVR_POWER7)) {
2064 /* check active counters for special buggy p7 overflow */
2065 for (i = 0; i < cpuhw->n_events; ++i) {
2066 event = cpuhw->event[i];
2067 if (!event->hw.idx || is_limited_pmc(event->hw.idx))
2069 if (pmc_overflow_power7(val[event->hw.idx - 1])) {
2070 /* event has overflowed in a buggy way*/
2072 record_and_restart(event,
2073 val[event->hw.idx - 1],
2078 if (!found && !nmi && printk_ratelimit())
2079 printk(KERN_WARNING "Can't find PMC that caused IRQ\n");
2082 * Reset MMCR0 to its normal value. This will set PMXE and
2083 * clear FC (freeze counters) and PMAO (perf mon alert occurred)
2084 * and thus allow interrupts to occur again.
2085 * XXX might want to use MSR.PM to keep the events frozen until
2086 * we get back out of this interrupt.
2088 write_mmcr0(cpuhw, cpuhw->mmcr[0]);
2096 static void power_pmu_setup(int cpu)
2098 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
2102 memset(cpuhw, 0, sizeof(*cpuhw));
2103 cpuhw->mmcr[0] = MMCR0_FC;
2107 power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
2109 unsigned int cpu = (long)hcpu;
2111 switch (action & ~CPU_TASKS_FROZEN) {
2112 case CPU_UP_PREPARE:
2113 power_pmu_setup(cpu);
2123 int register_power_pmu(struct power_pmu *pmu)
2126 return -EBUSY; /* something's already registered */
2129 pr_info("%s performance monitor hardware support registered\n",
2132 power_pmu.attr_groups = ppmu->attr_groups;
2136 * Use FCHV to ignore kernel events if MSR.HV is set.
2138 if (mfmsr() & MSR_HV)
2139 freeze_events_kernel = MMCR0_FCHV;
2140 #endif /* CONFIG_PPC64 */
2142 perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW);
2143 perf_cpu_notifier(power_pmu_notifier);