arch/powerpc/perf/power8-pmu.c

   1 /*
   2  * Performance counter support for POWER8 processors.
   3  *
   4  * Copyright 2009 Paul Mackerras, IBM Corporation.
   5  * Copyright 2013 Michael Ellerman, IBM Corporation.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version
  10  * 2 of the License, or (at your option) any later version.
  11  */
  12
  13 #define pr_fmt(fmt)     "power8-pmu: " fmt
  14
  15 #include "isa207-common.h"
  16
  17 /*
  18  * Some power8 event codes.
  19  */
  20 #define EVENT(_name, _code)     _name = _code,
  21
  22 enum {
  23 #include "power8-events-list.h"
  24 };
  25
  26 #undef EVENT
  27
  28 /* MMCRA IFM bits - POWER8 */
  29 #define POWER8_MMCRA_IFM1               0x0000000040000000UL
  30 #define POWER8_MMCRA_IFM2               0x0000000080000000UL
  31 #define POWER8_MMCRA_IFM3               0x00000000C0000000UL
  32
  33 /* PowerISA v2.07 format attribute structure*/
  34 extern struct attribute_group isa207_pmu_format_group;
  35
  36 /* Table of alternatives, sorted by column 0 */
  37 static const unsigned int event_alternatives[][MAX_ALT] = {
  38         { PM_MRK_ST_CMPL,               PM_MRK_ST_CMPL_ALT },
  39         { PM_BR_MRK_2PATH,              PM_BR_MRK_2PATH_ALT },
  40         { PM_L3_CO_MEPF,                PM_L3_CO_MEPF_ALT },
  41         { PM_MRK_DATA_FROM_L2MISS,      PM_MRK_DATA_FROM_L2MISS_ALT },
  42         { PM_CMPLU_STALL_ALT,           PM_CMPLU_STALL },
  43         { PM_BR_2PATH,                  PM_BR_2PATH_ALT },
  44         { PM_INST_DISP,                 PM_INST_DISP_ALT },
  45         { PM_RUN_CYC_ALT,               PM_RUN_CYC },
  46         { PM_MRK_FILT_MATCH,            PM_MRK_FILT_MATCH_ALT },
  47         { PM_LD_MISS_L1,                PM_LD_MISS_L1_ALT },
  48         { PM_RUN_INST_CMPL_ALT,         PM_RUN_INST_CMPL },
  49 };
  50
  51 static int power8_get_alternatives(u64 event, unsigned int flags, u64 alt[])
  52 {
  53         int i, j, num_alt = 0;
  54
  55         num_alt = isa207_get_alternatives(event, alt, event_alternatives,
  56                                         (int)ARRAY_SIZE(event_alternatives));
  57         if (flags & PPMU_ONLY_COUNT_RUN) {
  58                 /*
  59                  * We're only counting in RUN state, so PM_CYC is equivalent to
  60                  * PM_RUN_CYC and PM_INST_CMPL === PM_RUN_INST_CMPL.
  61                  */
  62                 j = num_alt;
  63                 for (i = 0; i < num_alt; ++i) {
  64                         switch (alt[i]) {
  65                         case PM_CYC:
  66                                 alt[j++] = PM_RUN_CYC;
  67                                 break;
  68                         case PM_RUN_CYC:
  69                                 alt[j++] = PM_CYC;
  70                                 break;
  71                         case PM_INST_CMPL:
  72                                 alt[j++] = PM_RUN_INST_CMPL;
  73                                 break;
  74                         case PM_RUN_INST_CMPL:
  75                                 alt[j++] = PM_INST_CMPL;
  76                                 break;
  77                         }
  78                 }
  79                 num_alt = j;
  80         }
  81
  82         return num_alt;
  83 }
  84
  85 GENERIC_EVENT_ATTR(cpu-cycles,                  PM_CYC);
  86 GENERIC_EVENT_ATTR(stalled-cycles-frontend,     PM_GCT_NOSLOT_CYC);
  87 GENERIC_EVENT_ATTR(stalled-cycles-backend,      PM_CMPLU_STALL);
  88 GENERIC_EVENT_ATTR(instructions,                PM_INST_CMPL);
  89 GENERIC_EVENT_ATTR(branch-instructions,         PM_BRU_FIN);
  90 GENERIC_EVENT_ATTR(branch-misses,               PM_BR_MPRED_CMPL);
  91 GENERIC_EVENT_ATTR(cache-references,            PM_LD_REF_L1);
  92 GENERIC_EVENT_ATTR(cache-misses,                PM_LD_MISS_L1);
  93 GENERIC_EVENT_ATTR(mem_access,                  MEM_ACCESS);
  94
  95 CACHE_EVENT_ATTR(L1-dcache-load-misses,         PM_LD_MISS_L1);
  96 CACHE_EVENT_ATTR(L1-dcache-loads,               PM_LD_REF_L1);
  97
  98 CACHE_EVENT_ATTR(L1-dcache-prefetches,          PM_L1_PREF);
  99 CACHE_EVENT_ATTR(L1-dcache-store-misses,        PM_ST_MISS_L1);
 100 CACHE_EVENT_ATTR(L1-icache-load-misses,         PM_L1_ICACHE_MISS);
 101 CACHE_EVENT_ATTR(L1-icache-loads,               PM_INST_FROM_L1);
 102 CACHE_EVENT_ATTR(L1-icache-prefetches,          PM_IC_PREF_WRITE);
 103
 104 CACHE_EVENT_ATTR(LLC-load-misses,               PM_DATA_FROM_L3MISS);
 105 CACHE_EVENT_ATTR(LLC-loads,                     PM_DATA_FROM_L3);
 106 CACHE_EVENT_ATTR(LLC-prefetches,                PM_L3_PREF_ALL);
 107 CACHE_EVENT_ATTR(LLC-store-misses,              PM_L2_ST_MISS);
 108 CACHE_EVENT_ATTR(LLC-stores,                    PM_L2_ST);
 109
 110 CACHE_EVENT_ATTR(branch-load-misses,            PM_BR_MPRED_CMPL);
 111 CACHE_EVENT_ATTR(branch-loads,                  PM_BRU_FIN);
 112 CACHE_EVENT_ATTR(dTLB-load-misses,              PM_DTLB_MISS);
 113 CACHE_EVENT_ATTR(iTLB-load-misses,              PM_ITLB_MISS);
 114
 115 static struct attribute *power8_events_attr[] = {
 116         GENERIC_EVENT_PTR(PM_CYC),
 117         GENERIC_EVENT_PTR(PM_GCT_NOSLOT_CYC),
 118         GENERIC_EVENT_PTR(PM_CMPLU_STALL),
 119         GENERIC_EVENT_PTR(PM_INST_CMPL),
 120         GENERIC_EVENT_PTR(PM_BRU_FIN),
 121         GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
 122         GENERIC_EVENT_PTR(PM_LD_REF_L1),
 123         GENERIC_EVENT_PTR(PM_LD_MISS_L1),
 124         GENERIC_EVENT_PTR(MEM_ACCESS),
 125
 126         CACHE_EVENT_PTR(PM_LD_MISS_L1),
 127         CACHE_EVENT_PTR(PM_LD_REF_L1),
 128         CACHE_EVENT_PTR(PM_L1_PREF),
 129         CACHE_EVENT_PTR(PM_ST_MISS_L1),
 130         CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
 131         CACHE_EVENT_PTR(PM_INST_FROM_L1),
 132         CACHE_EVENT_PTR(PM_IC_PREF_WRITE),
 133         CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
 134         CACHE_EVENT_PTR(PM_DATA_FROM_L3),
 135         CACHE_EVENT_PTR(PM_L3_PREF_ALL),
 136         CACHE_EVENT_PTR(PM_L2_ST_MISS),
 137         CACHE_EVENT_PTR(PM_L2_ST),
 138
 139         CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
 140         CACHE_EVENT_PTR(PM_BRU_FIN),
 141
 142         CACHE_EVENT_PTR(PM_DTLB_MISS),
 143         CACHE_EVENT_PTR(PM_ITLB_MISS),
 144         NULL
 145 };
 146
 147 static struct attribute_group power8_pmu_events_group = {
 148         .name = "events",
 149         .attrs = power8_events_attr,
 150 };
 151
 152 static const struct attribute_group *power8_pmu_attr_groups[] = {
 153         &isa207_pmu_format_group,
 154         &power8_pmu_events_group,
 155         NULL,
 156 };
 157
 158 static int power8_generic_events[] = {
 159         [PERF_COUNT_HW_CPU_CYCLES] =                    PM_CYC,
 160         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =       PM_GCT_NOSLOT_CYC,
 161         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =        PM_CMPLU_STALL,
 162         [PERF_COUNT_HW_INSTRUCTIONS] =                  PM_INST_CMPL,
 163         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =           PM_BRU_FIN,
 164         [PERF_COUNT_HW_BRANCH_MISSES] =                 PM_BR_MPRED_CMPL,
 165         [PERF_COUNT_HW_CACHE_REFERENCES] =              PM_LD_REF_L1,
 166         [PERF_COUNT_HW_CACHE_MISSES] =                  PM_LD_MISS_L1,
 167 };
 168
 169 static u64 power8_bhrb_filter_map(u64 branch_sample_type)
 170 {
 171         u64 pmu_bhrb_filter = 0;
 172
 173         /* BHRB and regular PMU events share the same privilege state
 174          * filter configuration. BHRB is always recorded along with a
 175          * regular PMU event. As the privilege state filter is handled
 176          * in the basic PMC configuration of the accompanying regular
 177          * PMU event, we ignore any separate BHRB specific request.
 178          */
 179
 180         /* No branch filter requested */
 181         if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY)
 182                 return pmu_bhrb_filter;
 183
 184         /* Invalid branch filter options - HW does not support */
 185         if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
 186                 return -1;
 187
 188         if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL)
 189                 return -1;
 190
 191         if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL)
 192                 return -1;
 193
 194         if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) {
 195                 pmu_bhrb_filter |= POWER8_MMCRA_IFM1;
 196                 return pmu_bhrb_filter;
 197         }
 198
 199         /* Every thing else is unsupported */
 200         return -1;
 201 }
 202
 203 static void power8_config_bhrb(u64 pmu_bhrb_filter)
 204 {
 205         /* Enable BHRB filter in PMU */
 206         mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
 207 }
 208
 209 #define C(x)    PERF_COUNT_HW_CACHE_##x
 210
 211 /*
 212  * Table of generalized cache-related events.
 213  * 0 means not supported, -1 means nonsensical, other values
 214  * are event codes.
 215  */
 216 static int power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
 217         [ C(L1D) ] = {
 218                 [ C(OP_READ) ] = {
 219                         [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
 220                         [ C(RESULT_MISS)   ] = PM_LD_MISS_L1,
 221                 },
 222                 [ C(OP_WRITE) ] = {
 223                         [ C(RESULT_ACCESS) ] = 0,
 224                         [ C(RESULT_MISS)   ] = PM_ST_MISS_L1,
 225                 },
 226                 [ C(OP_PREFETCH) ] = {
 227                         [ C(RESULT_ACCESS) ] = PM_L1_PREF,
 228                         [ C(RESULT_MISS)   ] = 0,
 229                 },
 230         },
 231         [ C(L1I) ] = {
 232                 [ C(OP_READ) ] = {
 233                         [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
 234                         [ C(RESULT_MISS)   ] = PM_L1_ICACHE_MISS,
 235                 },
 236                 [ C(OP_WRITE) ] = {
 237                         [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
 238                         [ C(RESULT_MISS)   ] = -1,
 239                 },
 240                 [ C(OP_PREFETCH) ] = {
 241                         [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
 242                         [ C(RESULT_MISS)   ] = 0,
 243                 },
 244         },
 245         [ C(LL) ] = {
 246                 [ C(OP_READ) ] = {
 247                         [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
 248                         [ C(RESULT_MISS)   ] = PM_DATA_FROM_L3MISS,
 249                 },
 250                 [ C(OP_WRITE) ] = {
 251                         [ C(RESULT_ACCESS) ] = PM_L2_ST,
 252                         [ C(RESULT_MISS)   ] = PM_L2_ST_MISS,
 253                 },
 254                 [ C(OP_PREFETCH) ] = {
 255                         [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
 256                         [ C(RESULT_MISS)   ] = 0,
 257                 },
 258         },
 259         [ C(DTLB) ] = {
 260                 [ C(OP_READ) ] = {
 261                         [ C(RESULT_ACCESS) ] = 0,
 262                         [ C(RESULT_MISS)   ] = PM_DTLB_MISS,
 263                 },
 264                 [ C(OP_WRITE) ] = {
 265                         [ C(RESULT_ACCESS) ] = -1,
 266                         [ C(RESULT_MISS)   ] = -1,
 267                 },
 268                 [ C(OP_PREFETCH) ] = {
 269                         [ C(RESULT_ACCESS) ] = -1,
 270                         [ C(RESULT_MISS)   ] = -1,
 271                 },
 272         },
 273         [ C(ITLB) ] = {
 274                 [ C(OP_READ) ] = {
 275                         [ C(RESULT_ACCESS) ] = 0,
 276                         [ C(RESULT_MISS)   ] = PM_ITLB_MISS,
 277                 },
 278                 [ C(OP_WRITE) ] = {
 279                         [ C(RESULT_ACCESS) ] = -1,
 280                         [ C(RESULT_MISS)   ] = -1,
 281                 },
 282                 [ C(OP_PREFETCH) ] = {
 283                         [ C(RESULT_ACCESS) ] = -1,
 284                         [ C(RESULT_MISS)   ] = -1,
 285                 },
 286         },
 287         [ C(BPU) ] = {
 288                 [ C(OP_READ) ] = {
 289                         [ C(RESULT_ACCESS) ] = PM_BRU_FIN,
 290                         [ C(RESULT_MISS)   ] = PM_BR_MPRED_CMPL,
 291                 },
 292                 [ C(OP_WRITE) ] = {
 293                         [ C(RESULT_ACCESS) ] = -1,
 294                         [ C(RESULT_MISS)   ] = -1,
 295                 },
 296                 [ C(OP_PREFETCH) ] = {
 297                         [ C(RESULT_ACCESS) ] = -1,
 298                         [ C(RESULT_MISS)   ] = -1,
 299                 },
 300         },
 301         [ C(NODE) ] = {
 302                 [ C(OP_READ) ] = {
 303                         [ C(RESULT_ACCESS) ] = -1,
 304                         [ C(RESULT_MISS)   ] = -1,
 305                 },
 306                 [ C(OP_WRITE) ] = {
 307                         [ C(RESULT_ACCESS) ] = -1,
 308                         [ C(RESULT_MISS)   ] = -1,
 309                 },
 310                 [ C(OP_PREFETCH) ] = {
 311                         [ C(RESULT_ACCESS) ] = -1,
 312                         [ C(RESULT_MISS)   ] = -1,
 313                 },
 314         },
 315 };
 316
 317 #undef C
 318
 319 static struct power_pmu power8_pmu = {
 320         .name                   = "POWER8",
 321         .n_counter              = MAX_PMU_COUNTERS,
 322         .max_alternatives       = MAX_ALT + 1,
 323         .add_fields             = ISA207_ADD_FIELDS,
 324         .test_adder             = ISA207_TEST_ADDER,
 325         .compute_mmcr           = isa207_compute_mmcr,
 326         .config_bhrb            = power8_config_bhrb,
 327         .bhrb_filter_map        = power8_bhrb_filter_map,
 328         .get_constraint         = isa207_get_constraint,
 329         .get_alternatives       = power8_get_alternatives,
 330         .get_mem_data_src       = isa207_get_mem_data_src,
 331         .get_mem_weight         = isa207_get_mem_weight,
 332         .disable_pmc            = isa207_disable_pmc,
 333         .flags                  = PPMU_HAS_SIER | PPMU_ARCH_207S,
 334         .n_generic              = ARRAY_SIZE(power8_generic_events),
 335         .generic_events         = power8_generic_events,
 336         .cache_events           = &power8_cache_events,
 337         .attr_groups            = power8_pmu_attr_groups,
 338         .bhrb_nr                = 32,
 339 };
 340
 341 static int __init init_power8_pmu(void)
 342 {
 343         int rc;
 344
 345         if (!cur_cpu_spec->oprofile_cpu_type ||
 346             strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power8"))
 347                 return -ENODEV;
 348
 349         rc = register_power_pmu(&power8_pmu);
 350         if (rc)
 351                 return rc;
 352
 353         /* Tell userspace that EBB is supported */
 354         cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;
 355
 356         if (cpu_has_feature(CPU_FTR_PMAO_BUG))
 357                 pr_info("PMAO restore workaround active.\n");
 358
 359         return 0;
 360 }
 361 early_initcall(init_power8_pmu);