2 * Copyright (C) 2007,2008 Freescale Semiconductor, Inc. All rights reserved.
4 * Author: John Rigby <jrigby@freescale.com>
6 * Implements the clk api defined in include/linux/clk.h
8 * Original based on linux/arch/arm/mach-integrator/clock.c
10 * Copyright (C) 2004 ARM Limited.
11 * Written by Deep Blue Solutions Limited.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/list.h>
19 #include <linux/errno.h>
20 #include <linux/err.h>
21 #include <linux/module.h>
22 #include <linux/string.h>
23 #include <linux/clk.h>
24 #include <linux/mutex.h>
27 #include <linux/of_platform.h>
28 #include <asm/mpc5xxx.h>
29 #include <asm/clk_interface.h>
33 static int clocks_initialized;
35 #define CLK_HAS_RATE 0x1 /* has rate in MHz */
36 #define CLK_HAS_CTRL 0x2 /* has control reg and bit */
39 struct list_head node;
45 void (*calc) (struct clk *);
47 int reg, bit; /* CLK_HAS_CTRL */
48 int div_shift; /* only used by generic_div_clk_calc */
51 static LIST_HEAD(clocks);
52 static DEFINE_MUTEX(clocks_mutex);
54 static struct clk *mpc5121_clk_get(struct device *dev, const char *id)
56 struct clk *p, *clk = ERR_PTR(-ENOENT);
60 if (dev == NULL || id == NULL)
63 mutex_lock(&clocks_mutex);
64 list_for_each_entry(p, &clocks, node) {
67 if (strcmp(id, p->name) == 0)
69 if ((dev_match || id_match) && try_module_get(p->owner)) {
74 mutex_unlock(&clocks_mutex);
80 static void dump_clocks(void)
84 mutex_lock(&clocks_mutex);
85 printk(KERN_INFO "CLOCKS:\n");
86 list_for_each_entry(p, &clocks, node) {
87 pr_info(" %s=%ld", p->name, p->rate);
89 pr_cont(" %s=%ld", p->parent->name,
91 if (p->flags & CLK_HAS_CTRL)
92 pr_cont(" reg/bit=%d/%d", p->reg, p->bit);
95 mutex_unlock(&clocks_mutex);
97 #define DEBUG_CLK_DUMP() dump_clocks()
99 #define DEBUG_CLK_DUMP()
103 static void mpc5121_clk_put(struct clk *clk)
105 module_put(clk->owner);
110 struct mpc512x_clockctl {
111 u32 spmr; /* System PLL Mode Reg */
112 u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */
113 u32 scfr1; /* System Clk Freq Reg 1 */
114 u32 scfr2; /* System Clk Freq Reg 2 */
116 u32 bcr; /* Bread Crumb Reg */
117 u32 pccr[NRPSC]; /* PSC Clk Ctrl Reg 0-11 */
118 u32 spccr; /* SPDIF Clk Ctrl Reg */
119 u32 cccr; /* CFM Clk Ctrl Reg */
120 u32 dccr; /* DIU Clk Cnfg Reg */
123 struct mpc512x_clockctl __iomem *clockctl;
125 static int mpc5121_clk_enable(struct clk *clk)
129 if (clk->flags & CLK_HAS_CTRL) {
130 mask = in_be32(&clockctl->sccr[clk->reg]);
131 mask |= 1 << clk->bit;
132 out_be32(&clockctl->sccr[clk->reg], mask);
137 static void mpc5121_clk_disable(struct clk *clk)
141 if (clk->flags & CLK_HAS_CTRL) {
142 mask = in_be32(&clockctl->sccr[clk->reg]);
143 mask &= ~(1 << clk->bit);
144 out_be32(&clockctl->sccr[clk->reg], mask);
148 static unsigned long mpc5121_clk_get_rate(struct clk *clk)
150 if (clk->flags & CLK_HAS_RATE)
156 static long mpc5121_clk_round_rate(struct clk *clk, unsigned long rate)
161 static int mpc5121_clk_set_rate(struct clk *clk, unsigned long rate)
166 static int clk_register(struct clk *clk)
168 mutex_lock(&clocks_mutex);
169 list_add(&clk->node, &clocks);
170 mutex_unlock(&clocks_mutex);
174 static unsigned long spmf_mult(void)
177 * Convert spmf to multiplier
179 static int spmf_to_mult[] = {
185 int spmf = (clockctl->spmr >> 24) & 0xf;
186 return spmf_to_mult[spmf];
189 static unsigned long sysdiv_div_x_2(void)
192 * Convert sysdiv to divisor x 2
193 * Some divisors have fractional parts so
194 * multiply by 2 then divide by this value
196 static int sysdiv_to_div_x_2[] = {
207 int sysdiv = (clockctl->scfr2 >> 26) & 0x3f;
208 return sysdiv_to_div_x_2[sysdiv];
211 static unsigned long ref_to_sys(unsigned long rate)
215 rate /= sysdiv_div_x_2();
220 static unsigned long sys_to_ref(unsigned long rate)
222 rate *= sysdiv_div_x_2();
229 static long ips_to_ref(unsigned long rate)
231 int ips_div = (clockctl->scfr1 >> 23) & 0x7;
233 rate *= ips_div; /* csb_clk = ips_clk * ips_div */
234 rate *= 2; /* sys_clk = csb_clk * 2 */
235 return sys_to_ref(rate);
238 static unsigned long devtree_getfreq(char *clockname)
240 struct device_node *np;
241 const unsigned int *prop;
242 unsigned int val = 0;
244 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-immr");
246 prop = of_get_property(np, clockname, NULL);
254 static void ref_clk_calc(struct clk *clk)
258 rate = devtree_getfreq("bus-frequency");
260 printk(KERN_ERR "No bus-frequency in dev tree\n");
264 clk->rate = ips_to_ref(rate);
267 static struct clk ref_clk = {
269 .calc = ref_clk_calc,
273 static void sys_clk_calc(struct clk *clk)
275 clk->rate = ref_to_sys(ref_clk.rate);
278 static struct clk sys_clk = {
280 .calc = sys_clk_calc,
283 static void diu_clk_calc(struct clk *clk)
285 int diudiv_x_2 = clockctl->scfr1 & 0xff;
296 static void viu_clk_calc(struct clk *clk)
305 static void half_clk_calc(struct clk *clk)
307 clk->rate = clk->parent->rate / 2;
310 static void generic_div_clk_calc(struct clk *clk)
312 int div = (clockctl->scfr1 >> clk->div_shift) & 0x7;
314 clk->rate = clk->parent->rate / div;
317 static void unity_clk_calc(struct clk *clk)
319 clk->rate = clk->parent->rate;
322 static struct clk csb_clk = {
324 .calc = half_clk_calc,
328 static void e300_clk_calc(struct clk *clk)
330 int spmf = (clockctl->spmr >> 16) & 0xf;
331 int ratex2 = clk->parent->rate * spmf;
333 clk->rate = ratex2 / 2;
336 static struct clk e300_clk = {
338 .calc = e300_clk_calc,
342 static struct clk ips_clk = {
344 .calc = generic_div_clk_calc,
350 * Clocks controlled by SCCR1 (.reg = 0)
352 static struct clk lpc_clk = {
354 .flags = CLK_HAS_CTRL,
357 .calc = generic_div_clk_calc,
362 static struct clk nfc_clk = {
364 .flags = CLK_HAS_CTRL,
367 .calc = generic_div_clk_calc,
372 static struct clk pata_clk = {
374 .flags = CLK_HAS_CTRL,
377 .calc = unity_clk_calc,
382 * PSC clocks (bits 27 - 16)
383 * are setup elsewhere
386 static struct clk sata_clk = {
388 .flags = CLK_HAS_CTRL,
391 .calc = unity_clk_calc,
395 static struct clk fec_clk = {
397 .flags = CLK_HAS_CTRL,
400 .calc = unity_clk_calc,
404 static struct clk pci_clk = {
406 .flags = CLK_HAS_CTRL,
409 .calc = generic_div_clk_calc,
415 * Clocks controlled by SCCR2 (.reg = 1)
417 static struct clk diu_clk = {
419 .flags = CLK_HAS_CTRL,
422 .calc = diu_clk_calc,
425 static struct clk viu_clk = {
427 .flags = CLK_HAS_CTRL,
430 .calc = viu_clk_calc,
433 static struct clk axe_clk = {
435 .flags = CLK_HAS_CTRL,
438 .calc = unity_clk_calc,
442 static struct clk usb1_clk = {
444 .flags = CLK_HAS_CTRL,
447 .calc = unity_clk_calc,
451 static struct clk usb2_clk = {
453 .flags = CLK_HAS_CTRL,
456 .calc = unity_clk_calc,
460 static struct clk i2c_clk = {
462 .flags = CLK_HAS_CTRL,
465 .calc = unity_clk_calc,
469 static struct clk mscan_clk = {
471 .flags = CLK_HAS_CTRL,
474 .calc = unity_clk_calc,
478 static struct clk sdhc_clk = {
480 .flags = CLK_HAS_CTRL,
483 .calc = unity_clk_calc,
487 static struct clk mbx_bus_clk = {
488 .name = "mbx_bus_clk",
489 .flags = CLK_HAS_CTRL,
492 .calc = half_clk_calc,
496 static struct clk mbx_clk = {
498 .flags = CLK_HAS_CTRL,
501 .calc = unity_clk_calc,
505 static struct clk mbx_3d_clk = {
506 .name = "mbx_3d_clk",
507 .flags = CLK_HAS_CTRL,
510 .calc = generic_div_clk_calc,
511 .parent = &mbx_bus_clk,
515 static void psc_mclk_in_calc(struct clk *clk)
517 clk->rate = devtree_getfreq("psc_mclk_in");
519 clk->rate = 25000000;
522 static struct clk psc_mclk_in = {
523 .name = "psc_mclk_in",
524 .calc = psc_mclk_in_calc,
527 static struct clk spdif_txclk = {
528 .name = "spdif_txclk",
529 .flags = CLK_HAS_CTRL,
534 static struct clk spdif_rxclk = {
535 .name = "spdif_rxclk",
536 .flags = CLK_HAS_CTRL,
541 static void ac97_clk_calc(struct clk *clk)
543 /* ac97 bit clock is always 24.567 MHz */
544 clk->rate = 24567000;
547 static struct clk ac97_clk = {
548 .name = "ac97_clk_in",
549 .calc = ac97_clk_calc,
552 struct clk *rate_clks[] = {
582 static void rate_clk_init(struct clk *clk)
586 clk->flags |= CLK_HAS_RATE;
590 "Could not initialize clk %s without a calc routine\n",
595 static void rate_clks_init(void)
597 struct clk **cpp, *clk;
600 while ((clk = *cpp++))
605 * There are two clk enable registers with 32 enable bits each
606 * psc clocks and device clocks are all stored in dev_clks
608 struct clk dev_clks[2][32];
611 * Given a psc number return the dev_clk
614 static struct clk *psc_dev_clk(int pscnum)
622 clk = &dev_clks[reg][bit];
629 * PSC clock rate calculation
631 static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
633 unsigned long mclk_src = sys_clk.rate;
634 unsigned long mclk_div;
637 * Can only change value of mclk divider
638 * when the divider is disabled.
640 * Zero is not a valid divider so minimum
643 * disable/set divider/enable
645 out_be32(&clockctl->pccr[pscnum], 0);
646 out_be32(&clockctl->pccr[pscnum], 0x00020000);
647 out_be32(&clockctl->pccr[pscnum], 0x00030000);
649 if (clockctl->pccr[pscnum] & 0x80) {
650 clk->rate = spdif_rxclk.rate;
654 switch ((clockctl->pccr[pscnum] >> 14) & 0x3) {
656 mclk_src = sys_clk.rate;
659 mclk_src = ref_clk.rate;
662 mclk_src = psc_mclk_in.rate;
665 mclk_src = spdif_txclk.rate;
669 mclk_div = ((clockctl->pccr[pscnum] >> 17) & 0x7fff) + 1;
670 clk->rate = mclk_src / mclk_div;
674 * Find all psc nodes in device tree and assign a clock
675 * with name "psc%d_mclk" and dev pointing at the device
676 * returned from of_find_device_by_node
678 static void psc_clks_init(void)
680 struct device_node *np;
681 const u32 *cell_index;
682 struct platform_device *ofdev;
684 for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
685 cell_index = of_get_property(np, "cell-index", NULL);
687 int pscnum = *cell_index;
688 struct clk *clk = psc_dev_clk(pscnum);
690 clk->flags = CLK_HAS_RATE | CLK_HAS_CTRL;
691 ofdev = of_find_device_by_node(np);
692 clk->dev = &ofdev->dev;
694 * AC97 is special rate clock does
695 * not go through normal path
697 if (strcmp("ac97", np->name) == 0)
698 clk->rate = ac97_clk.rate;
700 psc_calc_rate(clk, pscnum, np);
701 sprintf(clk->name, "psc%d_mclk", pscnum);
708 static struct clk_interface mpc5121_clk_functions = {
709 .clk_get = mpc5121_clk_get,
710 .clk_enable = mpc5121_clk_enable,
711 .clk_disable = mpc5121_clk_disable,
712 .clk_get_rate = mpc5121_clk_get_rate,
713 .clk_put = mpc5121_clk_put,
714 .clk_round_rate = mpc5121_clk_round_rate,
715 .clk_set_rate = mpc5121_clk_set_rate,
716 .clk_set_parent = NULL,
717 .clk_get_parent = NULL,
720 int __init mpc5121_clk_init(void)
722 struct device_node *np;
724 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
726 clockctl = of_iomap(np, 0);
731 printk(KERN_ERR "Could not map clock control registers\n");
738 /* leave clockctl mapped forever */
739 /*iounmap(clockctl); */
741 clocks_initialized++;
742 clk_functions = mpc5121_clk_functions;