2 * Copyright (C) 2007,2008 Freescale Semiconductor, Inc. All rights reserved.
4 * Author: John Rigby <jrigby@freescale.com>
6 * Implements the clk api defined in include/linux/clk.h
8 * Original based on linux/arch/arm/mach-integrator/clock.c
10 * Copyright (C) 2004 ARM Limited.
11 * Written by Deep Blue Solutions Limited.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/list.h>
19 #include <linux/errno.h>
20 #include <linux/err.h>
21 #include <linux/module.h>
22 #include <linux/string.h>
23 #include <linux/clk.h>
24 #include <linux/mutex.h>
27 #include <linux/of_address.h>
28 #include <linux/of_platform.h>
29 #include <asm/mpc5xxx.h>
30 #include <asm/mpc5121.h>
31 #include <asm/clk_interface.h>
37 static int clocks_initialized;
39 #define CLK_HAS_RATE 0x1 /* has rate in MHz */
40 #define CLK_HAS_CTRL 0x2 /* has control reg and bit */
43 struct list_head node;
49 void (*calc) (struct clk *);
51 int reg, bit; /* CLK_HAS_CTRL */
52 int div_shift; /* only used by generic_div_clk_calc */
55 static LIST_HEAD(clocks);
56 static DEFINE_MUTEX(clocks_mutex);
58 static struct clk *mpc5121_clk_get(struct device *dev, const char *id)
60 struct clk *p, *clk = ERR_PTR(-ENOENT);
64 if (dev == NULL || id == NULL)
67 mutex_lock(&clocks_mutex);
68 list_for_each_entry(p, &clocks, node) {
69 dev_match = id_match = 0;
73 if (strcmp(id, p->name) == 0)
75 if ((dev_match || id_match) && try_module_get(p->owner)) {
80 mutex_unlock(&clocks_mutex);
86 static void dump_clocks(void)
90 mutex_lock(&clocks_mutex);
91 printk(KERN_INFO "CLOCKS:\n");
92 list_for_each_entry(p, &clocks, node) {
93 pr_info(" %s=%ld", p->name, p->rate);
95 pr_cont(" %s=%ld", p->parent->name,
97 if (p->flags & CLK_HAS_CTRL)
98 pr_cont(" reg/bit=%d/%d", p->reg, p->bit);
101 mutex_unlock(&clocks_mutex);
103 #define DEBUG_CLK_DUMP() dump_clocks()
105 #define DEBUG_CLK_DUMP()
109 static void mpc5121_clk_put(struct clk *clk)
111 module_put(clk->owner);
116 struct mpc512x_clockctl {
117 u32 spmr; /* System PLL Mode Reg */
118 u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */
119 u32 scfr1; /* System Clk Freq Reg 1 */
120 u32 scfr2; /* System Clk Freq Reg 2 */
122 u32 bcr; /* Bread Crumb Reg */
123 u32 pccr[NRPSC]; /* PSC Clk Ctrl Reg 0-11 */
124 u32 spccr; /* SPDIF Clk Ctrl Reg */
125 u32 cccr; /* CFM Clk Ctrl Reg */
126 u32 dccr; /* DIU Clk Cnfg Reg */
129 static struct mpc512x_clockctl __iomem *clockctl;
131 static int mpc5121_clk_enable(struct clk *clk)
135 if (clk->flags & CLK_HAS_CTRL) {
136 mask = in_be32(&clockctl->sccr[clk->reg]);
137 mask |= 1 << clk->bit;
138 out_be32(&clockctl->sccr[clk->reg], mask);
143 static void mpc5121_clk_disable(struct clk *clk)
147 if (clk->flags & CLK_HAS_CTRL) {
148 mask = in_be32(&clockctl->sccr[clk->reg]);
149 mask &= ~(1 << clk->bit);
150 out_be32(&clockctl->sccr[clk->reg], mask);
154 static unsigned long mpc5121_clk_get_rate(struct clk *clk)
156 if (clk->flags & CLK_HAS_RATE)
162 static long mpc5121_clk_round_rate(struct clk *clk, unsigned long rate)
167 static int mpc5121_clk_set_rate(struct clk *clk, unsigned long rate)
172 static int clk_register(struct clk *clk)
174 mutex_lock(&clocks_mutex);
175 list_add(&clk->node, &clocks);
176 mutex_unlock(&clocks_mutex);
180 static unsigned long spmf_mult(void)
183 * Convert spmf to multiplier
185 static int spmf_to_mult[] = {
191 int spmf = (in_be32(&clockctl->spmr) >> 24) & 0xf;
192 return spmf_to_mult[spmf];
195 static unsigned long sysdiv_div_x_2(void)
198 * Convert sysdiv to divisor x 2
199 * Some divisors have fractional parts so
200 * multiply by 2 then divide by this value
202 static int sysdiv_to_div_x_2[] = {
213 int sysdiv = (in_be32(&clockctl->scfr2) >> 26) & 0x3f;
214 return sysdiv_to_div_x_2[sysdiv];
217 static unsigned long ref_to_sys(unsigned long rate)
221 rate /= sysdiv_div_x_2();
226 static unsigned long sys_to_ref(unsigned long rate)
228 rate *= sysdiv_div_x_2();
235 static long ips_to_ref(unsigned long rate)
237 int ips_div = (in_be32(&clockctl->scfr1) >> 23) & 0x7;
239 rate *= ips_div; /* csb_clk = ips_clk * ips_div */
240 rate *= 2; /* sys_clk = csb_clk * 2 */
241 return sys_to_ref(rate);
244 static unsigned long devtree_getfreq(char *clockname)
246 struct device_node *np;
247 const unsigned int *prop;
248 unsigned int val = 0;
250 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-immr");
252 prop = of_get_property(np, clockname, NULL);
260 static void ref_clk_calc(struct clk *clk)
264 rate = devtree_getfreq("bus-frequency");
266 printk(KERN_ERR "No bus-frequency in dev tree\n");
270 clk->rate = ips_to_ref(rate);
273 static struct clk ref_clk = {
275 .calc = ref_clk_calc,
279 static void sys_clk_calc(struct clk *clk)
281 clk->rate = ref_to_sys(ref_clk.rate);
284 static struct clk sys_clk = {
286 .calc = sys_clk_calc,
289 static void diu_clk_calc(struct clk *clk)
291 int diudiv_x_2 = in_be32(&clockctl->scfr1) & 0xff;
302 static void viu_clk_calc(struct clk *clk)
311 static void half_clk_calc(struct clk *clk)
313 clk->rate = clk->parent->rate / 2;
316 static void generic_div_clk_calc(struct clk *clk)
318 int div = (in_be32(&clockctl->scfr1) >> clk->div_shift) & 0x7;
320 clk->rate = clk->parent->rate / div;
323 static void unity_clk_calc(struct clk *clk)
325 clk->rate = clk->parent->rate;
328 static struct clk csb_clk = {
330 .calc = half_clk_calc,
334 static void e300_clk_calc(struct clk *clk)
336 int spmf = (in_be32(&clockctl->spmr) >> 16) & 0xf;
337 int ratex2 = clk->parent->rate * spmf;
339 clk->rate = ratex2 / 2;
342 static struct clk e300_clk = {
344 .calc = e300_clk_calc,
348 static struct clk ips_clk = {
350 .calc = generic_div_clk_calc,
356 * Clocks controlled by SCCR1 (.reg = 0)
358 static struct clk lpc_clk = {
360 .flags = CLK_HAS_CTRL,
363 .calc = generic_div_clk_calc,
368 static struct clk nfc_clk = {
370 .flags = CLK_HAS_CTRL,
373 .calc = generic_div_clk_calc,
378 static struct clk pata_clk = {
380 .flags = CLK_HAS_CTRL,
383 .calc = unity_clk_calc,
388 * PSC clocks (bits 27 - 16)
389 * are setup elsewhere
392 static struct clk sata_clk = {
394 .flags = CLK_HAS_CTRL,
397 .calc = unity_clk_calc,
401 static struct clk fec_clk = {
403 .flags = CLK_HAS_CTRL,
406 .calc = unity_clk_calc,
410 static struct clk pci_clk = {
412 .flags = CLK_HAS_CTRL,
415 .calc = generic_div_clk_calc,
421 * Clocks controlled by SCCR2 (.reg = 1)
423 static struct clk diu_clk = {
425 .flags = CLK_HAS_CTRL,
428 .calc = diu_clk_calc,
431 static struct clk viu_clk = {
433 .flags = CLK_HAS_CTRL,
436 .calc = viu_clk_calc,
439 static struct clk axe_clk = {
441 .flags = CLK_HAS_CTRL,
444 .calc = unity_clk_calc,
448 static struct clk usb1_clk = {
450 .flags = CLK_HAS_CTRL,
453 .calc = unity_clk_calc,
457 static struct clk usb2_clk = {
459 .flags = CLK_HAS_CTRL,
462 .calc = unity_clk_calc,
466 static struct clk i2c_clk = {
468 .flags = CLK_HAS_CTRL,
471 .calc = unity_clk_calc,
475 static struct clk mscan_clk = {
477 .flags = CLK_HAS_CTRL,
480 .calc = unity_clk_calc,
484 static struct clk sdhc_clk = {
486 .flags = CLK_HAS_CTRL,
489 .calc = unity_clk_calc,
493 static struct clk mbx_bus_clk = {
494 .name = "mbx_bus_clk",
495 .flags = CLK_HAS_CTRL,
498 .calc = half_clk_calc,
502 static struct clk mbx_clk = {
504 .flags = CLK_HAS_CTRL,
507 .calc = unity_clk_calc,
511 static struct clk mbx_3d_clk = {
512 .name = "mbx_3d_clk",
513 .flags = CLK_HAS_CTRL,
516 .calc = generic_div_clk_calc,
517 .parent = &mbx_bus_clk,
521 static void psc_mclk_in_calc(struct clk *clk)
523 clk->rate = devtree_getfreq("psc_mclk_in");
525 clk->rate = 25000000;
528 static struct clk psc_mclk_in = {
529 .name = "psc_mclk_in",
530 .calc = psc_mclk_in_calc,
533 static struct clk spdif_txclk = {
534 .name = "spdif_txclk",
535 .flags = CLK_HAS_CTRL,
540 static struct clk spdif_rxclk = {
541 .name = "spdif_rxclk",
542 .flags = CLK_HAS_CTRL,
547 static void ac97_clk_calc(struct clk *clk)
549 /* ac97 bit clock is always 24.567 MHz */
550 clk->rate = 24567000;
553 static struct clk ac97_clk = {
554 .name = "ac97_clk_in",
555 .calc = ac97_clk_calc,
558 static struct clk *rate_clks[] = {
588 static void rate_clk_init(struct clk *clk)
592 clk->flags |= CLK_HAS_RATE;
596 "Could not initialize clk %s without a calc routine\n",
601 static void rate_clks_init(void)
603 struct clk **cpp, *clk;
606 while ((clk = *cpp++))
611 * There are two clk enable registers with 32 enable bits each
612 * psc clocks and device clocks are all stored in dev_clks
614 static struct clk dev_clks[2][32];
617 * Given a psc number return the dev_clk
620 static struct clk *psc_dev_clk(int pscnum)
628 clk = &dev_clks[reg][bit];
635 * PSC clock rate calculation
637 static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
639 unsigned long mclk_src = sys_clk.rate;
640 unsigned long mclk_div;
643 * Can only change value of mclk divider
644 * when the divider is disabled.
646 * Zero is not a valid divider so minimum
649 * disable/set divider/enable
651 out_be32(&clockctl->pccr[pscnum], 0);
652 out_be32(&clockctl->pccr[pscnum], 0x00020000);
653 out_be32(&clockctl->pccr[pscnum], 0x00030000);
655 if (in_be32(&clockctl->pccr[pscnum]) & 0x80) {
656 clk->rate = spdif_rxclk.rate;
660 switch ((in_be32(&clockctl->pccr[pscnum]) >> 14) & 0x3) {
662 mclk_src = sys_clk.rate;
665 mclk_src = ref_clk.rate;
668 mclk_src = psc_mclk_in.rate;
671 mclk_src = spdif_txclk.rate;
675 mclk_div = ((in_be32(&clockctl->pccr[pscnum]) >> 17) & 0x7fff) + 1;
676 clk->rate = mclk_src / mclk_div;
680 * Find all psc nodes in device tree and assign a clock
681 * with name "psc%d_mclk" and dev pointing at the device
682 * returned from of_find_device_by_node
684 static void psc_clks_init(void)
686 struct device_node *np;
687 struct platform_device *ofdev;
689 const char *psc_compat;
691 psc_compat = mpc512x_select_psc_compat();
695 for_each_compatible_node(np, NULL, psc_compat) {
696 if (!of_property_read_u32(np, "reg", ®)) {
697 int pscnum = (reg & 0xf00) >> 8;
698 struct clk *clk = psc_dev_clk(pscnum);
700 clk->flags = CLK_HAS_RATE | CLK_HAS_CTRL;
701 ofdev = of_find_device_by_node(np);
702 clk->dev = &ofdev->dev;
704 * AC97 is special rate clock does
705 * not go through normal path
707 if (of_device_is_compatible(np, "fsl,mpc5121-psc-ac97"))
708 clk->rate = ac97_clk.rate;
710 psc_calc_rate(clk, pscnum, np);
711 sprintf(clk->name, "psc%d_mclk", pscnum);
718 static struct clk_interface mpc5121_clk_functions = {
719 .clk_get = mpc5121_clk_get,
720 .clk_enable = mpc5121_clk_enable,
721 .clk_disable = mpc5121_clk_disable,
722 .clk_get_rate = mpc5121_clk_get_rate,
723 .clk_put = mpc5121_clk_put,
724 .clk_round_rate = mpc5121_clk_round_rate,
725 .clk_set_rate = mpc5121_clk_set_rate,
726 .clk_set_parent = NULL,
727 .clk_get_parent = NULL,
730 int __init mpc5121_clk_init(void)
732 struct device_node *np;
734 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
736 clockctl = of_iomap(np, 0);
741 printk(KERN_ERR "Could not map clock control registers\n");
748 /* leave clockctl mapped forever */
749 /*iounmap(clockctl); */
751 clocks_initialized++;
752 clk_functions = mpc5121_clk_functions;