2 * Copyright (C) 2007,2008 Freescale Semiconductor, Inc. All rights reserved.
4 * Author: John Rigby <jrigby@freescale.com>
6 * Implements the clk api defined in include/linux/clk.h
8 * Original based on linux/arch/arm/mach-integrator/clock.c
10 * Copyright (C) 2004 ARM Limited.
11 * Written by Deep Blue Solutions Limited.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/list.h>
19 #include <linux/errno.h>
20 #include <linux/err.h>
21 #include <linux/string.h>
22 #include <linux/clk.h>
23 #include <linux/mutex.h>
26 #include <linux/of_platform.h>
27 #include <asm/mpc5xxx.h>
28 #include <asm/clk_interface.h>
32 static int clocks_initialized;
34 #define CLK_HAS_RATE 0x1 /* has rate in MHz */
35 #define CLK_HAS_CTRL 0x2 /* has control reg and bit */
38 struct list_head node;
44 void (*calc) (struct clk *);
46 int reg, bit; /* CLK_HAS_CTRL */
47 int div_shift; /* only used by generic_div_clk_calc */
50 static LIST_HEAD(clocks);
51 static DEFINE_MUTEX(clocks_mutex);
53 static struct clk *mpc5121_clk_get(struct device *dev, const char *id)
55 struct clk *p, *clk = ERR_PTR(-ENOENT);
59 if (dev == NULL || id == NULL)
62 mutex_lock(&clocks_mutex);
63 list_for_each_entry(p, &clocks, node) {
66 if (strcmp(id, p->name) == 0)
68 if ((dev_match || id_match) && try_module_get(p->owner)) {
73 mutex_unlock(&clocks_mutex);
79 static void dump_clocks(void)
83 mutex_lock(&clocks_mutex);
84 printk(KERN_INFO "CLOCKS:\n");
85 list_for_each_entry(p, &clocks, node) {
86 pr_info(" %s=%ld", p->name, p->rate);
88 pr_cont(" %s=%ld", p->parent->name,
90 if (p->flags & CLK_HAS_CTRL)
91 pr_cont(" reg/bit=%d/%d", p->reg, p->bit);
94 mutex_unlock(&clocks_mutex);
96 #define DEBUG_CLK_DUMP() dump_clocks()
98 #define DEBUG_CLK_DUMP()
102 static void mpc5121_clk_put(struct clk *clk)
104 module_put(clk->owner);
109 struct mpc512x_clockctl {
110 u32 spmr; /* System PLL Mode Reg */
111 u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */
112 u32 scfr1; /* System Clk Freq Reg 1 */
113 u32 scfr2; /* System Clk Freq Reg 2 */
115 u32 bcr; /* Bread Crumb Reg */
116 u32 pccr[NRPSC]; /* PSC Clk Ctrl Reg 0-11 */
117 u32 spccr; /* SPDIF Clk Ctrl Reg */
118 u32 cccr; /* CFM Clk Ctrl Reg */
119 u32 dccr; /* DIU Clk Cnfg Reg */
122 struct mpc512x_clockctl __iomem *clockctl;
124 static int mpc5121_clk_enable(struct clk *clk)
128 if (clk->flags & CLK_HAS_CTRL) {
129 mask = in_be32(&clockctl->sccr[clk->reg]);
130 mask |= 1 << clk->bit;
131 out_be32(&clockctl->sccr[clk->reg], mask);
136 static void mpc5121_clk_disable(struct clk *clk)
140 if (clk->flags & CLK_HAS_CTRL) {
141 mask = in_be32(&clockctl->sccr[clk->reg]);
142 mask &= ~(1 << clk->bit);
143 out_be32(&clockctl->sccr[clk->reg], mask);
147 static unsigned long mpc5121_clk_get_rate(struct clk *clk)
149 if (clk->flags & CLK_HAS_RATE)
155 static long mpc5121_clk_round_rate(struct clk *clk, unsigned long rate)
160 static int mpc5121_clk_set_rate(struct clk *clk, unsigned long rate)
165 static int clk_register(struct clk *clk)
167 mutex_lock(&clocks_mutex);
168 list_add(&clk->node, &clocks);
169 mutex_unlock(&clocks_mutex);
173 static unsigned long spmf_mult(void)
176 * Convert spmf to multiplier
178 static int spmf_to_mult[] = {
184 int spmf = (clockctl->spmr >> 24) & 0xf;
185 return spmf_to_mult[spmf];
188 static unsigned long sysdiv_div_x_2(void)
191 * Convert sysdiv to divisor x 2
192 * Some divisors have fractional parts so
193 * multiply by 2 then divide by this value
195 static int sysdiv_to_div_x_2[] = {
206 int sysdiv = (clockctl->scfr2 >> 26) & 0x3f;
207 return sysdiv_to_div_x_2[sysdiv];
210 static unsigned long ref_to_sys(unsigned long rate)
214 rate /= sysdiv_div_x_2();
219 static unsigned long sys_to_ref(unsigned long rate)
221 rate *= sysdiv_div_x_2();
228 static long ips_to_ref(unsigned long rate)
230 int ips_div = (clockctl->scfr1 >> 23) & 0x7;
232 rate *= ips_div; /* csb_clk = ips_clk * ips_div */
233 rate *= 2; /* sys_clk = csb_clk * 2 */
234 return sys_to_ref(rate);
237 static unsigned long devtree_getfreq(char *clockname)
239 struct device_node *np;
240 const unsigned int *prop;
241 unsigned int val = 0;
243 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-immr");
245 prop = of_get_property(np, clockname, NULL);
253 static void ref_clk_calc(struct clk *clk)
257 rate = devtree_getfreq("bus-frequency");
259 printk(KERN_ERR "No bus-frequency in dev tree\n");
263 clk->rate = ips_to_ref(rate);
266 static struct clk ref_clk = {
268 .calc = ref_clk_calc,
272 static void sys_clk_calc(struct clk *clk)
274 clk->rate = ref_to_sys(ref_clk.rate);
277 static struct clk sys_clk = {
279 .calc = sys_clk_calc,
282 static void diu_clk_calc(struct clk *clk)
284 int diudiv_x_2 = clockctl->scfr1 & 0xff;
295 static void viu_clk_calc(struct clk *clk)
304 static void half_clk_calc(struct clk *clk)
306 clk->rate = clk->parent->rate / 2;
309 static void generic_div_clk_calc(struct clk *clk)
311 int div = (clockctl->scfr1 >> clk->div_shift) & 0x7;
313 clk->rate = clk->parent->rate / div;
316 static void unity_clk_calc(struct clk *clk)
318 clk->rate = clk->parent->rate;
321 static struct clk csb_clk = {
323 .calc = half_clk_calc,
327 static void e300_clk_calc(struct clk *clk)
329 int spmf = (clockctl->spmr >> 16) & 0xf;
330 int ratex2 = clk->parent->rate * spmf;
332 clk->rate = ratex2 / 2;
335 static struct clk e300_clk = {
337 .calc = e300_clk_calc,
341 static struct clk ips_clk = {
343 .calc = generic_div_clk_calc,
349 * Clocks controlled by SCCR1 (.reg = 0)
351 static struct clk lpc_clk = {
353 .flags = CLK_HAS_CTRL,
356 .calc = generic_div_clk_calc,
361 static struct clk nfc_clk = {
363 .flags = CLK_HAS_CTRL,
366 .calc = generic_div_clk_calc,
371 static struct clk pata_clk = {
373 .flags = CLK_HAS_CTRL,
376 .calc = unity_clk_calc,
381 * PSC clocks (bits 27 - 16)
382 * are setup elsewhere
385 static struct clk sata_clk = {
387 .flags = CLK_HAS_CTRL,
390 .calc = unity_clk_calc,
394 static struct clk fec_clk = {
396 .flags = CLK_HAS_CTRL,
399 .calc = unity_clk_calc,
403 static struct clk pci_clk = {
405 .flags = CLK_HAS_CTRL,
408 .calc = generic_div_clk_calc,
414 * Clocks controlled by SCCR2 (.reg = 1)
416 static struct clk diu_clk = {
418 .flags = CLK_HAS_CTRL,
421 .calc = diu_clk_calc,
424 static struct clk viu_clk = {
426 .flags = CLK_HAS_CTRL,
429 .calc = viu_clk_calc,
432 static struct clk axe_clk = {
434 .flags = CLK_HAS_CTRL,
437 .calc = unity_clk_calc,
441 static struct clk usb1_clk = {
443 .flags = CLK_HAS_CTRL,
446 .calc = unity_clk_calc,
450 static struct clk usb2_clk = {
452 .flags = CLK_HAS_CTRL,
455 .calc = unity_clk_calc,
459 static struct clk i2c_clk = {
461 .flags = CLK_HAS_CTRL,
464 .calc = unity_clk_calc,
468 static struct clk mscan_clk = {
470 .flags = CLK_HAS_CTRL,
473 .calc = unity_clk_calc,
477 static struct clk sdhc_clk = {
479 .flags = CLK_HAS_CTRL,
482 .calc = unity_clk_calc,
486 static struct clk mbx_bus_clk = {
487 .name = "mbx_bus_clk",
488 .flags = CLK_HAS_CTRL,
491 .calc = half_clk_calc,
495 static struct clk mbx_clk = {
497 .flags = CLK_HAS_CTRL,
500 .calc = unity_clk_calc,
504 static struct clk mbx_3d_clk = {
505 .name = "mbx_3d_clk",
506 .flags = CLK_HAS_CTRL,
509 .calc = generic_div_clk_calc,
510 .parent = &mbx_bus_clk,
514 static void psc_mclk_in_calc(struct clk *clk)
516 clk->rate = devtree_getfreq("psc_mclk_in");
518 clk->rate = 25000000;
521 static struct clk psc_mclk_in = {
522 .name = "psc_mclk_in",
523 .calc = psc_mclk_in_calc,
526 static struct clk spdif_txclk = {
527 .name = "spdif_txclk",
528 .flags = CLK_HAS_CTRL,
533 static struct clk spdif_rxclk = {
534 .name = "spdif_rxclk",
535 .flags = CLK_HAS_CTRL,
540 static void ac97_clk_calc(struct clk *clk)
542 /* ac97 bit clock is always 24.567 MHz */
543 clk->rate = 24567000;
546 static struct clk ac97_clk = {
547 .name = "ac97_clk_in",
548 .calc = ac97_clk_calc,
551 struct clk *rate_clks[] = {
581 static void rate_clk_init(struct clk *clk)
585 clk->flags |= CLK_HAS_RATE;
589 "Could not initialize clk %s without a calc routine\n",
594 static void rate_clks_init(void)
596 struct clk **cpp, *clk;
599 while ((clk = *cpp++))
604 * There are two clk enable registers with 32 enable bits each
605 * psc clocks and device clocks are all stored in dev_clks
607 struct clk dev_clks[2][32];
610 * Given a psc number return the dev_clk
613 static struct clk *psc_dev_clk(int pscnum)
621 clk = &dev_clks[reg][bit];
628 * PSC clock rate calculation
630 static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
632 unsigned long mclk_src = sys_clk.rate;
633 unsigned long mclk_div;
636 * Can only change value of mclk divider
637 * when the divider is disabled.
639 * Zero is not a valid divider so minimum
642 * disable/set divider/enable
644 out_be32(&clockctl->pccr[pscnum], 0);
645 out_be32(&clockctl->pccr[pscnum], 0x00020000);
646 out_be32(&clockctl->pccr[pscnum], 0x00030000);
648 if (clockctl->pccr[pscnum] & 0x80) {
649 clk->rate = spdif_rxclk.rate;
653 switch ((clockctl->pccr[pscnum] >> 14) & 0x3) {
655 mclk_src = sys_clk.rate;
658 mclk_src = ref_clk.rate;
661 mclk_src = psc_mclk_in.rate;
664 mclk_src = spdif_txclk.rate;
668 mclk_div = ((clockctl->pccr[pscnum] >> 17) & 0x7fff) + 1;
669 clk->rate = mclk_src / mclk_div;
673 * Find all psc nodes in device tree and assign a clock
674 * with name "psc%d_mclk" and dev pointing at the device
675 * returned from of_find_device_by_node
677 static void psc_clks_init(void)
679 struct device_node *np;
680 const u32 *cell_index;
681 struct platform_device *ofdev;
683 for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
684 cell_index = of_get_property(np, "cell-index", NULL);
686 int pscnum = *cell_index;
687 struct clk *clk = psc_dev_clk(pscnum);
689 clk->flags = CLK_HAS_RATE | CLK_HAS_CTRL;
690 ofdev = of_find_device_by_node(np);
691 clk->dev = &ofdev->dev;
693 * AC97 is special rate clock does
694 * not go through normal path
696 if (strcmp("ac97", np->name) == 0)
697 clk->rate = ac97_clk.rate;
699 psc_calc_rate(clk, pscnum, np);
700 sprintf(clk->name, "psc%d_mclk", pscnum);
707 static struct clk_interface mpc5121_clk_functions = {
708 .clk_get = mpc5121_clk_get,
709 .clk_enable = mpc5121_clk_enable,
710 .clk_disable = mpc5121_clk_disable,
711 .clk_get_rate = mpc5121_clk_get_rate,
712 .clk_put = mpc5121_clk_put,
713 .clk_round_rate = mpc5121_clk_round_rate,
714 .clk_set_rate = mpc5121_clk_set_rate,
715 .clk_set_parent = NULL,
716 .clk_get_parent = NULL,
719 int __init mpc5121_clk_init(void)
721 struct device_node *np;
723 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
725 clockctl = of_iomap(np, 0);
730 printk(KERN_ERR "Could not map clock control registers\n");
737 /* leave clockctl mapped forever */
738 /*iounmap(clockctl); */
740 clocks_initialized++;
741 clk_functions = mpc5121_clk_functions;