2 * Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved.
4 * Author: Andy Fleming <afleming@freescale.com>
6 * Based on 83xx/mpc8360e_pb.c by:
7 * Li Yang <LeoLi@freescale.com>
8 * Yin Olivia <Hong-hua.Yin@freescale.com>
11 * MPC85xx MDS board specific routines.
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
19 #include <linux/stddef.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/reboot.h>
24 #include <linux/pci.h>
25 #include <linux/kdev_t.h>
26 #include <linux/major.h>
27 #include <linux/console.h>
28 #include <linux/delay.h>
29 #include <linux/seq_file.h>
30 #include <linux/initrd.h>
31 #include <linux/module.h>
32 #include <linux/fsl_devices.h>
33 #include <linux/of_platform.h>
34 #include <linux/of_device.h>
35 #include <linux/phy.h>
36 #include <linux/lmb.h>
38 #include <asm/system.h>
39 #include <asm/atomic.h>
42 #include <asm/machdep.h>
43 #include <asm/pci-bridge.h>
45 #include <mm/mmu_decl.h>
48 #include <sysdev/fsl_soc.h>
49 #include <sysdev/fsl_pci.h>
50 #include <sysdev/simple_gpio.h>
52 #include <asm/qe_ic.h>
54 #include <asm/swiotlb.h>
58 #define DBG(fmt...) udbg_printf(fmt)
63 #define MV88E1111_SCR 0x10
64 #define MV88E1111_SCR_125CLK 0x0010
65 static int mpc8568_fixup_125_clock(struct phy_device *phydev)
70 /* Workaround for the 125 CLK Toggle */
71 scr = phy_read(phydev, MV88E1111_SCR);
76 err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));
81 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
86 scr = phy_read(phydev, MV88E1111_SCR);
91 err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);
96 static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
102 err = phy_write(phydev,29, 0x0006);
107 temp = phy_read(phydev, 30);
112 temp = (temp & (~0x8000)) | 0x4000;
113 err = phy_write(phydev,30, temp);
118 err = phy_write(phydev,29, 0x000a);
123 temp = phy_read(phydev, 30);
128 temp = phy_read(phydev, 30);
135 err = phy_write(phydev,30,temp);
140 /* Disable automatic MDI/MDIX selection */
141 temp = phy_read(phydev, 16);
147 err = phy_write(phydev,16,temp);
152 /* ************************************************************************
154 * Setup the architecture
157 static void __init mpc85xx_mds_setup_arch(void)
159 struct device_node *np;
160 static u8 __iomem *bcsr_regs = NULL;
162 struct pci_controller *hose;
164 dma_addr_t max = 0xffffffff;
167 ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
170 np = of_find_node_by_name(NULL, "bcsr");
174 of_address_to_resource(np, 0, &res);
175 bcsr_regs = ioremap(res.start, res.end - res.start +1);
180 for_each_node_by_type(np, "pci") {
181 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
182 of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
183 struct resource rsrc;
184 of_address_to_resource(np, 0, &rsrc);
185 if ((rsrc.start & 0xfffff) == 0x8000)
186 fsl_add_bridge(np, 1);
188 fsl_add_bridge(np, 0);
190 hose = pci_find_hose_for_OF_device(np);
191 max = min(max, hose->dma_window_base_cur +
192 hose->dma_window_size);
197 #ifdef CONFIG_QUICC_ENGINE
198 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
200 np = of_find_node_by_name(NULL, "qe");
208 np = of_find_node_by_name(NULL, "par_io");
210 struct device_node *ucc;
215 for_each_node_by_name(ucc, "ucc")
216 par_io_of_config(ucc);
220 if (machine_is(mpc8568_mds)) {
221 #define BCSR_UCC1_GETH_EN (0x1 << 7)
222 #define BCSR_UCC2_GETH_EN (0x1 << 7)
223 #define BCSR_UCC1_MODE_MSK (0x3 << 4)
224 #define BCSR_UCC2_MODE_MSK (0x3 << 0)
226 /* Turn off UCC1 & UCC2 */
227 clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
228 clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
230 /* Mode is RGMII, all bits clear */
231 clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
234 /* Turn UCC1 & UCC2 on */
235 setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
236 setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
237 } else if (machine_is(mpc8569_mds)) {
238 #define BCSR7_UCC12_GETHnRST (0x1 << 2)
239 #define BCSR8_UEM_MARVELL_RST (0x1 << 1)
240 #define BCSR_UCC_RGMII (0x1 << 6)
241 #define BCSR_UCC_RTBI (0x1 << 5)
243 * U-Boot mangles interrupt polarity for Marvell PHYs,
244 * so reset built-in and UEM Marvell PHYs, this puts
245 * the PHYs into their normal state.
247 clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
248 setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
250 setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
251 clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
253 for (np = NULL; (np = of_find_compatible_node(np,
255 "ucc_geth")) != NULL;) {
256 const unsigned int *prop;
259 prop = of_get_property(np, "cell-index", NULL);
265 prop = of_get_property(np, "phy-connection-type", NULL);
269 if (strcmp("rtbi", (const char *)prop) == 0)
270 clrsetbits_8(&bcsr_regs[7 + ucc_num],
271 BCSR_UCC_RGMII, BCSR_UCC_RTBI);
277 #endif /* CONFIG_QUICC_ENGINE */
279 #ifdef CONFIG_SWIOTLB
280 if (lmb_end_of_DRAM() > max) {
281 ppc_swiotlb_enable = 1;
282 set_pci_dma_ops(&swiotlb_dma_ops);
283 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
289 static int __init board_fixups(void)
292 char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
293 struct device_node *mdio;
297 for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
298 mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);
300 of_address_to_resource(mdio, 0, &res);
301 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
302 (unsigned long long)res.start, 1);
304 phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
305 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
307 /* Register a workaround for errata */
308 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
309 (unsigned long long)res.start, 7);
310 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
317 machine_arch_initcall(mpc8568_mds, board_fixups);
318 machine_arch_initcall(mpc8569_mds, board_fixups);
320 static struct of_device_id mpc85xx_ids[] = {
322 { .compatible = "soc", },
323 { .compatible = "simple-bus", },
325 { .compatible = "fsl,qe", },
326 { .compatible = "gianfar", },
327 { .compatible = "fsl,rapidio-delta", },
328 { .compatible = "fsl,mpc8548-guts", },
329 { .compatible = "gpio-leds", },
333 static int __init mpc85xx_publish_devices(void)
335 if (machine_is(mpc8568_mds))
336 simple_gpiochip_init("fsl,mpc8568mds-bcsr-gpio");
337 if (machine_is(mpc8569_mds))
338 simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
340 /* Publish the QE devices */
341 of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
345 machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
346 machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);
348 machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
349 machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
351 static void __init mpc85xx_mds_pic_init(void)
355 struct device_node *np = NULL;
357 np = of_find_node_by_type(NULL, "open-pic");
361 if (of_address_to_resource(np, 0, &r)) {
362 printk(KERN_ERR "Failed to map mpic register space\n");
367 mpic = mpic_alloc(np, r.start,
368 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
369 MPIC_BROKEN_FRR_NIRQS,
370 0, 256, " OpenPIC ");
371 BUG_ON(mpic == NULL);
376 #ifdef CONFIG_QUICC_ENGINE
377 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
379 np = of_find_node_by_type(NULL, "qeic");
383 qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
385 #endif /* CONFIG_QUICC_ENGINE */
388 static int __init mpc85xx_mds_probe(void)
390 unsigned long root = of_get_flat_dt_root();
392 return of_flat_dt_is_compatible(root, "MPC85xxMDS");
395 define_machine(mpc8568_mds) {
396 .name = "MPC8568 MDS",
397 .probe = mpc85xx_mds_probe,
398 .setup_arch = mpc85xx_mds_setup_arch,
399 .init_IRQ = mpc85xx_mds_pic_init,
400 .get_irq = mpic_get_irq,
401 .restart = fsl_rstcr_restart,
402 .calibrate_decr = generic_calibrate_decr,
403 .progress = udbg_progress,
405 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
409 static int __init mpc8569_mds_probe(void)
411 unsigned long root = of_get_flat_dt_root();
413 return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS");
416 define_machine(mpc8569_mds) {
417 .name = "MPC8569 MDS",
418 .probe = mpc8569_mds_probe,
419 .setup_arch = mpc85xx_mds_setup_arch,
420 .init_IRQ = mpc85xx_mds_pic_init,
421 .get_irq = mpic_get_irq,
422 .restart = fsl_rstcr_restart,
423 .calibrate_decr = generic_calibrate_decr,
424 .progress = udbg_progress,
426 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,