2 * P1022DS board specific routines
4 * Authors: Travis Wheatley <travis.wheatley@freescale.com>
5 * Dave Liu <daveliu@freescale.com>
6 * Timur Tabi <timur@freescale.com>
8 * Copyright 2010 Freescale Semiconductor, Inc.
10 * This file is taken from the Freescale P1022DS BSP, with modifications:
12 * 3) No PCI endpoint support
14 * This file is licensed under the terms of the GNU General Public License
15 * version 2. This program is licensed "as is" without any warranty of any
16 * kind, whether express or implied.
19 #include <linux/pci.h>
20 #include <linux/of_platform.h>
21 #include <linux/memblock.h>
22 #include <asm/div64.h>
24 #include <asm/swiotlb.h>
26 #include <sysdev/fsl_soc.h>
27 #include <sysdev/fsl_pci.h>
29 #include <asm/fsl_guts.h>
34 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
36 #define PMUXCR_ELBCDIU_MASK 0xc0000000
37 #define PMUXCR_ELBCDIU_NOR16 0x80000000
38 #define PMUXCR_ELBCDIU_DIU 0x40000000
41 * Board-specific initialization of the DIU. This code should probably be
42 * executed when the DIU is opened, rather than in arch code, but the DIU
43 * driver does not have a mechanism for this (yet).
45 * This is especially problematic on the P1022DS because the local bus (eLBC)
46 * and the DIU video signals share the same pins, which means that enabling the
47 * DIU will disable access to NOR flash.
50 /* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
51 #define CLKDVDR_PXCKEN 0x80000000
52 #define CLKDVDR_PXCKINV 0x10000000
53 #define CLKDVDR_PXCKDLY 0x06000000
54 #define CLKDVDR_PXCLK_MASK 0x00FF0000
56 /* Some ngPIXIS register definitions */
61 #define PX_BRDCFG0_ELBC_SPI_MASK 0xc0
62 #define PX_BRDCFG0_ELBC_SPI_ELBC 0x00
63 #define PX_BRDCFG0_ELBC_SPI_NULL 0xc0
64 #define PX_BRDCFG0_ELBC_DIU 0x02
66 #define PX_BRDCFG1_DVIEN 0x80
67 #define PX_BRDCFG1_DFPEN 0x40
68 #define PX_BRDCFG1_BACKLIGHT 0x20
69 #define PX_BRDCFG1_DDCEN 0x10
71 #define PX_CTL_ALTACC 0x80
76 * Note that we need to byte-swap the value before it's written to the AD
77 * register. So even though the registers don't look like they're in the same
78 * bit positions as they are on the MPC8610, the same value is written to the
79 * AD register on the MPC8610 and on the P1022.
81 #define AD_BYTE_F 0x10000000
82 #define AD_ALPHA_C_MASK 0x0E000000
83 #define AD_ALPHA_C_SHIFT 25
84 #define AD_BLUE_C_MASK 0x01800000
85 #define AD_BLUE_C_SHIFT 23
86 #define AD_GREEN_C_MASK 0x00600000
87 #define AD_GREEN_C_SHIFT 21
88 #define AD_RED_C_MASK 0x00180000
89 #define AD_RED_C_SHIFT 19
90 #define AD_PALETTE 0x00040000
91 #define AD_PIXEL_S_MASK 0x00030000
92 #define AD_PIXEL_S_SHIFT 16
93 #define AD_COMP_3_MASK 0x0000F000
94 #define AD_COMP_3_SHIFT 12
95 #define AD_COMP_2_MASK 0x00000F00
96 #define AD_COMP_2_SHIFT 8
97 #define AD_COMP_1_MASK 0x000000F0
98 #define AD_COMP_1_SHIFT 4
99 #define AD_COMP_0_MASK 0x0000000F
100 #define AD_COMP_0_SHIFT 0
102 #define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
103 cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \
104 (blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \
105 (red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \
106 (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
107 (c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))
110 * p1022ds_get_pixel_format: return the Area Descriptor for a given pixel depth
112 * The Area Descriptor is a 32-bit value that determine which bits in each
113 * pixel are to be used for each color.
115 static u32 p1022ds_get_pixel_format(enum fsl_diu_monitor_port port,
116 unsigned int bits_per_pixel)
118 switch (bits_per_pixel) {
121 return MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8);
124 return MAKE_AD(4, 0, 1, 2, 2, 0, 8, 8, 8);
127 return MAKE_AD(4, 2, 1, 0, 1, 5, 6, 5, 0);
129 pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel);
135 * p1022ds_set_gamma_table: update the gamma table, if necessary
137 * On some boards, the gamma table for some ports may need to be modified.
138 * This is not the case on the P1022DS, so we do nothing.
140 static void p1022ds_set_gamma_table(enum fsl_diu_monitor_port port,
141 char *gamma_table_base)
146 * p1022ds_set_monitor_port: switch the output to a different monitor port
149 static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
151 struct device_node *guts_node;
152 struct device_node *indirect_node = NULL;
153 struct ccsr_guts __iomem *guts;
154 u8 __iomem *lbc_lcs0_ba = NULL;
155 u8 __iomem *lbc_lcs1_ba = NULL;
158 /* Map the global utilities registers. */
159 guts_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
161 pr_err("p1022ds: missing global utilties device node\n");
165 guts = of_iomap(guts_node, 0);
167 pr_err("p1022ds: could not map global utilties device\n");
171 indirect_node = of_find_compatible_node(NULL, NULL,
172 "fsl,p1022ds-indirect-pixis");
173 if (!indirect_node) {
174 pr_err("p1022ds: missing pixis indirect mode node\n");
178 lbc_lcs0_ba = of_iomap(indirect_node, 0);
180 pr_err("p1022ds: could not map localbus chip select 0\n");
184 lbc_lcs1_ba = of_iomap(indirect_node, 1);
186 pr_err("p1022ds: could not map localbus chip select 1\n");
190 /* Make sure we're in indirect mode first. */
191 if ((in_be32(&guts->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
192 PMUXCR_ELBCDIU_DIU) {
193 struct device_node *pixis_node;
197 of_find_compatible_node(NULL, NULL, "fsl,p1022ds-fpga");
199 pr_err("p1022ds: missing pixis node\n");
203 pixis = of_iomap(pixis_node, 0);
204 of_node_put(pixis_node);
206 pr_err("p1022ds: could not map pixis registers\n");
210 /* Enable indirect PIXIS mode. */
211 setbits8(pixis + PX_CTL, PX_CTL_ALTACC);
214 /* Switch the board mux to the DIU */
215 out_8(lbc_lcs0_ba, PX_BRDCFG0); /* BRDCFG0 */
216 b = in_8(lbc_lcs1_ba);
217 b |= PX_BRDCFG0_ELBC_DIU;
218 out_8(lbc_lcs1_ba, b);
220 /* Set the chip mux to DIU mode. */
221 clrsetbits_be32(&guts->pmuxcr, PMUXCR_ELBCDIU_MASK,
223 in_be32(&guts->pmuxcr);
228 case FSL_DIU_PORT_DVI:
229 /* Enable the DVI port, disable the DFP and the backlight */
230 out_8(lbc_lcs0_ba, PX_BRDCFG1);
231 b = in_8(lbc_lcs1_ba);
232 b &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
233 b |= PX_BRDCFG1_DVIEN;
234 out_8(lbc_lcs1_ba, b);
236 case FSL_DIU_PORT_LVDS:
238 * LVDS also needs backlight enabled, otherwise the display
241 /* Enable the DFP port, disable the DVI and the backlight */
242 out_8(lbc_lcs0_ba, PX_BRDCFG1);
243 b = in_8(lbc_lcs1_ba);
244 b &= ~PX_BRDCFG1_DVIEN;
245 b |= PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT;
246 out_8(lbc_lcs1_ba, b);
249 pr_err("p1022ds: unsupported monitor port %i\n", port);
254 iounmap(lbc_lcs1_ba);
256 iounmap(lbc_lcs0_ba);
260 of_node_put(indirect_node);
261 of_node_put(guts_node);
265 * p1022ds_set_pixel_clock: program the DIU's clock
267 * @pixclock: the wavelength, in picoseconds, of the clock
269 void p1022ds_set_pixel_clock(unsigned int pixclock)
271 struct device_node *guts_np = NULL;
272 struct ccsr_guts __iomem *guts;
277 /* Map the global utilities registers. */
278 guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
280 pr_err("p1022ds: missing global utilties device node\n");
284 guts = of_iomap(guts_np, 0);
285 of_node_put(guts_np);
287 pr_err("p1022ds: could not map global utilties device\n");
291 /* Convert pixclock from a wavelength to a frequency */
292 temp = 1000000000000ULL;
293 do_div(temp, pixclock);
297 * 'pxclk' is the ratio of the platform clock to the pixel clock.
298 * This number is programmed into the CLKDVDR register, and the valid
299 * range of values is 2-255.
301 pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
302 pxclk = clamp_t(u32, pxclk, 2, 255);
304 /* Disable the pixel clock, and set it to non-inverted and no delay */
305 clrbits32(&guts->clkdvdr,
306 CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
308 /* Enable the clock and set the pxclk */
309 setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
315 * p1022ds_valid_monitor_port: set the monitor port for sysfs
317 enum fsl_diu_monitor_port
318 p1022ds_valid_monitor_port(enum fsl_diu_monitor_port port)
321 case FSL_DIU_PORT_DVI:
322 case FSL_DIU_PORT_LVDS:
325 return FSL_DIU_PORT_DVI; /* Dual-link LVDS is not supported */
331 void __init p1022_ds_pic_init(void)
333 struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
334 MPIC_SINGLE_DEST_CPU,
335 0, 256, " OpenPIC ");
336 BUG_ON(mpic == NULL);
340 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
343 * Disables a node in the device tree.
345 * This function is called before kmalloc() is available, so the 'new' object
346 * should be allocated in the global area. The easiest way is to do that is
347 * to allocate one static local variable for each call to this function.
349 static void __init disable_one_node(struct device_node *np, struct property *new)
351 struct property *old;
353 old = of_find_property(np, new->name, NULL);
355 prom_update_property(np, new, old);
357 prom_add_property(np, new);
360 /* TRUE if there is a "video=fslfb" command-line parameter. */
364 * Search for a "video=fslfb" command-line parameter, and set 'fslfb' to
365 * true if we find it.
367 * We need to use early_param() instead of __setup() because the normal
368 * __setup() gets called to late. However, early_param() gets called very
369 * early, before the device tree is unflattened, so all we can do now is set a
370 * global variable. Later on, p1022_ds_setup_arch() will use that variable
371 * to determine if we need to update the device tree.
373 static int __init early_video_setup(char *options)
375 fslfb = (strncmp(options, "fslfb:", 6) == 0);
379 early_param("video", early_video_setup);
384 * Setup the architecture
386 static void __init p1022_ds_setup_arch(void)
389 struct device_node *np;
391 dma_addr_t max = 0xffffffff;
394 ppc_md.progress("p1022_ds_setup_arch()", 0);
397 for_each_compatible_node(np, "pci", "fsl,p1022-pcie") {
398 struct resource rsrc;
399 struct pci_controller *hose;
401 of_address_to_resource(np, 0, &rsrc);
403 if ((rsrc.start & 0xfffff) == 0x8000)
404 fsl_add_bridge(np, 1);
406 fsl_add_bridge(np, 0);
408 hose = pci_find_hose_for_OF_device(np);
409 max = min(max, hose->dma_window_base_cur +
410 hose->dma_window_size);
414 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
415 diu_ops.get_pixel_format = p1022ds_get_pixel_format;
416 diu_ops.set_gamma_table = p1022ds_set_gamma_table;
417 diu_ops.set_monitor_port = p1022ds_set_monitor_port;
418 diu_ops.set_pixel_clock = p1022ds_set_pixel_clock;
419 diu_ops.valid_monitor_port = p1022ds_valid_monitor_port;
422 * Disable the NOR flash node if there is video=fslfb... command-line
423 * parameter. When the DIU is active, NOR flash is unavailable, so we
424 * have to disable the node before the MTD driver loads.
427 struct device_node *np =
428 of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc");
431 np = of_find_compatible_node(np, NULL, "cfi-flash");
433 static struct property nor_status = {
436 .length = sizeof("disabled"),
439 pr_info("p1022ds: disabling %s node",
441 disable_one_node(np, &nor_status);
452 #ifdef CONFIG_SWIOTLB
453 if (memblock_end_of_DRAM() > max) {
454 ppc_swiotlb_enable = 1;
455 set_pci_dma_ops(&swiotlb_dma_ops);
456 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
460 pr_info("Freescale P1022 DS reference board\n");
463 static struct of_device_id __initdata p1022_ds_ids[] = {
464 /* So that the DMA channel nodes can be probed individually: */
465 { .compatible = "fsl,eloplus-dma", },
469 static int __init p1022_ds_publish_devices(void)
471 mpc85xx_common_publish_devices();
472 return of_platform_bus_probe(NULL, p1022_ds_ids, NULL);
474 machine_device_initcall(p1022_ds, p1022_ds_publish_devices);
476 machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
479 * Called very early, device-tree isn't unflattened
481 static int __init p1022_ds_probe(void)
483 unsigned long root = of_get_flat_dt_root();
485 return of_flat_dt_is_compatible(root, "fsl,p1022ds");
488 define_machine(p1022_ds) {
490 .probe = p1022_ds_probe,
491 .setup_arch = p1022_ds_setup_arch,
492 .init_IRQ = p1022_ds_pic_init,
494 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
496 .get_irq = mpic_get_irq,
497 .restart = fsl_rstcr_restart,
498 .calibrate_decr = generic_calibrate_decr,
499 .progress = udbg_progress,