2 * Copyright (C) 2009 Extreme Engineering Solutions, Inc.
4 * X-ES board-specific functionality
6 * Based on mpc85xx_ds code from Freescale Semiconductor, Inc.
8 * Author: Nate Case <ncase@xes-inc.com>
10 * This is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/stddef.h>
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/kdev_t.h>
19 #include <linux/delay.h>
20 #include <linux/seq_file.h>
21 #include <linux/interrupt.h>
22 #include <linux/of_platform.h>
24 #include <asm/system.h>
26 #include <asm/machdep.h>
27 #include <asm/pci-bridge.h>
28 #include <mm/mmu_decl.h>
33 #include <sysdev/fsl_soc.h>
34 #include <sysdev/fsl_pci.h>
35 #include <linux/of_platform.h>
37 /* A few bit definitions needed for fixups on some boards */
38 #define MPC85xx_L2CTL_L2E 0x80000000 /* L2 enable */
39 #define MPC85xx_L2CTL_L2I 0x40000000 /* L2 flash invalidate */
40 #define MPC85xx_L2CTL_L2SIZ_MASK 0x30000000 /* L2 SRAM size (R/O) */
42 void __init xes_mpc85xx_pic_init(void)
46 struct device_node *np;
48 np = of_find_node_by_type(NULL, "open-pic");
50 printk(KERN_ERR "Could not find open-pic node\n");
54 if (of_address_to_resource(np, 0, &r)) {
55 printk(KERN_ERR "Failed to map mpic register space\n");
60 mpic = mpic_alloc(np, r.start,
61 MPIC_PRIMARY | MPIC_WANTS_RESET |
62 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
70 static void xes_mpc85xx_configure_l2(void __iomem *l2_base)
72 volatile uint32_t ctl, tmp;
74 asm volatile("msync; isync");
75 tmp = in_be32(l2_base);
78 * xMon may have enabled part of L2 as SRAM, so we need to set it
79 * up for all cache mode just to be safe.
81 printk(KERN_INFO "xes_mpc85xx: Enabling L2 as cache\n");
83 ctl = MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2I;
84 if (machine_is_compatible("MPC8540") ||
85 machine_is_compatible("MPC8560"))
87 * Assume L2 SRAM is used fully for cache, so set
88 * L2BLKSZ (bits 4:5) to match L2SIZ (bits 2:3).
90 ctl |= (tmp & MPC85xx_L2CTL_L2SIZ_MASK) >> 2;
92 asm volatile("msync; isync");
93 out_be32(l2_base, ctl);
94 asm volatile("msync; isync");
97 static void xes_mpc85xx_fixups(void)
99 struct device_node *np;
103 * Legacy xMon firmware on some X-ES boards does not enable L2
104 * as cache. We must ensure that they get enabled here.
106 for_each_node_by_name(np, "l2-cache-controller") {
107 struct resource r[2];
108 void __iomem *l2_base;
110 /* Only MPC8548, MPC8540, and MPC8560 boards are affected */
111 if (!of_device_is_compatible(np,
112 "fsl,mpc8548-l2-cache-controller") &&
113 !of_device_is_compatible(np,
114 "fsl,mpc8540-l2-cache-controller") &&
115 !of_device_is_compatible(np,
116 "fsl,mpc8560-l2-cache-controller"))
119 err = of_address_to_resource(np, 0, &r[0]);
121 printk(KERN_WARNING "xes_mpc85xx: Could not get "
122 "resource for device tree node '%s'",
127 l2_base = ioremap(r[0].start, r[0].end - r[0].start + 1);
129 xes_mpc85xx_configure_l2(l2_base);
134 static int primary_phb_addr;
138 * Setup the architecture
141 extern void __init mpc85xx_smp_init(void);
143 static void __init xes_mpc85xx_setup_arch(void)
146 struct device_node *np;
148 struct device_node *root;
149 const char *model = "Unknown";
151 root = of_find_node_by_path("/");
155 model = of_get_property(root, "model", NULL);
157 printk(KERN_INFO "X-ES MPC85xx-based single-board computer: %s\n",
158 model + strlen("xes,"));
160 xes_mpc85xx_fixups();
163 for_each_node_by_type(np, "pci") {
164 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
165 of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
166 struct resource rsrc;
167 of_address_to_resource(np, 0, &rsrc);
168 if ((rsrc.start & 0xfffff) == primary_phb_addr)
169 fsl_add_bridge(np, 1);
171 fsl_add_bridge(np, 0);
181 static struct of_device_id __initdata xes_mpc85xx_ids[] = {
183 { .compatible = "soc", },
184 { .compatible = "simple-bus", },
185 { .compatible = "gianfar", },
189 static int __init xes_mpc85xx_publish_devices(void)
191 return of_platform_bus_probe(NULL, xes_mpc85xx_ids, NULL);
193 machine_device_initcall(xes_mpc8572, xes_mpc85xx_publish_devices);
194 machine_device_initcall(xes_mpc8548, xes_mpc85xx_publish_devices);
195 machine_device_initcall(xes_mpc8540, xes_mpc85xx_publish_devices);
198 * Called very early, device-tree isn't unflattened
200 static int __init xes_mpc8572_probe(void)
202 unsigned long root = of_get_flat_dt_root();
204 if (of_flat_dt_is_compatible(root, "xes,MPC8572")) {
206 primary_phb_addr = 0x8000;
214 static int __init xes_mpc8548_probe(void)
216 unsigned long root = of_get_flat_dt_root();
218 if (of_flat_dt_is_compatible(root, "xes,MPC8548")) {
220 primary_phb_addr = 0xb000;
228 static int __init xes_mpc8540_probe(void)
230 unsigned long root = of_get_flat_dt_root();
232 if (of_flat_dt_is_compatible(root, "xes,MPC8540")) {
234 primary_phb_addr = 0xb000;
242 define_machine(xes_mpc8572) {
243 .name = "X-ES MPC8572",
244 .probe = xes_mpc8572_probe,
245 .setup_arch = xes_mpc85xx_setup_arch,
246 .init_IRQ = xes_mpc85xx_pic_init,
248 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
250 .get_irq = mpic_get_irq,
251 .restart = fsl_rstcr_restart,
252 .calibrate_decr = generic_calibrate_decr,
253 .progress = udbg_progress,
256 define_machine(xes_mpc8548) {
257 .name = "X-ES MPC8548",
258 .probe = xes_mpc8548_probe,
259 .setup_arch = xes_mpc85xx_setup_arch,
260 .init_IRQ = xes_mpc85xx_pic_init,
262 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
264 .get_irq = mpic_get_irq,
265 .restart = fsl_rstcr_restart,
266 .calibrate_decr = generic_calibrate_decr,
267 .progress = udbg_progress,
270 define_machine(xes_mpc8540) {
271 .name = "X-ES MPC8540",
272 .probe = xes_mpc8540_probe,
273 .setup_arch = xes_mpc85xx_setup_arch,
274 .init_IRQ = xes_mpc85xx_pic_init,
276 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
278 .get_irq = mpic_get_irq,
279 .restart = fsl_rstcr_restart,
280 .calibrate_decr = generic_calibrate_decr,
281 .progress = udbg_progress,