1 menu "Platform support"
3 source "arch/powerpc/platforms/powernv/Kconfig"
4 source "arch/powerpc/platforms/pseries/Kconfig"
5 source "arch/powerpc/platforms/chrp/Kconfig"
6 source "arch/powerpc/platforms/512x/Kconfig"
7 source "arch/powerpc/platforms/52xx/Kconfig"
8 source "arch/powerpc/platforms/powermac/Kconfig"
9 source "arch/powerpc/platforms/prep/Kconfig"
10 source "arch/powerpc/platforms/maple/Kconfig"
11 source "arch/powerpc/platforms/pasemi/Kconfig"
12 source "arch/powerpc/platforms/ps3/Kconfig"
13 source "arch/powerpc/platforms/cell/Kconfig"
14 source "arch/powerpc/platforms/8xx/Kconfig"
15 source "arch/powerpc/platforms/82xx/Kconfig"
16 source "arch/powerpc/platforms/83xx/Kconfig"
17 source "arch/powerpc/platforms/85xx/Kconfig"
18 source "arch/powerpc/platforms/86xx/Kconfig"
19 source "arch/powerpc/platforms/embedded6xx/Kconfig"
20 source "arch/powerpc/platforms/44x/Kconfig"
21 source "arch/powerpc/platforms/40x/Kconfig"
22 source "arch/powerpc/platforms/amigaone/Kconfig"
23 source "arch/powerpc/platforms/wsp/Kconfig"
26 bool "KVM Guest support"
29 This option enables various optimizations for running under the KVM
30 hypervisor. Overhead for the kernel when not running inside KVM should
33 In case of doubt, say Y
37 depends on 6xx || PPC64
39 Support for running natively on the hardware, i.e. without
40 a hypervisor. This option is not user-selectable but should
41 be selected by all platforms that need it.
43 config PPC_OF_BOOT_TRAMPOLINE
44 bool "Support booting from Open Firmware or yaboot"
45 depends on 6xx || PPC64
48 Support from booting from Open Firmware or yaboot using an
49 Open Firmware client interface. This enables the kernel to
50 communicate with open firmware to retrieve system information
51 such as the device tree.
53 In case of doubt, say Y
55 config UDBG_RTAS_CONSOLE
56 bool "RTAS based debug console"
60 config PPC_SMP_MUXED_IPI
63 Select this opton if your platform supports SMP and your
64 interrupt controller provides less than 4 interrupts to each
65 cpu. This will enable the generic code to multiplex the 4
66 messages on to one ipi.
69 bool "BEAT based debug console"
81 config PPC_EPAPR_HV_PIC
90 bool "MPIC message register support"
94 Enables support for the MPIC message registers. These
95 registers are used for inter-processor communication.
110 config RTAS_ERROR_LOGGING
115 config PPC_RTAS_DAEMON
121 bool "Proc interface to RTAS"
126 tristate "Firmware flash interface"
127 depends on PPC64 && RTAS_PROC
133 config MPIC_U3_HT_IRQS
137 config MPIC_BROKEN_REGREAD
141 This option enables a MPIC driver workaround for some chips
142 that have a bug that causes some interrupt source information
143 to not read back properly. It is safe to use on other chips as
144 well, but enabling it uses about 8KB of memory to keep copies
145 of the register contents in software.
148 depends on PPC_PSERIES
153 depends on PPC_PSERIES
154 bool "Support for GX bus based adapters"
156 Bus device driver for GX bus based adapters.
170 config PPC_INDIRECT_IO
174 config PPC_INDIRECT_PIO
176 select PPC_INDIRECT_IO
178 config PPC_INDIRECT_MMIO
180 select PPC_INDIRECT_IO
182 config PPC_IO_WORKAROUNDS
185 source "drivers/cpufreq/Kconfig"
187 menu "CPU Frequency drivers"
191 bool "Support for Apple PowerBooks"
192 depends on ADB_PMU && PPC32
193 select CPU_FREQ_TABLE
195 This adds support for frequency switching on Apple PowerBooks,
196 this currently includes some models of iBook & Titanium
199 config CPU_FREQ_PMAC64
200 bool "Support for some Apple G5s"
201 depends on PPC_PMAC && PPC64
202 select CPU_FREQ_TABLE
204 This adds support for frequency switching on Apple iMac G5,
205 and some of the more recent desktop G5 machines as well.
207 config PPC_PASEMI_CPUFREQ
208 bool "Support for PA Semi PWRficient"
209 depends on PPC_PASEMI
211 select CPU_FREQ_TABLE
213 This adds the support for frequency switching on PA Semi
214 PWRficient processors.
218 menu "CPUIdle driver"
220 source "drivers/cpuidle/Kconfig"
224 config PPC601_SYNC_FIX
225 bool "Workarounds for PPC601 bugs"
226 depends on 6xx && (PPC_PREP || PPC_PMAC)
228 Some versions of the PPC601 (the first PowerPC chip) have bugs which
229 mean that extra synchronization instructions are required near
230 certain instructions, typically those that make major changes to the
231 CPU state. These extra instructions reduce performance slightly.
232 If you say N here, these extra instructions will not be included,
233 resulting in a kernel which will run faster but may not run at all
234 on some systems with the PPC601 chip.
236 If in doubt, say Y here.
239 bool "On-chip CPU temperature sensor support"
242 G3 and G4 processors have an on-chip temperature sensor called the
243 'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die
244 temperature within 2-4 degrees Celsius. This option shows the current
245 on-die temperature in /proc/cpuinfo if the cpu supports it.
247 Unfortunately, on some chip revisions, this sensor is very inaccurate
248 and in many cases, does not work at all, so don't assume the cpu
249 temp is actually what /proc/cpuinfo says it is.
252 bool "Interrupt driven TAU driver (DANGEROUS)"
255 The TAU supports an interrupt driven mode which causes an interrupt
256 whenever the temperature goes out of range. This is the fastest way
257 to get notified the temp has exceeded a range. With this option off,
258 a timer is used to re-check the temperature periodically.
260 However, on some cpus it appears that the TAU interrupt hardware
261 is buggy and can cause a situation which would lead unexplained hard
264 Unless you are extending the TAU driver, or enjoy kernel/hardware
265 debugging, leave this option off.
268 bool "Average high and low temp"
271 The TAU hardware can compare the temperature to an upper and lower
272 bound. The default behavior is to show both the upper and lower
273 bound in /proc/cpuinfo. If the range is large, the temperature is
274 either changing a lot, or the TAU hardware is broken (likely on some
275 G4's). If the range is small (around 4 degrees), the temperature is
276 relatively stable. If you say Y here, a single temperature value,
277 halfway between the upper and lower bounds, will be reported in
280 If in doubt, say N here.
283 bool "Freescale QUICC Engine (QE) Support"
284 depends on FSL_SOC && PPC32
288 The QUICC Engine (QE) is a new generation of communications
289 coprocessors on Freescale embedded CPUs (akin to CPM in older chips).
290 Selecting this option means that you wish to build a kernel
291 for a machine with a QE coprocessor.
294 bool "QE GPIO support"
295 depends on QUICC_ENGINE
297 select ARCH_REQUIRE_GPIOLIB
299 Say Y here if you're going to use hardware that connects to the
303 bool "Enable support for the CPM2 (Communications Processor Module)"
304 depends on (FSL_SOC_BOOKE && PPC32) || 8260
307 select PPC_PCI_CHOICE
308 select ARCH_REQUIRE_GPIOLIB
311 The CPM2 (Communications Processor Module) is a coprocessor on
312 embedded CPUs made by Freescale. Selecting this option means that
313 you wish to build a kernel for a machine with a CPM2 coprocessor
314 on it (826x, 827x, 8560).
317 tristate "Axon DDR2 memory device driver"
318 depends on PPC_IBM_CELL_BLADE && BLOCK
321 It registers one block device per Axon's DDR2 memory bank found
322 on a system. Block devices are called axonram?, their major and
323 minor numbers are available in /proc/devices, /proc/partitions or
324 in /sys/block/axonram?/dev.
329 select GENERIC_ISA_DMA
331 Supports for the ULI1575 PCIe south bridge that exists on some
332 Freescale reference boards. The boards all use the ULI in pretty
342 Uses information from the OF or flattened device tree to instantiate
343 platform devices for direct mapped RTC chips like the DS1742 or DS1743.
345 source "arch/powerpc/sysdev/bestcomm/Kconfig"
348 bool "Support for simple, memory-mapped GPIO controllers"
351 select ARCH_REQUIRE_GPIOLIB
353 Say Y here to support simple, memory-mapped GPIO controllers.
354 These are usually BCSRs used to control board's switches, LEDs,
355 chip-selects, Ethernet/USB PHY's power and various other small
356 on-board peripherals.
358 config MCU_MPC8349EMITX
359 bool "MPC8349E-mITX MCU driver"
360 depends on I2C=y && PPC_83xx
362 select ARCH_REQUIRE_GPIOLIB
364 Say Y here to enable soft power-off functionality on the Freescale
365 boards with the MPC8349E-mITX-compatible MCU chips. This driver will
366 also register MCU GPIOs with the generic GPIO API, so you'll able
367 to use MCU pins as GPIOs.
370 bool "Xilinx PCI host bridge support"
371 depends on PCI && XILINX_VIRTEX