2 * Cell Broadband Engine Performance Monitor
4 * (C) Copyright IBM Corporation 2001,2006
7 * David Erb (djerb@us.ibm.com)
8 * Kevin Corry (kevcorry@us.ibm.com)
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/interrupt.h>
26 #include <linux/types.h>
28 #include <asm/machdep.h>
34 #include "interrupt.h"
37 * When writing to write-only mmio addresses, save a shadow copy. All of the
38 * registers are 32-bit, but stored in the upper-half of a 64-bit field in
42 #define WRITE_WO_MMIO(reg, x) \
45 struct cbe_pmd_regs __iomem *pmd_regs; \
46 struct cbe_pmd_shadow_regs *shadow_regs; \
47 pmd_regs = cbe_get_cpu_pmd_regs(cpu); \
48 shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu); \
49 out_be64(&(pmd_regs->reg), (((u64)_x) << 32)); \
50 shadow_regs->reg = _x; \
53 #define READ_SHADOW_REG(val, reg) \
55 struct cbe_pmd_shadow_regs *shadow_regs; \
56 shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu); \
57 (val) = shadow_regs->reg; \
60 #define READ_MMIO_UPPER32(val, reg) \
62 struct cbe_pmd_regs __iomem *pmd_regs; \
63 pmd_regs = cbe_get_cpu_pmd_regs(cpu); \
64 (val) = (u32)(in_be64(&pmd_regs->reg) >> 32); \
68 * Physical counter registers.
69 * Each physical counter can act as one 32-bit counter or two 16-bit counters.
72 u32 cbe_read_phys_ctr(u32 cpu, u32 phys_ctr)
74 u32 val_in_latch, val = 0;
76 if (phys_ctr < NR_PHYS_CTRS) {
77 READ_SHADOW_REG(val_in_latch, counter_value_in_latch);
79 /* Read the latch or the actual counter, whichever is newer. */
80 if (val_in_latch & (1 << phys_ctr)) {
81 READ_SHADOW_REG(val, pm_ctr[phys_ctr]);
83 READ_MMIO_UPPER32(val, pm_ctr[phys_ctr]);
89 EXPORT_SYMBOL_GPL(cbe_read_phys_ctr);
91 void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val)
93 struct cbe_pmd_shadow_regs *shadow_regs;
96 if (phys_ctr < NR_PHYS_CTRS) {
97 /* Writing to a counter only writes to a hardware latch.
98 * The new value is not propagated to the actual counter
99 * until the performance monitor is enabled.
101 WRITE_WO_MMIO(pm_ctr[phys_ctr], val);
103 pm_ctrl = cbe_read_pm(cpu, pm_control);
104 if (pm_ctrl & CBE_PM_ENABLE_PERF_MON) {
105 /* The counters are already active, so we need to
106 * rewrite the pm_control register to "re-enable"
109 cbe_write_pm(cpu, pm_control, pm_ctrl);
111 shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);
112 shadow_regs->counter_value_in_latch |= (1 << phys_ctr);
116 EXPORT_SYMBOL_GPL(cbe_write_phys_ctr);
119 * "Logical" counter registers.
120 * These will read/write 16-bits or 32-bits depending on the
121 * current size of the counter. Counters 4 - 7 are always 16-bit.
124 u32 cbe_read_ctr(u32 cpu, u32 ctr)
127 u32 phys_ctr = ctr & (NR_PHYS_CTRS - 1);
129 val = cbe_read_phys_ctr(cpu, phys_ctr);
131 if (cbe_get_ctr_size(cpu, phys_ctr) == 16)
132 val = (ctr < NR_PHYS_CTRS) ? (val >> 16) : (val & 0xffff);
136 EXPORT_SYMBOL_GPL(cbe_read_ctr);
138 void cbe_write_ctr(u32 cpu, u32 ctr, u32 val)
143 phys_ctr = ctr & (NR_PHYS_CTRS - 1);
145 if (cbe_get_ctr_size(cpu, phys_ctr) == 16) {
146 phys_val = cbe_read_phys_ctr(cpu, phys_ctr);
148 if (ctr < NR_PHYS_CTRS)
149 val = (val << 16) | (phys_val & 0xffff);
151 val = (val & 0xffff) | (phys_val & 0xffff0000);
154 cbe_write_phys_ctr(cpu, phys_ctr, val);
156 EXPORT_SYMBOL_GPL(cbe_write_ctr);
159 * Counter-control registers.
160 * Each "logical" counter has a corresponding control register.
163 u32 cbe_read_pm07_control(u32 cpu, u32 ctr)
165 u32 pm07_control = 0;
168 READ_SHADOW_REG(pm07_control, pm07_control[ctr]);
172 EXPORT_SYMBOL_GPL(cbe_read_pm07_control);
174 void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val)
177 WRITE_WO_MMIO(pm07_control[ctr], val);
179 EXPORT_SYMBOL_GPL(cbe_write_pm07_control);
182 * Other PMU control registers. Most of these are write-only.
185 u32 cbe_read_pm(u32 cpu, enum pm_reg_name reg)
191 READ_SHADOW_REG(val, group_control);
194 case debug_bus_control:
195 READ_SHADOW_REG(val, debug_bus_control);
199 READ_MMIO_UPPER32(val, trace_address);
203 READ_SHADOW_REG(val, ext_tr_timer);
207 READ_MMIO_UPPER32(val, pm_status);
211 READ_SHADOW_REG(val, pm_control);
215 READ_SHADOW_REG(val, pm_interval);
219 READ_SHADOW_REG(val, pm_start_stop);
225 EXPORT_SYMBOL_GPL(cbe_read_pm);
227 void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val)
231 WRITE_WO_MMIO(group_control, val);
234 case debug_bus_control:
235 WRITE_WO_MMIO(debug_bus_control, val);
239 WRITE_WO_MMIO(trace_address, val);
243 WRITE_WO_MMIO(ext_tr_timer, val);
247 WRITE_WO_MMIO(pm_status, val);
251 WRITE_WO_MMIO(pm_control, val);
255 WRITE_WO_MMIO(pm_interval, val);
259 WRITE_WO_MMIO(pm_start_stop, val);
263 EXPORT_SYMBOL_GPL(cbe_write_pm);
266 * Get/set the size of a physical counter to either 16 or 32 bits.
269 u32 cbe_get_ctr_size(u32 cpu, u32 phys_ctr)
271 u32 pm_ctrl, size = 0;
273 if (phys_ctr < NR_PHYS_CTRS) {
274 pm_ctrl = cbe_read_pm(cpu, pm_control);
275 size = (pm_ctrl & CBE_PM_16BIT_CTR(phys_ctr)) ? 16 : 32;
280 EXPORT_SYMBOL_GPL(cbe_get_ctr_size);
282 void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size)
286 if (phys_ctr < NR_PHYS_CTRS) {
287 pm_ctrl = cbe_read_pm(cpu, pm_control);
290 pm_ctrl |= CBE_PM_16BIT_CTR(phys_ctr);
294 pm_ctrl &= ~CBE_PM_16BIT_CTR(phys_ctr);
297 cbe_write_pm(cpu, pm_control, pm_ctrl);
300 EXPORT_SYMBOL_GPL(cbe_set_ctr_size);
303 * Enable/disable the entire performance monitoring unit.
304 * When we enable the PMU, all pending writes to counters get committed.
307 void cbe_enable_pm(u32 cpu)
309 struct cbe_pmd_shadow_regs *shadow_regs;
312 shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);
313 shadow_regs->counter_value_in_latch = 0;
315 pm_ctrl = cbe_read_pm(cpu, pm_control) | CBE_PM_ENABLE_PERF_MON;
316 cbe_write_pm(cpu, pm_control, pm_ctrl);
318 EXPORT_SYMBOL_GPL(cbe_enable_pm);
320 void cbe_disable_pm(u32 cpu)
323 pm_ctrl = cbe_read_pm(cpu, pm_control) & ~CBE_PM_ENABLE_PERF_MON;
324 cbe_write_pm(cpu, pm_control, pm_ctrl);
326 EXPORT_SYMBOL_GPL(cbe_disable_pm);
329 * Reading from the trace_buffer.
330 * The trace buffer is two 64-bit registers. Reading from
331 * the second half automatically increments the trace_address.
334 void cbe_read_trace_buffer(u32 cpu, u64 *buf)
336 struct cbe_pmd_regs __iomem *pmd_regs = cbe_get_cpu_pmd_regs(cpu);
338 *buf++ = in_be64(&pmd_regs->trace_buffer_0_63);
339 *buf++ = in_be64(&pmd_regs->trace_buffer_64_127);
341 EXPORT_SYMBOL_GPL(cbe_read_trace_buffer);
344 * Enabling/disabling interrupts for the entire performance monitoring unit.
347 u32 cbe_query_pm_interrupts(u32 cpu)
349 return cbe_read_pm(cpu, pm_status);
351 EXPORT_SYMBOL_GPL(cbe_query_pm_interrupts);
353 u32 cbe_clear_pm_interrupts(u32 cpu)
355 /* Reading pm_status clears the interrupt bits. */
356 return cbe_query_pm_interrupts(cpu);
358 EXPORT_SYMBOL_GPL(cbe_clear_pm_interrupts);
360 void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask)
362 /* Set which node and thread will handle the next interrupt. */
363 iic_set_interrupt_routing(cpu, thread, 0);
365 /* Enable the interrupt bits in the pm_status register. */
367 cbe_write_pm(cpu, pm_status, mask);
369 EXPORT_SYMBOL_GPL(cbe_enable_pm_interrupts);
371 void cbe_disable_pm_interrupts(u32 cpu)
373 cbe_clear_pm_interrupts(cpu);
374 cbe_write_pm(cpu, pm_status, 0);
376 EXPORT_SYMBOL_GPL(cbe_disable_pm_interrupts);
378 static irqreturn_t cbe_pm_irq(int irq, void *dev_id, struct pt_regs *regs)
384 int __init cbe_init_pm_irq(void)
389 for_each_node(node) {
390 irq = irq_create_mapping(NULL, IIC_IRQ_IOEX_PMI |
391 (node << IIC_IRQ_NODE_SHIFT));
393 printk("ERROR: Unable to allocate irq for node %d\n",
398 rc = request_irq(irq, cbe_pm_irq,
399 IRQF_DISABLED, "cbe-pmu-0", NULL);
401 printk("ERROR: Request for irq on node %d failed\n",
409 arch_initcall(cbe_init_pm_irq);