arch/powerpc/platforms/cell/spufs/switch.c

   1 /*
   2  * spu_switch.c
   3  *
   4  * (C) Copyright IBM Corp. 2005
   5  *
   6  * Author: Mark Nutter <mnutter@us.ibm.com>
   7  *
   8  * Host-side part of SPU context switch sequence outlined in
   9  * Synergistic Processor Element, Book IV.
  10  *
  11  * A fully premptive switch of an SPE is very expensive in terms
  12  * of time and system resources.  SPE Book IV indicates that SPE
  13  * allocation should follow a "serially reusable device" model,
  14  * in which the SPE is assigned a task until it completes.  When
  15  * this is not possible, this sequence may be used to premptively
  16  * save, and then later (optionally) restore the context of a
  17  * program executing on an SPE.
  18  *
  19  *
  20  * This program is free software; you can redistribute it and/or modify
  21  * it under the terms of the GNU General Public License as published by
  22  * the Free Software Foundation; either version 2, or (at your option)
  23  * any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/errno.h>
  37 #include <linux/hardirq.h>
  38 #include <linux/sched.h>
  39 #include <linux/kernel.h>
  40 #include <linux/mm.h>
  41 #include <linux/vmalloc.h>
  42 #include <linux/smp.h>
  43 #include <linux/stddef.h>
  44 #include <linux/unistd.h>
  45
  46 #include <asm/io.h>
  47 #include <asm/spu.h>
  48 #include <asm/spu_priv1.h>
  49 #include <asm/spu_csa.h>
  50 #include <asm/mmu_context.h>
  51
  52 #include "spufs.h"
  53
  54 #include "spu_save_dump.h"
  55 #include "spu_restore_dump.h"
  56
  57 #if 0
  58 #define POLL_WHILE_TRUE(_c) {                           \
  59     do {                                                \
  60     } while (_c);                                       \
  61   }
  62 #else
  63 #define RELAX_SPIN_COUNT                                1000
  64 #define POLL_WHILE_TRUE(_c) {                           \
  65     do {                                                \
  66         int _i;                                         \
  67         for (_i=0; _i<RELAX_SPIN_COUNT && (_c); _i++) { \
  68             cpu_relax();                                \
  69         }                                               \
  70         if (unlikely(_c)) yield();                      \
  71         else break;                                     \
  72     } while (_c);                                       \
  73   }
  74 #endif                          /* debug */
  75
  76 #define POLL_WHILE_FALSE(_c)    POLL_WHILE_TRUE(!(_c))
  77
  78 static inline void acquire_spu_lock(struct spu *spu)
  79 {
  80         /* Save, Step 1:
  81          * Restore, Step 1:
  82          *    Acquire SPU-specific mutual exclusion lock.
  83          *    TBD.
  84          */
  85 }
  86
  87 static inline void release_spu_lock(struct spu *spu)
  88 {
  89         /* Restore, Step 76:
  90          *    Release SPU-specific mutual exclusion lock.
  91          *    TBD.
  92          */
  93 }
  94
  95 static inline int check_spu_isolate(struct spu_state *csa, struct spu *spu)
  96 {
  97         struct spu_problem __iomem *prob = spu->problem;
  98         u32 isolate_state;
  99
 100         /* Save, Step 2:
 101          * Save, Step 6:
 102          *     If SPU_Status[E,L,IS] any field is '1', this
 103          *     SPU is in isolate state and cannot be context
 104          *     saved at this time.
 105          */
 106         isolate_state = SPU_STATUS_ISOLATED_STATE |
 107             SPU_STATUS_ISOLATED_LOAD_STATUS | SPU_STATUS_ISOLATED_EXIT_STATUS;
 108         return (in_be32(&prob->spu_status_R) & isolate_state) ? 1 : 0;
 109 }
 110
 111 static inline void disable_interrupts(struct spu_state *csa, struct spu *spu)
 112 {
 113         /* Save, Step 3:
 114          * Restore, Step 2:
 115          *     Save INT_Mask_class0 in CSA.
 116          *     Write INT_MASK_class0 with value of 0.
 117          *     Save INT_Mask_class1 in CSA.
 118          *     Write INT_MASK_class1 with value of 0.
 119          *     Save INT_Mask_class2 in CSA.
 120          *     Write INT_MASK_class2 with value of 0.
 121          *     Synchronize all three interrupts to be sure
 122          *     we no longer execute a handler on another CPU.
 123          */
 124         spin_lock_irq(&spu->register_lock);
 125         if (csa) {
 126                 csa->priv1.int_mask_class0_RW = spu_int_mask_get(spu, 0);
 127                 csa->priv1.int_mask_class1_RW = spu_int_mask_get(spu, 1);
 128                 csa->priv1.int_mask_class2_RW = spu_int_mask_get(spu, 2);
 129         }
 130         spu_int_mask_set(spu, 0, 0ul);
 131         spu_int_mask_set(spu, 1, 0ul);
 132         spu_int_mask_set(spu, 2, 0ul);
 133         eieio();
 134         spin_unlock_irq(&spu->register_lock);
 135         synchronize_irq(spu->irqs[0]);
 136         synchronize_irq(spu->irqs[1]);
 137         synchronize_irq(spu->irqs[2]);
 138 }
 139
 140 static inline void set_watchdog_timer(struct spu_state *csa, struct spu *spu)
 141 {
 142         /* Save, Step 4:
 143          * Restore, Step 25.
 144          *    Set a software watchdog timer, which specifies the
 145          *    maximum allowable time for a context save sequence.
 146          *
 147          *    For present, this implementation will not set a global
 148          *    watchdog timer, as virtualization & variable system load
 149          *    may cause unpredictable execution times.
 150          */
 151 }
 152
 153 static inline void inhibit_user_access(struct spu_state *csa, struct spu *spu)
 154 {
 155         /* Save, Step 5:
 156          * Restore, Step 3:
 157          *     Inhibit user-space access (if provided) to this
 158          *     SPU by unmapping the virtual pages assigned to
 159          *     the SPU memory-mapped I/O (MMIO) for problem
 160          *     state. TBD.
 161          */
 162 }
 163
 164 static inline void set_switch_pending(struct spu_state *csa, struct spu *spu)
 165 {
 166         /* Save, Step 7:
 167          * Restore, Step 5:
 168          *     Set a software context switch pending flag.
 169          */
 170         set_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);
 171         mb();
 172 }
 173
 174 static inline void save_mfc_cntl(struct spu_state *csa, struct spu *spu)
 175 {
 176         struct spu_priv2 __iomem *priv2 = spu->priv2;
 177
 178         /* Save, Step 8:
 179          *     Suspend DMA and save MFC_CNTL.
 180          */
 181         switch (in_be64(&priv2->mfc_control_RW) &
 182                MFC_CNTL_SUSPEND_DMA_STATUS_MASK) {
 183         case MFC_CNTL_SUSPEND_IN_PROGRESS:
 184                 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
 185                                   MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
 186                                  MFC_CNTL_SUSPEND_COMPLETE);
 187                 /* fall through */
 188         case MFC_CNTL_SUSPEND_COMPLETE:
 189                 if (csa) {
 190                         csa->priv2.mfc_control_RW =
 191                                 MFC_CNTL_SUSPEND_MASK |
 192                                 MFC_CNTL_SUSPEND_DMA_QUEUE;
 193                 }
 194                 break;
 195         case MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION:
 196                 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
 197                 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
 198                                   MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
 199                                  MFC_CNTL_SUSPEND_COMPLETE);
 200                 if (csa) {
 201                         csa->priv2.mfc_control_RW = 0;
 202                 }
 203                 break;
 204         }
 205 }
 206
 207 static inline void save_spu_runcntl(struct spu_state *csa, struct spu *spu)
 208 {
 209         struct spu_problem __iomem *prob = spu->problem;
 210
 211         /* Save, Step 9:
 212          *     Save SPU_Runcntl in the CSA.  This value contains
 213          *     the "Application Desired State".
 214          */
 215         csa->prob.spu_runcntl_RW = in_be32(&prob->spu_runcntl_RW);
 216 }
 217
 218 static inline void save_mfc_sr1(struct spu_state *csa, struct spu *spu)
 219 {
 220         /* Save, Step 10:
 221          *     Save MFC_SR1 in the CSA.
 222          */
 223         csa->priv1.mfc_sr1_RW = spu_mfc_sr1_get(spu);
 224 }
 225
 226 static inline void save_spu_status(struct spu_state *csa, struct spu *spu)
 227 {
 228         struct spu_problem __iomem *prob = spu->problem;
 229
 230         /* Save, Step 11:
 231          *     Read SPU_Status[R], and save to CSA.
 232          */
 233         if ((in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) == 0) {
 234                 csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
 235         } else {
 236                 u32 stopped;
 237
 238                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
 239                 eieio();
 240                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
 241                                 SPU_STATUS_RUNNING);
 242                 stopped =
 243                     SPU_STATUS_INVALID_INSTR | SPU_STATUS_SINGLE_STEP |
 244                     SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP;
 245                 if ((in_be32(&prob->spu_status_R) & stopped) == 0)
 246                         csa->prob.spu_status_R = SPU_STATUS_RUNNING;
 247                 else
 248                         csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
 249         }
 250 }
 251
 252 static inline void save_mfc_decr(struct spu_state *csa, struct spu *spu)
 253 {
 254         struct spu_priv2 __iomem *priv2 = spu->priv2;
 255
 256         /* Save, Step 12:
 257          *     Read MFC_CNTL[Ds].  Update saved copy of
 258          *     CSA.MFC_CNTL[Ds].
 259          */
 260         csa->priv2.mfc_control_RW |=
 261                 in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DECREMENTER_RUNNING;
 262 }
 263
 264 static inline void halt_mfc_decr(struct spu_state *csa, struct spu *spu)
 265 {
 266         struct spu_priv2 __iomem *priv2 = spu->priv2;
 267
 268         /* Save, Step 13:
 269          *     Write MFC_CNTL[Dh] set to a '1' to halt
 270          *     the decrementer.
 271          */
 272         out_be64(&priv2->mfc_control_RW,
 273                  MFC_CNTL_DECREMENTER_HALTED | MFC_CNTL_SUSPEND_MASK);
 274         eieio();
 275 }
 276
 277 static inline void save_timebase(struct spu_state *csa, struct spu *spu)
 278 {
 279         /* Save, Step 14:
 280          *    Read PPE Timebase High and Timebase low registers
 281          *    and save in CSA.  TBD.
 282          */
 283         csa->suspend_time = get_cycles();
 284 }
 285
 286 static inline void remove_other_spu_access(struct spu_state *csa,
 287                                            struct spu *spu)
 288 {
 289         /* Save, Step 15:
 290          *     Remove other SPU access to this SPU by unmapping
 291          *     this SPU's pages from their address space.  TBD.
 292          */
 293 }
 294
 295 static inline void do_mfc_mssync(struct spu_state *csa, struct spu *spu)
 296 {
 297         struct spu_problem __iomem *prob = spu->problem;
 298
 299         /* Save, Step 16:
 300          * Restore, Step 11.
 301          *     Write SPU_MSSync register. Poll SPU_MSSync[P]
 302          *     for a value of 0.
 303          */
 304         out_be64(&prob->spc_mssync_RW, 1UL);
 305         POLL_WHILE_TRUE(in_be64(&prob->spc_mssync_RW) & MS_SYNC_PENDING);
 306 }
 307
 308 static inline void issue_mfc_tlbie(struct spu_state *csa, struct spu *spu)
 309 {
 310         /* Save, Step 17:
 311          * Restore, Step 12.
 312          * Restore, Step 48.
 313          *     Write TLB_Invalidate_Entry[IS,VPN,L,Lp]=0 register.
 314          *     Then issue a PPE sync instruction.
 315          */
 316         spu_tlb_invalidate(spu);
 317         mb();
 318 }
 319
 320 static inline void handle_pending_interrupts(struct spu_state *csa,
 321                                              struct spu *spu)
 322 {
 323         /* Save, Step 18:
 324          *     Handle any pending interrupts from this SPU
 325          *     here.  This is OS or hypervisor specific.  One
 326          *     option is to re-enable interrupts to handle any
 327          *     pending interrupts, with the interrupt handlers
 328          *     recognizing the software Context Switch Pending
 329          *     flag, to ensure the SPU execution or MFC command
 330          *     queue is not restarted.  TBD.
 331          */
 332 }
 333
 334 static inline void save_mfc_queues(struct spu_state *csa, struct spu *spu)
 335 {
 336         struct spu_priv2 __iomem *priv2 = spu->priv2;
 337         int i;
 338
 339         /* Save, Step 19:
 340          *     If MFC_Cntl[Se]=0 then save
 341          *     MFC command queues.
 342          */
 343         if ((in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DMA_QUEUES_EMPTY) == 0) {
 344                 for (i = 0; i < 8; i++) {
 345                         csa->priv2.puq[i].mfc_cq_data0_RW =
 346                             in_be64(&priv2->puq[i].mfc_cq_data0_RW);
 347                         csa->priv2.puq[i].mfc_cq_data1_RW =
 348                             in_be64(&priv2->puq[i].mfc_cq_data1_RW);
 349                         csa->priv2.puq[i].mfc_cq_data2_RW =
 350                             in_be64(&priv2->puq[i].mfc_cq_data2_RW);
 351                         csa->priv2.puq[i].mfc_cq_data3_RW =
 352                             in_be64(&priv2->puq[i].mfc_cq_data3_RW);
 353                 }
 354                 for (i = 0; i < 16; i++) {
 355                         csa->priv2.spuq[i].mfc_cq_data0_RW =
 356                             in_be64(&priv2->spuq[i].mfc_cq_data0_RW);
 357                         csa->priv2.spuq[i].mfc_cq_data1_RW =
 358                             in_be64(&priv2->spuq[i].mfc_cq_data1_RW);
 359                         csa->priv2.spuq[i].mfc_cq_data2_RW =
 360                             in_be64(&priv2->spuq[i].mfc_cq_data2_RW);
 361                         csa->priv2.spuq[i].mfc_cq_data3_RW =
 362                             in_be64(&priv2->spuq[i].mfc_cq_data3_RW);
 363                 }
 364         }
 365 }
 366
 367 static inline void save_ppu_querymask(struct spu_state *csa, struct spu *spu)
 368 {
 369         struct spu_problem __iomem *prob = spu->problem;
 370
 371         /* Save, Step 20:
 372          *     Save the PPU_QueryMask register
 373          *     in the CSA.
 374          */
 375         csa->prob.dma_querymask_RW = in_be32(&prob->dma_querymask_RW);
 376 }
 377
 378 static inline void save_ppu_querytype(struct spu_state *csa, struct spu *spu)
 379 {
 380         struct spu_problem __iomem *prob = spu->problem;
 381
 382         /* Save, Step 21:
 383          *     Save the PPU_QueryType register
 384          *     in the CSA.
 385          */
 386         csa->prob.dma_querytype_RW = in_be32(&prob->dma_querytype_RW);
 387 }
 388
 389 static inline void save_ppu_tagstatus(struct spu_state *csa, struct spu *spu)
 390 {
 391         struct spu_problem __iomem *prob = spu->problem;
 392
 393         /* Save the Prxy_TagStatus register in the CSA.
 394          *
 395          * It is unnecessary to restore dma_tagstatus_R, however,
 396          * dma_tagstatus_R in the CSA is accessed via backing_ops, so
 397          * we must save it.
 398          */
 399         csa->prob.dma_tagstatus_R = in_be32(&prob->dma_tagstatus_R);
 400 }
 401
 402 static inline void save_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
 403 {
 404         struct spu_priv2 __iomem *priv2 = spu->priv2;
 405
 406         /* Save, Step 22:
 407          *     Save the MFC_CSR_TSQ register
 408          *     in the LSCSA.
 409          */
 410         csa->priv2.spu_tag_status_query_RW =
 411             in_be64(&priv2->spu_tag_status_query_RW);
 412 }
 413
 414 static inline void save_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
 415 {
 416         struct spu_priv2 __iomem *priv2 = spu->priv2;
 417
 418         /* Save, Step 23:
 419          *     Save the MFC_CSR_CMD1 and MFC_CSR_CMD2
 420          *     registers in the CSA.
 421          */
 422         csa->priv2.spu_cmd_buf1_RW = in_be64(&priv2->spu_cmd_buf1_RW);
 423         csa->priv2.spu_cmd_buf2_RW = in_be64(&priv2->spu_cmd_buf2_RW);
 424 }
 425
 426 static inline void save_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
 427 {
 428         struct spu_priv2 __iomem *priv2 = spu->priv2;
 429
 430         /* Save, Step 24:
 431          *     Save the MFC_CSR_ATO register in
 432          *     the CSA.
 433          */
 434         csa->priv2.spu_atomic_status_RW = in_be64(&priv2->spu_atomic_status_RW);
 435 }
 436
 437 static inline void save_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
 438 {
 439         /* Save, Step 25:
 440          *     Save the MFC_TCLASS_ID register in
 441          *     the CSA.
 442          */
 443         csa->priv1.mfc_tclass_id_RW = spu_mfc_tclass_id_get(spu);
 444 }
 445
 446 static inline void set_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
 447 {
 448         /* Save, Step 26:
 449          * Restore, Step 23.
 450          *     Write the MFC_TCLASS_ID register with
 451          *     the value 0x10000000.
 452          */
 453         spu_mfc_tclass_id_set(spu, 0x10000000);
 454         eieio();
 455 }
 456
 457 static inline void purge_mfc_queue(struct spu_state *csa, struct spu *spu)
 458 {
 459         struct spu_priv2 __iomem *priv2 = spu->priv2;
 460
 461         /* Save, Step 27:
 462          * Restore, Step 14.
 463          *     Write MFC_CNTL[Pc]=1 (purge queue).
 464          */
 465         out_be64(&priv2->mfc_control_RW,
 466                         MFC_CNTL_PURGE_DMA_REQUEST |
 467                         MFC_CNTL_SUSPEND_MASK);
 468         eieio();
 469 }
 470
 471 static inline void wait_purge_complete(struct spu_state *csa, struct spu *spu)
 472 {
 473         struct spu_priv2 __iomem *priv2 = spu->priv2;
 474
 475         /* Save, Step 28:
 476          *     Poll MFC_CNTL[Ps] until value '11' is read
 477          *     (purge complete).
 478          */
 479         POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
 480                          MFC_CNTL_PURGE_DMA_STATUS_MASK) ==
 481                          MFC_CNTL_PURGE_DMA_COMPLETE);
 482 }
 483
 484 static inline void setup_mfc_sr1(struct spu_state *csa, struct spu *spu)
 485 {
 486         /* Save, Step 30:
 487          * Restore, Step 18:
 488          *     Write MFC_SR1 with MFC_SR1[D=0,S=1] and
 489          *     MFC_SR1[TL,R,Pr,T] set correctly for the
 490          *     OS specific environment.
 491          *
 492          *     Implementation note: The SPU-side code
 493          *     for save/restore is privileged, so the
 494          *     MFC_SR1[Pr] bit is not set.
 495          *
 496          */
 497         spu_mfc_sr1_set(spu, (MFC_STATE1_MASTER_RUN_CONTROL_MASK |
 498                               MFC_STATE1_RELOCATE_MASK |
 499                               MFC_STATE1_BUS_TLBIE_MASK));
 500 }
 501
 502 static inline void save_spu_npc(struct spu_state *csa, struct spu *spu)
 503 {
 504         struct spu_problem __iomem *prob = spu->problem;
 505
 506         /* Save, Step 31:
 507          *     Save SPU_NPC in the CSA.
 508          */
 509         csa->prob.spu_npc_RW = in_be32(&prob->spu_npc_RW);
 510 }
 511
 512 static inline void save_spu_privcntl(struct spu_state *csa, struct spu *spu)
 513 {
 514         struct spu_priv2 __iomem *priv2 = spu->priv2;
 515
 516         /* Save, Step 32:
 517          *     Save SPU_PrivCntl in the CSA.
 518          */
 519         csa->priv2.spu_privcntl_RW = in_be64(&priv2->spu_privcntl_RW);
 520 }
 521
 522 static inline void reset_spu_privcntl(struct spu_state *csa, struct spu *spu)
 523 {
 524         struct spu_priv2 __iomem *priv2 = spu->priv2;
 525
 526         /* Save, Step 33:
 527          * Restore, Step 16:
 528          *     Write SPU_PrivCntl[S,Le,A] fields reset to 0.
 529          */
 530         out_be64(&priv2->spu_privcntl_RW, 0UL);
 531         eieio();
 532 }
 533
 534 static inline void save_spu_lslr(struct spu_state *csa, struct spu *spu)
 535 {
 536         struct spu_priv2 __iomem *priv2 = spu->priv2;
 537
 538         /* Save, Step 34:
 539          *     Save SPU_LSLR in the CSA.
 540          */
 541         csa->priv2.spu_lslr_RW = in_be64(&priv2->spu_lslr_RW);
 542 }
 543
 544 static inline void reset_spu_lslr(struct spu_state *csa, struct spu *spu)
 545 {
 546         struct spu_priv2 __iomem *priv2 = spu->priv2;
 547
 548         /* Save, Step 35:
 549          * Restore, Step 17.
 550          *     Reset SPU_LSLR.
 551          */
 552         out_be64(&priv2->spu_lslr_RW, LS_ADDR_MASK);
 553         eieio();
 554 }
 555
 556 static inline void save_spu_cfg(struct spu_state *csa, struct spu *spu)
 557 {
 558         struct spu_priv2 __iomem *priv2 = spu->priv2;
 559
 560         /* Save, Step 36:
 561          *     Save SPU_Cfg in the CSA.
 562          */
 563         csa->priv2.spu_cfg_RW = in_be64(&priv2->spu_cfg_RW);
 564 }
 565
 566 static inline void save_pm_trace(struct spu_state *csa, struct spu *spu)
 567 {
 568         /* Save, Step 37:
 569          *     Save PM_Trace_Tag_Wait_Mask in the CSA.
 570          *     Not performed by this implementation.
 571          */
 572 }
 573
 574 static inline void save_mfc_rag(struct spu_state *csa, struct spu *spu)
 575 {
 576         /* Save, Step 38:
 577          *     Save RA_GROUP_ID register and the
 578          *     RA_ENABLE reigster in the CSA.
 579          */
 580         csa->priv1.resource_allocation_groupID_RW =
 581                 spu_resource_allocation_groupID_get(spu);
 582         csa->priv1.resource_allocation_enable_RW =
 583                 spu_resource_allocation_enable_get(spu);
 584 }
 585
 586 static inline void save_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
 587 {
 588         struct spu_problem __iomem *prob = spu->problem;
 589
 590         /* Save, Step 39:
 591          *     Save MB_Stat register in the CSA.
 592          */
 593         csa->prob.mb_stat_R = in_be32(&prob->mb_stat_R);
 594 }
 595
 596 static inline void save_ppu_mb(struct spu_state *csa, struct spu *spu)
 597 {
 598         struct spu_problem __iomem *prob = spu->problem;
 599
 600         /* Save, Step 40:
 601          *     Save the PPU_MB register in the CSA.
 602          */
 603         csa->prob.pu_mb_R = in_be32(&prob->pu_mb_R);
 604 }
 605
 606 static inline void save_ppuint_mb(struct spu_state *csa, struct spu *spu)
 607 {
 608         struct spu_priv2 __iomem *priv2 = spu->priv2;
 609
 610         /* Save, Step 41:
 611          *     Save the PPUINT_MB register in the CSA.
 612          */
 613         csa->priv2.puint_mb_R = in_be64(&priv2->puint_mb_R);
 614 }
 615
 616 static inline void save_ch_part1(struct spu_state *csa, struct spu *spu)
 617 {
 618         struct spu_priv2 __iomem *priv2 = spu->priv2;
 619         u64 idx, ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
 620         int i;
 621
 622         /* Save, Step 42:
 623          */
 624
 625         /* Save CH 1, without channel count */
 626         out_be64(&priv2->spu_chnlcntptr_RW, 1);
 627         csa->spu_chnldata_RW[1] = in_be64(&priv2->spu_chnldata_RW);
 628
 629         /* Save the following CH: [0,3,4,24,25,27] */
 630         for (i = 0; i < ARRAY_SIZE(ch_indices); i++) {
 631                 idx = ch_indices[i];
 632                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
 633                 eieio();
 634                 csa->spu_chnldata_RW[idx] = in_be64(&priv2->spu_chnldata_RW);
 635                 csa->spu_chnlcnt_RW[idx] = in_be64(&priv2->spu_chnlcnt_RW);
 636                 out_be64(&priv2->spu_chnldata_RW, 0UL);
 637                 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
 638                 eieio();
 639         }
 640 }
 641
 642 static inline void save_spu_mb(struct spu_state *csa, struct spu *spu)
 643 {
 644         struct spu_priv2 __iomem *priv2 = spu->priv2;
 645         int i;
 646
 647         /* Save, Step 43:
 648          *     Save SPU Read Mailbox Channel.
 649          */
 650         out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
 651         eieio();
 652         csa->spu_chnlcnt_RW[29] = in_be64(&priv2->spu_chnlcnt_RW);
 653         for (i = 0; i < 4; i++) {
 654                 csa->spu_mailbox_data[i] = in_be64(&priv2->spu_chnldata_RW);
 655         }
 656         out_be64(&priv2->spu_chnlcnt_RW, 0UL);
 657         eieio();
 658 }
 659
 660 static inline void save_mfc_cmd(struct spu_state *csa, struct spu *spu)
 661 {
 662         struct spu_priv2 __iomem *priv2 = spu->priv2;
 663
 664         /* Save, Step 44:
 665          *     Save MFC_CMD Channel.
 666          */
 667         out_be64(&priv2->spu_chnlcntptr_RW, 21UL);
 668         eieio();
 669         csa->spu_chnlcnt_RW[21] = in_be64(&priv2->spu_chnlcnt_RW);
 670         eieio();
 671 }
 672
 673 static inline void reset_ch(struct spu_state *csa, struct spu *spu)
 674 {
 675         struct spu_priv2 __iomem *priv2 = spu->priv2;
 676         u64 ch_indices[4] = { 21UL, 23UL, 28UL, 30UL };
 677         u64 ch_counts[4] = { 16UL, 1UL, 1UL, 1UL };
 678         u64 idx;
 679         int i;
 680
 681         /* Save, Step 45:
 682          *     Reset the following CH: [21, 23, 28, 30]
 683          */
 684         for (i = 0; i < 4; i++) {
 685                 idx = ch_indices[i];
 686                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
 687                 eieio();
 688                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
 689                 eieio();
 690         }
 691 }
 692
 693 static inline void resume_mfc_queue(struct spu_state *csa, struct spu *spu)
 694 {
 695         struct spu_priv2 __iomem *priv2 = spu->priv2;
 696
 697         /* Save, Step 46:
 698          * Restore, Step 25.
 699          *     Write MFC_CNTL[Sc]=0 (resume queue processing).
 700          */
 701         out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESUME_DMA_QUEUE);
 702 }
 703
 704 static inline void setup_mfc_slbs(struct spu_state *csa, struct spu *spu,
 705                 unsigned int *code, int code_size)
 706 {
 707         /* Save, Step 47:
 708          * Restore, Step 30.
 709          *     If MFC_SR1[R]=1, write 0 to SLB_Invalidate_All
 710          *     register, then initialize SLB_VSID and SLB_ESID
 711          *     to provide access to SPU context save code and
 712          *     LSCSA.
 713          *
 714          *     This implementation places both the context
 715          *     switch code and LSCSA in kernel address space.
 716          *
 717          *     Further this implementation assumes that the
 718          *     MFC_SR1[R]=1 (in other words, assume that
 719          *     translation is desired by OS environment).
 720          */
 721         spu_invalidate_slbs(spu);
 722         spu_setup_kernel_slbs(spu, csa->lscsa, code, code_size);
 723 }
 724
 725 static inline void set_switch_active(struct spu_state *csa, struct spu *spu)
 726 {
 727         /* Save, Step 48:
 728          * Restore, Step 23.
 729          *     Change the software context switch pending flag
 730          *     to context switch active.
 731          *
 732          *     This implementation does not uses a switch active flag.
 733          */
 734         clear_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);
 735         mb();
 736 }
 737
 738 static inline void enable_interrupts(struct spu_state *csa, struct spu *spu)
 739 {
 740         unsigned long class1_mask = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
 741             CLASS1_ENABLE_STORAGE_FAULT_INTR;
 742
 743         /* Save, Step 49:
 744          * Restore, Step 22:
 745          *     Reset and then enable interrupts, as
 746          *     needed by OS.
 747          *
 748          *     This implementation enables only class1
 749          *     (translation) interrupts.
 750          */
 751         spin_lock_irq(&spu->register_lock);
 752         spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
 753         spu_int_stat_clear(spu, 1, CLASS1_INTR_MASK);
 754         spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
 755         spu_int_mask_set(spu, 0, 0ul);
 756         spu_int_mask_set(spu, 1, class1_mask);
 757         spu_int_mask_set(spu, 2, 0ul);
 758         spin_unlock_irq(&spu->register_lock);
 759 }
 760
 761 static inline int send_mfc_dma(struct spu *spu, unsigned long ea,
 762                                unsigned int ls_offset, unsigned int size,
 763                                unsigned int tag, unsigned int rclass,
 764                                unsigned int cmd)
 765 {
 766         struct spu_problem __iomem *prob = spu->problem;
 767         union mfc_tag_size_class_cmd command;
 768         unsigned int transfer_size;
 769         volatile unsigned int status = 0x0;
 770
 771         while (size > 0) {
 772                 transfer_size =
 773                     (size > MFC_MAX_DMA_SIZE) ? MFC_MAX_DMA_SIZE : size;
 774                 command.u.mfc_size = transfer_size;
 775                 command.u.mfc_tag = tag;
 776                 command.u.mfc_rclassid = rclass;
 777                 command.u.mfc_cmd = cmd;
 778                 do {
 779                         out_be32(&prob->mfc_lsa_W, ls_offset);
 780                         out_be64(&prob->mfc_ea_W, ea);
 781                         out_be64(&prob->mfc_union_W.all64, command.all64);
 782                         status =
 783                             in_be32(&prob->mfc_union_W.by32.mfc_class_cmd32);
 784                         if (unlikely(status & 0x2)) {
 785                                 cpu_relax();
 786                         }
 787                 } while (status & 0x3);
 788                 size -= transfer_size;
 789                 ea += transfer_size;
 790                 ls_offset += transfer_size;
 791         }
 792         return 0;
 793 }
 794
 795 static inline void save_ls_16kb(struct spu_state *csa, struct spu *spu)
 796 {
 797         unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
 798         unsigned int ls_offset = 0x0;
 799         unsigned int size = 16384;
 800         unsigned int tag = 0;
 801         unsigned int rclass = 0;
 802         unsigned int cmd = MFC_PUT_CMD;
 803
 804         /* Save, Step 50:
 805          *     Issue a DMA command to copy the first 16K bytes
 806          *     of local storage to the CSA.
 807          */
 808         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
 809 }
 810
 811 static inline void set_spu_npc(struct spu_state *csa, struct spu *spu)
 812 {
 813         struct spu_problem __iomem *prob = spu->problem;
 814
 815         /* Save, Step 51:
 816          * Restore, Step 31.
 817          *     Write SPU_NPC[IE]=0 and SPU_NPC[LSA] to entry
 818          *     point address of context save code in local
 819          *     storage.
 820          *
 821          *     This implementation uses SPU-side save/restore
 822          *     programs with entry points at LSA of 0.
 823          */
 824         out_be32(&prob->spu_npc_RW, 0);
 825         eieio();
 826 }
 827
 828 static inline void set_signot1(struct spu_state *csa, struct spu *spu)
 829 {
 830         struct spu_problem __iomem *prob = spu->problem;
 831         union {
 832                 u64 ull;
 833                 u32 ui[2];
 834         } addr64;
 835
 836         /* Save, Step 52:
 837          * Restore, Step 32:
 838          *    Write SPU_Sig_Notify_1 register with upper 32-bits
 839          *    of the CSA.LSCSA effective address.
 840          */
 841         addr64.ull = (u64) csa->lscsa;
 842         out_be32(&prob->signal_notify1, addr64.ui[0]);
 843         eieio();
 844 }
 845
 846 static inline void set_signot2(struct spu_state *csa, struct spu *spu)
 847 {
 848         struct spu_problem __iomem *prob = spu->problem;
 849         union {
 850                 u64 ull;
 851                 u32 ui[2];
 852         } addr64;
 853
 854         /* Save, Step 53:
 855          * Restore, Step 33:
 856          *    Write SPU_Sig_Notify_2 register with lower 32-bits
 857          *    of the CSA.LSCSA effective address.
 858          */
 859         addr64.ull = (u64) csa->lscsa;
 860         out_be32(&prob->signal_notify2, addr64.ui[1]);
 861         eieio();
 862 }
 863
 864 static inline void send_save_code(struct spu_state *csa, struct spu *spu)
 865 {
 866         unsigned long addr = (unsigned long)&spu_save_code[0];
 867         unsigned int ls_offset = 0x0;
 868         unsigned int size = sizeof(spu_save_code);
 869         unsigned int tag = 0;
 870         unsigned int rclass = 0;
 871         unsigned int cmd = MFC_GETFS_CMD;
 872
 873         /* Save, Step 54:
 874          *     Issue a DMA command to copy context save code
 875          *     to local storage and start SPU.
 876          */
 877         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
 878 }
 879
 880 static inline void set_ppu_querymask(struct spu_state *csa, struct spu *spu)
 881 {
 882         struct spu_problem __iomem *prob = spu->problem;
 883
 884         /* Save, Step 55:
 885          * Restore, Step 38.
 886          *     Write PPU_QueryMask=1 (enable Tag Group 0)
 887          *     and issue eieio instruction.
 888          */
 889         out_be32(&prob->dma_querymask_RW, MFC_TAGID_TO_TAGMASK(0));
 890         eieio();
 891 }
 892
 893 static inline void wait_tag_complete(struct spu_state *csa, struct spu *spu)
 894 {
 895         struct spu_problem __iomem *prob = spu->problem;
 896         u32 mask = MFC_TAGID_TO_TAGMASK(0);
 897         unsigned long flags;
 898
 899         /* Save, Step 56:
 900          * Restore, Step 39.
 901          * Restore, Step 39.
 902          * Restore, Step 46.
 903          *     Poll PPU_TagStatus[gn] until 01 (Tag group 0 complete)
 904          *     or write PPU_QueryType[TS]=01 and wait for Tag Group
 905          *     Complete Interrupt.  Write INT_Stat_Class0 or
 906          *     INT_Stat_Class2 with value of 'handled'.
 907          */
 908         POLL_WHILE_FALSE(in_be32(&prob->dma_tagstatus_R) & mask);
 909
 910         local_irq_save(flags);
 911         spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
 912         spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
 913         local_irq_restore(flags);
 914 }
 915
 916 static inline void wait_spu_stopped(struct spu_state *csa, struct spu *spu)
 917 {
 918         struct spu_problem __iomem *prob = spu->problem;
 919         unsigned long flags;
 920
 921         /* Save, Step 57:
 922          * Restore, Step 40.
 923          *     Poll until SPU_Status[R]=0 or wait for SPU Class 0
 924          *     or SPU Class 2 interrupt.  Write INT_Stat_class0
 925          *     or INT_Stat_class2 with value of handled.
 926          */
 927         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
 928
 929         local_irq_save(flags);
 930         spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
 931         spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
 932         local_irq_restore(flags);
 933 }
 934
 935 static inline int check_save_status(struct spu_state *csa, struct spu *spu)
 936 {
 937         struct spu_problem __iomem *prob = spu->problem;
 938         u32 complete;
 939
 940         /* Save, Step 54:
 941          *     If SPU_Status[P]=1 and SPU_Status[SC] = "success",
 942          *     context save succeeded, otherwise context save
 943          *     failed.
 944          */
 945         complete = ((SPU_SAVE_COMPLETE << SPU_STOP_STATUS_SHIFT) |
 946                     SPU_STATUS_STOPPED_BY_STOP);
 947         return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0;
 948 }
 949
 950 static inline void terminate_spu_app(struct spu_state *csa, struct spu *spu)
 951 {
 952         /* Restore, Step 4:
 953          *    If required, notify the "using application" that
 954          *    the SPU task has been terminated.  TBD.
 955          */
 956 }
 957
 958 static inline void suspend_mfc_and_halt_decr(struct spu_state *csa,
 959                 struct spu *spu)
 960 {
 961         struct spu_priv2 __iomem *priv2 = spu->priv2;
 962
 963         /* Restore, Step 7:
 964          *     Write MFC_Cntl[Dh,Sc,Sm]='1','1','0' to suspend
 965          *     the queue and halt the decrementer.
 966          */
 967         out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE |
 968                  MFC_CNTL_DECREMENTER_HALTED);
 969         eieio();
 970 }
 971
 972 static inline void wait_suspend_mfc_complete(struct spu_state *csa,
 973                                              struct spu *spu)
 974 {
 975         struct spu_priv2 __iomem *priv2 = spu->priv2;
 976
 977         /* Restore, Step 8:
 978          * Restore, Step 47.
 979          *     Poll MFC_CNTL[Ss] until 11 is returned.
 980          */
 981         POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
 982                          MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
 983                          MFC_CNTL_SUSPEND_COMPLETE);
 984 }
 985
 986 static inline int suspend_spe(struct spu_state *csa, struct spu *spu)
 987 {
 988         struct spu_problem __iomem *prob = spu->problem;
 989
 990         /* Restore, Step 9:
 991          *    If SPU_Status[R]=1, stop SPU execution
 992          *    and wait for stop to complete.
 993          *
 994          *    Returns       1 if SPU_Status[R]=1 on entry.
 995          *                  0 otherwise
 996          */
 997         if (in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) {
 998                 if (in_be32(&prob->spu_status_R) &
 999                     SPU_STATUS_ISOLATED_EXIT_STATUS) {
1000                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1001                                         SPU_STATUS_RUNNING);
1002                 }
1003                 if ((in_be32(&prob->spu_status_R) &
1004                      SPU_STATUS_ISOLATED_LOAD_STATUS)
1005                     || (in_be32(&prob->spu_status_R) &
1006                         SPU_STATUS_ISOLATED_STATE)) {
1007                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1008                         eieio();
1009                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1010                                         SPU_STATUS_RUNNING);
1011                         out_be32(&prob->spu_runcntl_RW, 0x2);
1012                         eieio();
1013                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1014                                         SPU_STATUS_RUNNING);
1015                 }
1016                 if (in_be32(&prob->spu_status_R) &
1017                     SPU_STATUS_WAITING_FOR_CHANNEL) {
1018                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1019                         eieio();
1020                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1021                                         SPU_STATUS_RUNNING);
1022                 }
1023                 return 1;
1024         }
1025         return 0;
1026 }
1027
1028 static inline void clear_spu_status(struct spu_state *csa, struct spu *spu)
1029 {
1030         struct spu_problem __iomem *prob = spu->problem;
1031
1032         /* Restore, Step 10:
1033          *    If SPU_Status[R]=0 and SPU_Status[E,L,IS]=1,
1034          *    release SPU from isolate state.
1035          */
1036         if (!(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING)) {
1037                 if (in_be32(&prob->spu_status_R) &
1038                     SPU_STATUS_ISOLATED_EXIT_STATUS) {
1039                         spu_mfc_sr1_set(spu,
1040                                         MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1041                         eieio();
1042                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1043                         eieio();
1044                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1045                                         SPU_STATUS_RUNNING);
1046                 }
1047                 if ((in_be32(&prob->spu_status_R) &
1048                      SPU_STATUS_ISOLATED_LOAD_STATUS)
1049                     || (in_be32(&prob->spu_status_R) &
1050                         SPU_STATUS_ISOLATED_STATE)) {
1051                         spu_mfc_sr1_set(spu,
1052                                         MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1053                         eieio();
1054                         out_be32(&prob->spu_runcntl_RW, 0x2);
1055                         eieio();
1056                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1057                                         SPU_STATUS_RUNNING);
1058                 }
1059         }
1060 }
1061
1062 static inline void reset_ch_part1(struct spu_state *csa, struct spu *spu)
1063 {
1064         struct spu_priv2 __iomem *priv2 = spu->priv2;
1065         u64 ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
1066         u64 idx;
1067         int i;
1068
1069         /* Restore, Step 20:
1070          */
1071
1072         /* Reset CH 1 */
1073         out_be64(&priv2->spu_chnlcntptr_RW, 1);
1074         out_be64(&priv2->spu_chnldata_RW, 0UL);
1075
1076         /* Reset the following CH: [0,3,4,24,25,27] */
1077         for (i = 0; i < ARRAY_SIZE(ch_indices); i++) {
1078                 idx = ch_indices[i];
1079                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1080                 eieio();
1081                 out_be64(&priv2->spu_chnldata_RW, 0UL);
1082                 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
1083                 eieio();
1084         }
1085 }
1086
1087 static inline void reset_ch_part2(struct spu_state *csa, struct spu *spu)
1088 {
1089         struct spu_priv2 __iomem *priv2 = spu->priv2;
1090         u64 ch_indices[5] = { 21UL, 23UL, 28UL, 29UL, 30UL };
1091         u64 ch_counts[5] = { 16UL, 1UL, 1UL, 0UL, 1UL };
1092         u64 idx;
1093         int i;
1094
1095         /* Restore, Step 21:
1096          *     Reset the following CH: [21, 23, 28, 29, 30]
1097          */
1098         for (i = 0; i < 5; i++) {
1099                 idx = ch_indices[i];
1100                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1101                 eieio();
1102                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1103                 eieio();
1104         }
1105 }
1106
1107 static inline void setup_spu_status_part1(struct spu_state *csa,
1108                                           struct spu *spu)
1109 {
1110         u32 status_P = SPU_STATUS_STOPPED_BY_STOP;
1111         u32 status_I = SPU_STATUS_INVALID_INSTR;
1112         u32 status_H = SPU_STATUS_STOPPED_BY_HALT;
1113         u32 status_S = SPU_STATUS_SINGLE_STEP;
1114         u32 status_S_I = SPU_STATUS_SINGLE_STEP | SPU_STATUS_INVALID_INSTR;
1115         u32 status_S_P = SPU_STATUS_SINGLE_STEP | SPU_STATUS_STOPPED_BY_STOP;
1116         u32 status_P_H = SPU_STATUS_STOPPED_BY_HALT |SPU_STATUS_STOPPED_BY_STOP;
1117         u32 status_P_I = SPU_STATUS_STOPPED_BY_STOP |SPU_STATUS_INVALID_INSTR;
1118         u32 status_code;
1119
1120         /* Restore, Step 27:
1121          *     If the CSA.SPU_Status[I,S,H,P]=1 then add the correct
1122          *     instruction sequence to the end of the SPU based restore
1123          *     code (after the "context restored" stop and signal) to
1124          *     restore the correct SPU status.
1125          *
1126          *     NOTE: Rather than modifying the SPU executable, we
1127          *     instead add a new 'stopped_status' field to the
1128          *     LSCSA.  The SPU-side restore reads this field and
1129          *     takes the appropriate action when exiting.
1130          */
1131
1132         status_code =
1133             (csa->prob.spu_status_R >> SPU_STOP_STATUS_SHIFT) & 0xFFFF;
1134         if ((csa->prob.spu_status_R & status_P_I) == status_P_I) {
1135
1136                 /* SPU_Status[P,I]=1 - Illegal Instruction followed
1137                  * by Stop and Signal instruction, followed by 'br -4'.
1138                  *
1139                  */
1140                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_I;
1141                 csa->lscsa->stopped_status.slot[1] = status_code;
1142
1143         } else if ((csa->prob.spu_status_R & status_P_H) == status_P_H) {
1144
1145                 /* SPU_Status[P,H]=1 - Halt Conditional, followed
1146                  * by Stop and Signal instruction, followed by
1147                  * 'br -4'.
1148                  */
1149                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_H;
1150                 csa->lscsa->stopped_status.slot[1] = status_code;
1151
1152         } else if ((csa->prob.spu_status_R & status_S_P) == status_S_P) {
1153
1154                 /* SPU_Status[S,P]=1 - Stop and Signal instruction
1155                  * followed by 'br -4'.
1156                  */
1157                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_P;
1158                 csa->lscsa->stopped_status.slot[1] = status_code;
1159
1160         } else if ((csa->prob.spu_status_R & status_S_I) == status_S_I) {
1161
1162                 /* SPU_Status[S,I]=1 - Illegal instruction followed
1163                  * by 'br -4'.
1164                  */
1165                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_I;
1166                 csa->lscsa->stopped_status.slot[1] = status_code;
1167
1168         } else if ((csa->prob.spu_status_R & status_P) == status_P) {
1169
1170                 /* SPU_Status[P]=1 - Stop and Signal instruction
1171                  * followed by 'br -4'.
1172                  */
1173                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P;
1174                 csa->lscsa->stopped_status.slot[1] = status_code;
1175
1176         } else if ((csa->prob.spu_status_R & status_H) == status_H) {
1177
1178                 /* SPU_Status[H]=1 - Halt Conditional, followed
1179                  * by 'br -4'.
1180                  */
1181                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_H;
1182
1183         } else if ((csa->prob.spu_status_R & status_S) == status_S) {
1184
1185                 /* SPU_Status[S]=1 - Two nop instructions.
1186                  */
1187                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S;
1188
1189         } else if ((csa->prob.spu_status_R & status_I) == status_I) {
1190
1191                 /* SPU_Status[I]=1 - Illegal instruction followed
1192                  * by 'br -4'.
1193                  */
1194                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_I;
1195
1196         }
1197 }
1198
1199 static inline void setup_spu_status_part2(struct spu_state *csa,
1200                                           struct spu *spu)
1201 {
1202         u32 mask;
1203
1204         /* Restore, Step 28:
1205          *     If the CSA.SPU_Status[I,S,H,P,R]=0 then
1206          *     add a 'br *' instruction to the end of
1207          *     the SPU based restore code.
1208          *
1209          *     NOTE: Rather than modifying the SPU executable, we
1210          *     instead add a new 'stopped_status' field to the
1211          *     LSCSA.  The SPU-side restore reads this field and
1212          *     takes the appropriate action when exiting.
1213          */
1214         mask = SPU_STATUS_INVALID_INSTR |
1215             SPU_STATUS_SINGLE_STEP |
1216             SPU_STATUS_STOPPED_BY_HALT |
1217             SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING;
1218         if (!(csa->prob.spu_status_R & mask)) {
1219                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_R;
1220         }
1221 }
1222
1223 static inline void restore_mfc_rag(struct spu_state *csa, struct spu *spu)
1224 {
1225         /* Restore, Step 29:
1226          *     Restore RA_GROUP_ID register and the
1227          *     RA_ENABLE reigster from the CSA.
1228          */
1229         spu_resource_allocation_groupID_set(spu,
1230                         csa->priv1.resource_allocation_groupID_RW);
1231         spu_resource_allocation_enable_set(spu,
1232                         csa->priv1.resource_allocation_enable_RW);
1233 }
1234
1235 static inline void send_restore_code(struct spu_state *csa, struct spu *spu)
1236 {
1237         unsigned long addr = (unsigned long)&spu_restore_code[0];
1238         unsigned int ls_offset = 0x0;
1239         unsigned int size = sizeof(spu_restore_code);
1240         unsigned int tag = 0;
1241         unsigned int rclass = 0;
1242         unsigned int cmd = MFC_GETFS_CMD;
1243
1244         /* Restore, Step 37:
1245          *     Issue MFC DMA command to copy context
1246          *     restore code to local storage.
1247          */
1248         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
1249 }
1250
1251 static inline void setup_decr(struct spu_state *csa, struct spu *spu)
1252 {
1253         /* Restore, Step 34:
1254          *     If CSA.MFC_CNTL[Ds]=1 (decrementer was
1255          *     running) then adjust decrementer, set
1256          *     decrementer running status in LSCSA,
1257          *     and set decrementer "wrapped" status
1258          *     in LSCSA.
1259          */
1260         if (csa->priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) {
1261                 cycles_t resume_time = get_cycles();
1262                 cycles_t delta_time = resume_time - csa->suspend_time;
1263
1264                 csa->lscsa->decr_status.slot[0] = SPU_DECR_STATUS_RUNNING;
1265                 if (csa->lscsa->decr.slot[0] < delta_time) {
1266                         csa->lscsa->decr_status.slot[0] |=
1267                                  SPU_DECR_STATUS_WRAPPED;
1268                 }
1269
1270                 csa->lscsa->decr.slot[0] -= delta_time;
1271         } else {
1272                 csa->lscsa->decr_status.slot[0] = 0;
1273         }
1274 }
1275
1276 static inline void setup_ppu_mb(struct spu_state *csa, struct spu *spu)
1277 {
1278         /* Restore, Step 35:
1279          *     Copy the CSA.PU_MB data into the LSCSA.
1280          */
1281         csa->lscsa->ppu_mb.slot[0] = csa->prob.pu_mb_R;
1282 }
1283
1284 static inline void setup_ppuint_mb(struct spu_state *csa, struct spu *spu)
1285 {
1286         /* Restore, Step 36:
1287          *     Copy the CSA.PUINT_MB data into the LSCSA.
1288          */
1289         csa->lscsa->ppuint_mb.slot[0] = csa->priv2.puint_mb_R;
1290 }
1291
1292 static inline int check_restore_status(struct spu_state *csa, struct spu *spu)
1293 {
1294         struct spu_problem __iomem *prob = spu->problem;
1295         u32 complete;
1296
1297         /* Restore, Step 40:
1298          *     If SPU_Status[P]=1 and SPU_Status[SC] = "success",
1299          *     context restore succeeded, otherwise context restore
1300          *     failed.
1301          */
1302         complete = ((SPU_RESTORE_COMPLETE << SPU_STOP_STATUS_SHIFT) |
1303                     SPU_STATUS_STOPPED_BY_STOP);
1304         return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0;
1305 }
1306
1307 static inline void restore_spu_privcntl(struct spu_state *csa, struct spu *spu)
1308 {
1309         struct spu_priv2 __iomem *priv2 = spu->priv2;
1310
1311         /* Restore, Step 41:
1312          *     Restore SPU_PrivCntl from the CSA.
1313          */
1314         out_be64(&priv2->spu_privcntl_RW, csa->priv2.spu_privcntl_RW);
1315         eieio();
1316 }
1317
1318 static inline void restore_status_part1(struct spu_state *csa, struct spu *spu)
1319 {
1320         struct spu_problem __iomem *prob = spu->problem;
1321         u32 mask;
1322
1323         /* Restore, Step 42:
1324          *     If any CSA.SPU_Status[I,S,H,P]=1, then
1325          *     restore the error or single step state.
1326          */
1327         mask = SPU_STATUS_INVALID_INSTR |
1328             SPU_STATUS_SINGLE_STEP |
1329             SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP;
1330         if (csa->prob.spu_status_R & mask) {
1331                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1332                 eieio();
1333                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1334                                 SPU_STATUS_RUNNING);
1335         }
1336 }
1337
1338 static inline void restore_status_part2(struct spu_state *csa, struct spu *spu)
1339 {
1340         struct spu_problem __iomem *prob = spu->problem;
1341         u32 mask;
1342
1343         /* Restore, Step 43:
1344          *     If all CSA.SPU_Status[I,S,H,P,R]=0 then write
1345          *     SPU_RunCntl[R0R1]='01', wait for SPU_Status[R]=1,
1346          *     then write '00' to SPU_RunCntl[R0R1] and wait
1347          *     for SPU_Status[R]=0.
1348          */
1349         mask = SPU_STATUS_INVALID_INSTR |
1350             SPU_STATUS_SINGLE_STEP |
1351             SPU_STATUS_STOPPED_BY_HALT |
1352             SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING;
1353         if (!(csa->prob.spu_status_R & mask)) {
1354                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1355                 eieio();
1356                 POLL_WHILE_FALSE(in_be32(&prob->spu_status_R) &
1357                                  SPU_STATUS_RUNNING);
1358                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1359                 eieio();
1360                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1361                                 SPU_STATUS_RUNNING);
1362         }
1363 }
1364
1365 static inline void restore_ls_16kb(struct spu_state *csa, struct spu *spu)
1366 {
1367         unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
1368         unsigned int ls_offset = 0x0;
1369         unsigned int size = 16384;
1370         unsigned int tag = 0;
1371         unsigned int rclass = 0;
1372         unsigned int cmd = MFC_GET_CMD;
1373
1374         /* Restore, Step 44:
1375          *     Issue a DMA command to restore the first
1376          *     16kb of local storage from CSA.
1377          */
1378         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
1379 }
1380
1381 static inline void suspend_mfc(struct spu_state *csa, struct spu *spu)
1382 {
1383         struct spu_priv2 __iomem *priv2 = spu->priv2;
1384
1385         /* Restore, Step 47.
1386          *     Write MFC_Cntl[Sc,Sm]='1','0' to suspend
1387          *     the queue.
1388          */
1389         out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
1390         eieio();
1391 }
1392
1393 static inline void clear_interrupts(struct spu_state *csa, struct spu *spu)
1394 {
1395         /* Restore, Step 49:
1396          *     Write INT_MASK_class0 with value of 0.
1397          *     Write INT_MASK_class1 with value of 0.
1398          *     Write INT_MASK_class2 with value of 0.
1399          *     Write INT_STAT_class0 with value of -1.
1400          *     Write INT_STAT_class1 with value of -1.
1401          *     Write INT_STAT_class2 with value of -1.
1402          */
1403         spin_lock_irq(&spu->register_lock);
1404         spu_int_mask_set(spu, 0, 0ul);
1405         spu_int_mask_set(spu, 1, 0ul);
1406         spu_int_mask_set(spu, 2, 0ul);
1407         spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
1408         spu_int_stat_clear(spu, 1, CLASS1_INTR_MASK);
1409         spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
1410         spin_unlock_irq(&spu->register_lock);
1411 }
1412
1413 static inline void restore_mfc_queues(struct spu_state *csa, struct spu *spu)
1414 {
1415         struct spu_priv2 __iomem *priv2 = spu->priv2;
1416         int i;
1417
1418         /* Restore, Step 50:
1419          *     If MFC_Cntl[Se]!=0 then restore
1420          *     MFC command queues.
1421          */
1422         if ((csa->priv2.mfc_control_RW & MFC_CNTL_DMA_QUEUES_EMPTY_MASK) == 0) {
1423                 for (i = 0; i < 8; i++) {
1424                         out_be64(&priv2->puq[i].mfc_cq_data0_RW,
1425                                  csa->priv2.puq[i].mfc_cq_data0_RW);
1426                         out_be64(&priv2->puq[i].mfc_cq_data1_RW,
1427                                  csa->priv2.puq[i].mfc_cq_data1_RW);
1428                         out_be64(&priv2->puq[i].mfc_cq_data2_RW,
1429                                  csa->priv2.puq[i].mfc_cq_data2_RW);
1430                         out_be64(&priv2->puq[i].mfc_cq_data3_RW,
1431                                  csa->priv2.puq[i].mfc_cq_data3_RW);
1432                 }
1433                 for (i = 0; i < 16; i++) {
1434                         out_be64(&priv2->spuq[i].mfc_cq_data0_RW,
1435                                  csa->priv2.spuq[i].mfc_cq_data0_RW);
1436                         out_be64(&priv2->spuq[i].mfc_cq_data1_RW,
1437                                  csa->priv2.spuq[i].mfc_cq_data1_RW);
1438                         out_be64(&priv2->spuq[i].mfc_cq_data2_RW,
1439                                  csa->priv2.spuq[i].mfc_cq_data2_RW);
1440                         out_be64(&priv2->spuq[i].mfc_cq_data3_RW,
1441                                  csa->priv2.spuq[i].mfc_cq_data3_RW);
1442                 }
1443         }
1444         eieio();
1445 }
1446
1447 static inline void restore_ppu_querymask(struct spu_state *csa, struct spu *spu)
1448 {
1449         struct spu_problem __iomem *prob = spu->problem;
1450
1451         /* Restore, Step 51:
1452          *     Restore the PPU_QueryMask register from CSA.
1453          */
1454         out_be32(&prob->dma_querymask_RW, csa->prob.dma_querymask_RW);
1455         eieio();
1456 }
1457
1458 static inline void restore_ppu_querytype(struct spu_state *csa, struct spu *spu)
1459 {
1460         struct spu_problem __iomem *prob = spu->problem;
1461
1462         /* Restore, Step 52:
1463          *     Restore the PPU_QueryType register from CSA.
1464          */
1465         out_be32(&prob->dma_querytype_RW, csa->prob.dma_querytype_RW);
1466         eieio();
1467 }
1468
1469 static inline void restore_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
1470 {
1471         struct spu_priv2 __iomem *priv2 = spu->priv2;
1472
1473         /* Restore, Step 53:
1474          *     Restore the MFC_CSR_TSQ register from CSA.
1475          */
1476         out_be64(&priv2->spu_tag_status_query_RW,
1477                  csa->priv2.spu_tag_status_query_RW);
1478         eieio();
1479 }
1480
1481 static inline void restore_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
1482 {
1483         struct spu_priv2 __iomem *priv2 = spu->priv2;
1484
1485         /* Restore, Step 54:
1486          *     Restore the MFC_CSR_CMD1 and MFC_CSR_CMD2
1487          *     registers from CSA.
1488          */
1489         out_be64(&priv2->spu_cmd_buf1_RW, csa->priv2.spu_cmd_buf1_RW);
1490         out_be64(&priv2->spu_cmd_buf2_RW, csa->priv2.spu_cmd_buf2_RW);
1491         eieio();
1492 }
1493
1494 static inline void restore_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
1495 {
1496         struct spu_priv2 __iomem *priv2 = spu->priv2;
1497
1498         /* Restore, Step 55:
1499          *     Restore the MFC_CSR_ATO register from CSA.
1500          */
1501         out_be64(&priv2->spu_atomic_status_RW, csa->priv2.spu_atomic_status_RW);
1502 }
1503
1504 static inline void restore_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
1505 {
1506         /* Restore, Step 56:
1507          *     Restore the MFC_TCLASS_ID register from CSA.
1508          */
1509         spu_mfc_tclass_id_set(spu, csa->priv1.mfc_tclass_id_RW);
1510         eieio();
1511 }
1512
1513 static inline void set_llr_event(struct spu_state *csa, struct spu *spu)
1514 {
1515         u64 ch0_cnt, ch0_data;
1516         u64 ch1_data;
1517
1518         /* Restore, Step 57:
1519          *    Set the Lock Line Reservation Lost Event by:
1520          *      1. OR CSA.SPU_Event_Status with bit 21 (Lr) set to 1.
1521          *      2. If CSA.SPU_Channel_0_Count=0 and
1522          *         CSA.SPU_Wr_Event_Mask[Lr]=1 and
1523          *         CSA.SPU_Event_Status[Lr]=0 then set
1524          *         CSA.SPU_Event_Status_Count=1.
1525          */
1526         ch0_cnt = csa->spu_chnlcnt_RW[0];
1527         ch0_data = csa->spu_chnldata_RW[0];
1528         ch1_data = csa->spu_chnldata_RW[1];
1529         csa->spu_chnldata_RW[0] |= MFC_LLR_LOST_EVENT;
1530         if ((ch0_cnt == 0) && !(ch0_data & MFC_LLR_LOST_EVENT) &&
1531             (ch1_data & MFC_LLR_LOST_EVENT)) {
1532                 csa->spu_chnlcnt_RW[0] = 1;
1533         }
1534 }
1535
1536 static inline void restore_decr_wrapped(struct spu_state *csa, struct spu *spu)
1537 {
1538         /* Restore, Step 58:
1539          *     If the status of the CSA software decrementer
1540          *     "wrapped" flag is set, OR in a '1' to
1541          *     CSA.SPU_Event_Status[Tm].
1542          */
1543         if (!(csa->lscsa->decr_status.slot[0] & SPU_DECR_STATUS_WRAPPED))
1544                 return;
1545
1546         if ((csa->spu_chnlcnt_RW[0] == 0) &&
1547             (csa->spu_chnldata_RW[1] & 0x20) &&
1548             !(csa->spu_chnldata_RW[0] & 0x20))
1549                 csa->spu_chnlcnt_RW[0] = 1;
1550
1551         csa->spu_chnldata_RW[0] |= 0x20;
1552 }
1553
1554 static inline void restore_ch_part1(struct spu_state *csa, struct spu *spu)
1555 {
1556         struct spu_priv2 __iomem *priv2 = spu->priv2;
1557         u64 idx, ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
1558         int i;
1559
1560         /* Restore, Step 59:
1561          *      Restore the following CH: [0,3,4,24,25,27]
1562          */
1563         for (i = 0; i < ARRAY_SIZE(ch_indices); i++) {
1564                 idx = ch_indices[i];
1565                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1566                 eieio();
1567                 out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[idx]);
1568                 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[idx]);
1569                 eieio();
1570         }
1571 }
1572
1573 static inline void restore_ch_part2(struct spu_state *csa, struct spu *spu)
1574 {
1575         struct spu_priv2 __iomem *priv2 = spu->priv2;
1576         u64 ch_indices[3] = { 9UL, 21UL, 23UL };
1577         u64 ch_counts[3] = { 1UL, 16UL, 1UL };
1578         u64 idx;
1579         int i;
1580
1581         /* Restore, Step 60:
1582          *     Restore the following CH: [9,21,23].
1583          */
1584         ch_counts[0] = 1UL;
1585         ch_counts[1] = csa->spu_chnlcnt_RW[21];
1586         ch_counts[2] = 1UL;
1587         for (i = 0; i < 3; i++) {
1588                 idx = ch_indices[i];
1589                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1590                 eieio();
1591                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1592                 eieio();
1593         }
1594 }
1595
1596 static inline void restore_spu_lslr(struct spu_state *csa, struct spu *spu)
1597 {
1598         struct spu_priv2 __iomem *priv2 = spu->priv2;
1599
1600         /* Restore, Step 61:
1601          *     Restore the SPU_LSLR register from CSA.
1602          */
1603         out_be64(&priv2->spu_lslr_RW, csa->priv2.spu_lslr_RW);
1604         eieio();
1605 }
1606
1607 static inline void restore_spu_cfg(struct spu_state *csa, struct spu *spu)
1608 {
1609         struct spu_priv2 __iomem *priv2 = spu->priv2;
1610
1611         /* Restore, Step 62:
1612          *     Restore the SPU_Cfg register from CSA.
1613          */
1614         out_be64(&priv2->spu_cfg_RW, csa->priv2.spu_cfg_RW);
1615         eieio();
1616 }
1617
1618 static inline void restore_pm_trace(struct spu_state *csa, struct spu *spu)
1619 {
1620         /* Restore, Step 63:
1621          *     Restore PM_Trace_Tag_Wait_Mask from CSA.
1622          *     Not performed by this implementation.
1623          */
1624 }
1625
1626 static inline void restore_spu_npc(struct spu_state *csa, struct spu *spu)
1627 {
1628         struct spu_problem __iomem *prob = spu->problem;
1629
1630         /* Restore, Step 64:
1631          *     Restore SPU_NPC from CSA.
1632          */
1633         out_be32(&prob->spu_npc_RW, csa->prob.spu_npc_RW);
1634         eieio();
1635 }
1636
1637 static inline void restore_spu_mb(struct spu_state *csa, struct spu *spu)
1638 {
1639         struct spu_priv2 __iomem *priv2 = spu->priv2;
1640         int i;
1641
1642         /* Restore, Step 65:
1643          *     Restore MFC_RdSPU_MB from CSA.
1644          */
1645         out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
1646         eieio();
1647         out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[29]);
1648         for (i = 0; i < 4; i++) {
1649                 out_be64(&priv2->spu_chnldata_RW, csa->spu_mailbox_data[i]);
1650         }
1651         eieio();
1652 }
1653
1654 static inline void check_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
1655 {
1656         struct spu_problem __iomem *prob = spu->problem;
1657         u32 dummy = 0;
1658
1659         /* Restore, Step 66:
1660          *     If CSA.MB_Stat[P]=0 (mailbox empty) then
1661          *     read from the PPU_MB register.
1662          */
1663         if ((csa->prob.mb_stat_R & 0xFF) == 0) {
1664                 dummy = in_be32(&prob->pu_mb_R);
1665                 eieio();
1666         }
1667 }
1668
1669 static inline void check_ppuint_mb_stat(struct spu_state *csa, struct spu *spu)
1670 {
1671         struct spu_priv2 __iomem *priv2 = spu->priv2;
1672         u64 dummy = 0UL;
1673
1674         /* Restore, Step 66:
1675          *     If CSA.MB_Stat[I]=0 (mailbox empty) then
1676          *     read from the PPUINT_MB register.
1677          */
1678         if ((csa->prob.mb_stat_R & 0xFF0000) == 0) {
1679                 dummy = in_be64(&priv2->puint_mb_R);
1680                 eieio();
1681                 spu_int_stat_clear(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
1682                 eieio();
1683         }
1684 }
1685
1686 static inline void restore_mfc_sr1(struct spu_state *csa, struct spu *spu)
1687 {
1688         /* Restore, Step 69:
1689          *     Restore the MFC_SR1 register from CSA.
1690          */
1691         spu_mfc_sr1_set(spu, csa->priv1.mfc_sr1_RW);
1692         eieio();
1693 }
1694
1695 static inline void restore_other_spu_access(struct spu_state *csa,
1696                                             struct spu *spu)
1697 {
1698         /* Restore, Step 70:
1699          *     Restore other SPU mappings to this SPU. TBD.
1700          */
1701 }
1702
1703 static inline void restore_spu_runcntl(struct spu_state *csa, struct spu *spu)
1704 {
1705         struct spu_problem __iomem *prob = spu->problem;
1706
1707         /* Restore, Step 71:
1708          *     If CSA.SPU_Status[R]=1 then write
1709          *     SPU_RunCntl[R0R1]='01'.
1710          */
1711         if (csa->prob.spu_status_R & SPU_STATUS_RUNNING) {
1712                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1713                 eieio();
1714         }
1715 }
1716
1717 static inline void restore_mfc_cntl(struct spu_state *csa, struct spu *spu)
1718 {
1719         struct spu_priv2 __iomem *priv2 = spu->priv2;
1720
1721         /* Restore, Step 72:
1722          *    Restore the MFC_CNTL register for the CSA.
1723          */
1724         out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW);
1725         eieio();
1726         /*
1727          * FIXME: this is to restart a DMA that we were processing
1728          *        before the save. better remember the fault information
1729          *        in the csa instead.
1730          */
1731         if ((csa->priv2.mfc_control_RW & MFC_CNTL_SUSPEND_DMA_QUEUE_MASK)) {
1732                 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
1733                 eieio();
1734         }
1735 }
1736
1737 static inline void enable_user_access(struct spu_state *csa, struct spu *spu)
1738 {
1739         /* Restore, Step 73:
1740          *     Enable user-space access (if provided) to this
1741          *     SPU by mapping the virtual pages assigned to
1742          *     the SPU memory-mapped I/O (MMIO) for problem
1743          *     state. TBD.
1744          */
1745 }
1746
1747 static inline void reset_switch_active(struct spu_state *csa, struct spu *spu)
1748 {
1749         /* Restore, Step 74:
1750          *     Reset the "context switch active" flag.
1751          *     Not performed by this implementation.
1752          */
1753 }
1754
1755 static inline void reenable_interrupts(struct spu_state *csa, struct spu *spu)
1756 {
1757         /* Restore, Step 75:
1758          *     Re-enable SPU interrupts.
1759          */
1760         spin_lock_irq(&spu->register_lock);
1761         spu_int_mask_set(spu, 0, csa->priv1.int_mask_class0_RW);
1762         spu_int_mask_set(spu, 1, csa->priv1.int_mask_class1_RW);
1763         spu_int_mask_set(spu, 2, csa->priv1.int_mask_class2_RW);
1764         spin_unlock_irq(&spu->register_lock);
1765 }
1766
1767 static int quiece_spu(struct spu_state *prev, struct spu *spu)
1768 {
1769         /*
1770          * Combined steps 2-18 of SPU context save sequence, which
1771          * quiesce the SPU state (disable SPU execution, MFC command
1772          * queues, decrementer, SPU interrupts, etc.).
1773          *
1774          * Returns      0 on success.
1775          *              2 if failed step 2.
1776          *              6 if failed step 6.
1777          */
1778
1779         if (check_spu_isolate(prev, spu)) {     /* Step 2. */
1780                 return 2;
1781         }
1782         disable_interrupts(prev, spu);          /* Step 3. */
1783         set_watchdog_timer(prev, spu);          /* Step 4. */
1784         inhibit_user_access(prev, spu);         /* Step 5. */
1785         if (check_spu_isolate(prev, spu)) {     /* Step 6. */
1786                 return 6;
1787         }
1788         set_switch_pending(prev, spu);          /* Step 7. */
1789         save_mfc_cntl(prev, spu);               /* Step 8. */
1790         save_spu_runcntl(prev, spu);            /* Step 9. */
1791         save_mfc_sr1(prev, spu);                /* Step 10. */
1792         save_spu_status(prev, spu);             /* Step 11. */
1793         save_mfc_decr(prev, spu);               /* Step 12. */
1794         halt_mfc_decr(prev, spu);               /* Step 13. */
1795         save_timebase(prev, spu);               /* Step 14. */
1796         remove_other_spu_access(prev, spu);     /* Step 15. */
1797         do_mfc_mssync(prev, spu);               /* Step 16. */
1798         issue_mfc_tlbie(prev, spu);             /* Step 17. */
1799         handle_pending_interrupts(prev, spu);   /* Step 18. */
1800
1801         return 0;
1802 }
1803
1804 static void save_csa(struct spu_state *prev, struct spu *spu)
1805 {
1806         /*
1807          * Combine steps 19-44 of SPU context save sequence, which
1808          * save regions of the privileged & problem state areas.
1809          */
1810
1811         save_mfc_queues(prev, spu);     /* Step 19. */
1812         save_ppu_querymask(prev, spu);  /* Step 20. */
1813         save_ppu_querytype(prev, spu);  /* Step 21. */
1814         save_ppu_tagstatus(prev, spu);  /* NEW.     */
1815         save_mfc_csr_tsq(prev, spu);    /* Step 22. */
1816         save_mfc_csr_cmd(prev, spu);    /* Step 23. */
1817         save_mfc_csr_ato(prev, spu);    /* Step 24. */
1818         save_mfc_tclass_id(prev, spu);  /* Step 25. */
1819         set_mfc_tclass_id(prev, spu);   /* Step 26. */
1820         save_mfc_cmd(prev, spu);        /* Step 26a - moved from 44. */
1821         purge_mfc_queue(prev, spu);     /* Step 27. */
1822         wait_purge_complete(prev, spu); /* Step 28. */
1823         setup_mfc_sr1(prev, spu);       /* Step 30. */
1824         save_spu_npc(prev, spu);        /* Step 31. */
1825         save_spu_privcntl(prev, spu);   /* Step 32. */
1826         reset_spu_privcntl(prev, spu);  /* Step 33. */
1827         save_spu_lslr(prev, spu);       /* Step 34. */
1828         reset_spu_lslr(prev, spu);      /* Step 35. */
1829         save_spu_cfg(prev, spu);        /* Step 36. */
1830         save_pm_trace(prev, spu);       /* Step 37. */
1831         save_mfc_rag(prev, spu);        /* Step 38. */
1832         save_ppu_mb_stat(prev, spu);    /* Step 39. */
1833         save_ppu_mb(prev, spu);         /* Step 40. */
1834         save_ppuint_mb(prev, spu);      /* Step 41. */
1835         save_ch_part1(prev, spu);       /* Step 42. */
1836         save_spu_mb(prev, spu);         /* Step 43. */
1837         reset_ch(prev, spu);            /* Step 45. */
1838 }
1839
1840 static void save_lscsa(struct spu_state *prev, struct spu *spu)
1841 {
1842         /*
1843          * Perform steps 46-57 of SPU context save sequence,
1844          * which save regions of the local store and register
1845          * file.
1846          */
1847
1848         resume_mfc_queue(prev, spu);    /* Step 46. */
1849         /* Step 47. */
1850         setup_mfc_slbs(prev, spu, spu_save_code, sizeof(spu_save_code));
1851         set_switch_active(prev, spu);   /* Step 48. */
1852         enable_interrupts(prev, spu);   /* Step 49. */
1853         save_ls_16kb(prev, spu);        /* Step 50. */
1854         set_spu_npc(prev, spu);         /* Step 51. */
1855         set_signot1(prev, spu);         /* Step 52. */
1856         set_signot2(prev, spu);         /* Step 53. */
1857         send_save_code(prev, spu);      /* Step 54. */
1858         set_ppu_querymask(prev, spu);   /* Step 55. */
1859         wait_tag_complete(prev, spu);   /* Step 56. */
1860         wait_spu_stopped(prev, spu);    /* Step 57. */
1861 }
1862
1863 static void force_spu_isolate_exit(struct spu *spu)
1864 {
1865         struct spu_problem __iomem *prob = spu->problem;
1866         struct spu_priv2 __iomem *priv2 = spu->priv2;
1867
1868         /* Stop SPE execution and wait for completion. */
1869         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1870         iobarrier_rw();
1871         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
1872
1873         /* Restart SPE master runcntl. */
1874         spu_mfc_sr1_set(spu, MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1875         iobarrier_w();
1876
1877         /* Initiate isolate exit request and wait for completion. */
1878         out_be64(&priv2->spu_privcntl_RW, 4LL);
1879         iobarrier_w();
1880         out_be32(&prob->spu_runcntl_RW, 2);
1881         iobarrier_rw();
1882         POLL_WHILE_FALSE((in_be32(&prob->spu_status_R)
1883                                 & SPU_STATUS_STOPPED_BY_STOP));
1884
1885         /* Reset load request to normal. */
1886         out_be64(&priv2->spu_privcntl_RW, SPU_PRIVCNT_LOAD_REQUEST_NORMAL);
1887         iobarrier_w();
1888 }
1889
1890 /**
1891  * stop_spu_isolate
1892  *      Check SPU run-control state and force isolated
1893  *      exit function as necessary.
1894  */
1895 static void stop_spu_isolate(struct spu *spu)
1896 {
1897         struct spu_problem __iomem *prob = spu->problem;
1898
1899         if (in_be32(&prob->spu_status_R) & SPU_STATUS_ISOLATED_STATE) {
1900                 /* The SPU is in isolated state; the only way
1901                  * to get it out is to perform an isolated
1902                  * exit (clean) operation.
1903                  */
1904                 force_spu_isolate_exit(spu);
1905         }
1906 }
1907
1908 static void harvest(struct spu_state *prev, struct spu *spu)
1909 {
1910         /*
1911          * Perform steps 2-25 of SPU context restore sequence,
1912          * which resets an SPU either after a failed save, or
1913          * when using SPU for first time.
1914          */
1915
1916         disable_interrupts(prev, spu);          /* Step 2.  */
1917         inhibit_user_access(prev, spu);         /* Step 3.  */
1918         terminate_spu_app(prev, spu);           /* Step 4.  */
1919         set_switch_pending(prev, spu);          /* Step 5.  */
1920         stop_spu_isolate(spu);                  /* NEW.     */
1921         remove_other_spu_access(prev, spu);     /* Step 6.  */
1922         suspend_mfc_and_halt_decr(prev, spu);   /* Step 7.  */
1923         wait_suspend_mfc_complete(prev, spu);   /* Step 8.  */
1924         if (!suspend_spe(prev, spu))            /* Step 9.  */
1925                 clear_spu_status(prev, spu);    /* Step 10. */
1926         do_mfc_mssync(prev, spu);               /* Step 11. */
1927         issue_mfc_tlbie(prev, spu);             /* Step 12. */
1928         handle_pending_interrupts(prev, spu);   /* Step 13. */
1929         purge_mfc_queue(prev, spu);             /* Step 14. */
1930         wait_purge_complete(prev, spu);         /* Step 15. */
1931         reset_spu_privcntl(prev, spu);          /* Step 16. */
1932         reset_spu_lslr(prev, spu);              /* Step 17. */
1933         setup_mfc_sr1(prev, spu);               /* Step 18. */
1934         spu_invalidate_slbs(spu);               /* Step 19. */
1935         reset_ch_part1(prev, spu);              /* Step 20. */
1936         reset_ch_part2(prev, spu);              /* Step 21. */
1937         enable_interrupts(prev, spu);           /* Step 22. */
1938         set_switch_active(prev, spu);           /* Step 23. */
1939         set_mfc_tclass_id(prev, spu);           /* Step 24. */
1940         resume_mfc_queue(prev, spu);            /* Step 25. */
1941 }
1942
1943 static void restore_lscsa(struct spu_state *next, struct spu *spu)
1944 {
1945         /*
1946          * Perform steps 26-40 of SPU context restore sequence,
1947          * which restores regions of the local store and register
1948          * file.
1949          */
1950
1951         set_watchdog_timer(next, spu);          /* Step 26. */
1952         setup_spu_status_part1(next, spu);      /* Step 27. */
1953         setup_spu_status_part2(next, spu);      /* Step 28. */
1954         restore_mfc_rag(next, spu);             /* Step 29. */
1955         /* Step 30. */
1956         setup_mfc_slbs(next, spu, spu_restore_code, sizeof(spu_restore_code));
1957         set_spu_npc(next, spu);                 /* Step 31. */
1958         set_signot1(next, spu);                 /* Step 32. */
1959         set_signot2(next, spu);                 /* Step 33. */
1960         setup_decr(next, spu);                  /* Step 34. */
1961         setup_ppu_mb(next, spu);                /* Step 35. */
1962         setup_ppuint_mb(next, spu);             /* Step 36. */
1963         send_restore_code(next, spu);           /* Step 37. */
1964         set_ppu_querymask(next, spu);           /* Step 38. */
1965         wait_tag_complete(next, spu);           /* Step 39. */
1966         wait_spu_stopped(next, spu);            /* Step 40. */
1967 }
1968
1969 static void restore_csa(struct spu_state *next, struct spu *spu)
1970 {
1971         /*
1972          * Combine steps 41-76 of SPU context restore sequence, which
1973          * restore regions of the privileged & problem state areas.
1974          */
1975
1976         restore_spu_privcntl(next, spu);        /* Step 41. */
1977         restore_status_part1(next, spu);        /* Step 42. */
1978         restore_status_part2(next, spu);        /* Step 43. */
1979         restore_ls_16kb(next, spu);             /* Step 44. */
1980         wait_tag_complete(next, spu);           /* Step 45. */
1981         suspend_mfc(next, spu);                 /* Step 46. */
1982         wait_suspend_mfc_complete(next, spu);   /* Step 47. */
1983         issue_mfc_tlbie(next, spu);             /* Step 48. */
1984         clear_interrupts(next, spu);            /* Step 49. */
1985         restore_mfc_queues(next, spu);          /* Step 50. */
1986         restore_ppu_querymask(next, spu);       /* Step 51. */
1987         restore_ppu_querytype(next, spu);       /* Step 52. */
1988         restore_mfc_csr_tsq(next, spu);         /* Step 53. */
1989         restore_mfc_csr_cmd(next, spu);         /* Step 54. */
1990         restore_mfc_csr_ato(next, spu);         /* Step 55. */
1991         restore_mfc_tclass_id(next, spu);       /* Step 56. */
1992         set_llr_event(next, spu);               /* Step 57. */
1993         restore_decr_wrapped(next, spu);        /* Step 58. */
1994         restore_ch_part1(next, spu);            /* Step 59. */
1995         restore_ch_part2(next, spu);            /* Step 60. */
1996         restore_spu_lslr(next, spu);            /* Step 61. */
1997         restore_spu_cfg(next, spu);             /* Step 62. */
1998         restore_pm_trace(next, spu);            /* Step 63. */
1999         restore_spu_npc(next, spu);             /* Step 64. */
2000         restore_spu_mb(next, spu);              /* Step 65. */
2001         check_ppu_mb_stat(next, spu);           /* Step 66. */
2002         check_ppuint_mb_stat(next, spu);        /* Step 67. */
2003         spu_invalidate_slbs(spu);               /* Modified Step 68. */
2004         restore_mfc_sr1(next, spu);             /* Step 69. */
2005         restore_other_spu_access(next, spu);    /* Step 70. */
2006         restore_spu_runcntl(next, spu);         /* Step 71. */
2007         restore_mfc_cntl(next, spu);            /* Step 72. */
2008         enable_user_access(next, spu);          /* Step 73. */
2009         reset_switch_active(next, spu);         /* Step 74. */
2010         reenable_interrupts(next, spu);         /* Step 75. */
2011 }
2012
2013 static int __do_spu_save(struct spu_state *prev, struct spu *spu)
2014 {
2015         int rc;
2016
2017         /*
2018          * SPU context save can be broken into three phases:
2019          *
2020          *     (a) quiesce [steps 2-16].
2021          *     (b) save of CSA, performed by PPE [steps 17-42]
2022          *     (c) save of LSCSA, mostly performed by SPU [steps 43-52].
2023          *
2024          * Returns      0 on success.
2025          *              2,6 if failed to quiece SPU
2026          *              53 if SPU-side of save failed.
2027          */
2028
2029         rc = quiece_spu(prev, spu);             /* Steps 2-16. */
2030         switch (rc) {
2031         default:
2032         case 2:
2033         case 6:
2034                 harvest(prev, spu);
2035                 return rc;
2036                 break;
2037         case 0:
2038                 break;
2039         }
2040         save_csa(prev, spu);                    /* Steps 17-43. */
2041         save_lscsa(prev, spu);                  /* Steps 44-53. */
2042         return check_save_status(prev, spu);    /* Step 54.     */
2043 }
2044
2045 static int __do_spu_restore(struct spu_state *next, struct spu *spu)
2046 {
2047         int rc;
2048
2049         /*
2050          * SPU context restore can be broken into three phases:
2051          *
2052          *    (a) harvest (or reset) SPU [steps 2-24].
2053          *    (b) restore LSCSA [steps 25-40], mostly performed by SPU.
2054          *    (c) restore CSA [steps 41-76], performed by PPE.
2055          *
2056          * The 'harvest' step is not performed here, but rather
2057          * as needed below.
2058          */
2059
2060         restore_lscsa(next, spu);               /* Steps 24-39. */
2061         rc = check_restore_status(next, spu);   /* Step 40.     */
2062         switch (rc) {
2063         default:
2064                 /* Failed. Return now. */
2065                 return rc;
2066                 break;
2067         case 0:
2068                 /* Fall through to next step. */
2069                 break;
2070         }
2071         restore_csa(next, spu);
2072
2073         return 0;
2074 }
2075
2076 /**
2077  * spu_save - SPU context save, with locking.
2078  * @prev: pointer to SPU context save area, to be saved.
2079  * @spu: pointer to SPU iomem structure.
2080  *
2081  * Acquire locks, perform the save operation then return.
2082  */
2083 int spu_save(struct spu_state *prev, struct spu *spu)
2084 {
2085         int rc;
2086
2087         acquire_spu_lock(spu);          /* Step 1.     */
2088         rc = __do_spu_save(prev, spu);  /* Steps 2-53. */
2089         release_spu_lock(spu);
2090         if (rc != 0 && rc != 2 && rc != 6) {
2091                 panic("%s failed on SPU[%d], rc=%d.\n",
2092                       __func__, spu->number, rc);
2093         }
2094         return 0;
2095 }
2096 EXPORT_SYMBOL_GPL(spu_save);
2097
2098 /**
2099  * spu_restore - SPU context restore, with harvest and locking.
2100  * @new: pointer to SPU context save area, to be restored.
2101  * @spu: pointer to SPU iomem structure.
2102  *
2103  * Perform harvest + restore, as we may not be coming
2104  * from a previous successful save operation, and the
2105  * hardware state is unknown.
2106  */
2107 int spu_restore(struct spu_state *new, struct spu *spu)
2108 {
2109         int rc;
2110
2111         acquire_spu_lock(spu);
2112         harvest(NULL, spu);
2113         spu->slb_replace = 0;
2114         rc = __do_spu_restore(new, spu);
2115         release_spu_lock(spu);
2116         if (rc) {
2117                 panic("%s failed on SPU[%d] rc=%d.\n",
2118                        __func__, spu->number, rc);
2119         }
2120         return rc;
2121 }
2122 EXPORT_SYMBOL_GPL(spu_restore);
2123
2124 static void init_prob(struct spu_state *csa)
2125 {
2126         csa->spu_chnlcnt_RW[9] = 1;
2127         csa->spu_chnlcnt_RW[21] = 16;
2128         csa->spu_chnlcnt_RW[23] = 1;
2129         csa->spu_chnlcnt_RW[28] = 1;
2130         csa->spu_chnlcnt_RW[30] = 1;
2131         csa->prob.spu_runcntl_RW = SPU_RUNCNTL_STOP;
2132         csa->prob.mb_stat_R = 0x000400;
2133 }
2134
2135 static void init_priv1(struct spu_state *csa)
2136 {
2137         /* Enable decode, relocate, tlbie response, master runcntl. */
2138         csa->priv1.mfc_sr1_RW = MFC_STATE1_LOCAL_STORAGE_DECODE_MASK |
2139             MFC_STATE1_MASTER_RUN_CONTROL_MASK |
2140             MFC_STATE1_PROBLEM_STATE_MASK |
2141             MFC_STATE1_RELOCATE_MASK | MFC_STATE1_BUS_TLBIE_MASK;
2142
2143         /* Enable OS-specific set of interrupts. */
2144         csa->priv1.int_mask_class0_RW = CLASS0_ENABLE_DMA_ALIGNMENT_INTR |
2145             CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR |
2146             CLASS0_ENABLE_SPU_ERROR_INTR;
2147         csa->priv1.int_mask_class1_RW = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
2148             CLASS1_ENABLE_STORAGE_FAULT_INTR;
2149         csa->priv1.int_mask_class2_RW = CLASS2_ENABLE_SPU_STOP_INTR |
2150             CLASS2_ENABLE_SPU_HALT_INTR |
2151             CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR;
2152 }
2153
2154 static void init_priv2(struct spu_state *csa)
2155 {
2156         csa->priv2.spu_lslr_RW = LS_ADDR_MASK;
2157         csa->priv2.mfc_control_RW = MFC_CNTL_RESUME_DMA_QUEUE |
2158             MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION |
2159             MFC_CNTL_DMA_QUEUES_EMPTY_MASK;
2160 }
2161
2162 /**
2163  * spu_alloc_csa - allocate and initialize an SPU context save area.
2164  *
2165  * Allocate and initialize the contents of an SPU context save area.
2166  * This includes enabling address translation, interrupt masks, etc.,
2167  * as appropriate for the given OS environment.
2168  *
2169  * Note that storage for the 'lscsa' is allocated separately,
2170  * as it is by far the largest of the context save regions,
2171  * and may need to be pinned or otherwise specially aligned.
2172  */
2173 int spu_init_csa(struct spu_state *csa)
2174 {
2175         int rc;
2176
2177         if (!csa)
2178                 return -EINVAL;
2179         memset(csa, 0, sizeof(struct spu_state));
2180
2181         rc = spu_alloc_lscsa(csa);
2182         if (rc)
2183                 return rc;
2184
2185         spin_lock_init(&csa->register_lock);
2186
2187         init_prob(csa);
2188         init_priv1(csa);
2189         init_priv2(csa);
2190
2191         return 0;
2192 }
2193
2194 void spu_fini_csa(struct spu_state *csa)
2195 {
2196         spu_free_lscsa(csa);
2197 }