4 * (C) Copyright IBM Corp. 2005
6 * Author: Mark Nutter <mnutter@us.ibm.com>
8 * Host-side part of SPU context switch sequence outlined in
9 * Synergistic Processor Element, Book IV.
11 * A fully premptive switch of an SPE is very expensive in terms
12 * of time and system resources. SPE Book IV indicates that SPE
13 * allocation should follow a "serially reusable device" model,
14 * in which the SPE is assigned a task until it completes. When
15 * this is not possible, this sequence may be used to premptively
16 * save, and then later (optionally) restore the context of a
17 * program executing on an SPE.
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
35 #include <linux/module.h>
36 #include <linux/errno.h>
37 #include <linux/hardirq.h>
38 #include <linux/sched.h>
39 #include <linux/kernel.h>
41 #include <linux/vmalloc.h>
42 #include <linux/smp.h>
43 #include <linux/stddef.h>
44 #include <linux/unistd.h>
48 #include <asm/spu_priv1.h>
49 #include <asm/spu_csa.h>
50 #include <asm/mmu_context.h>
54 #include "spu_save_dump.h"
55 #include "spu_restore_dump.h"
58 #define POLL_WHILE_TRUE(_c) { \
63 #define RELAX_SPIN_COUNT 1000
64 #define POLL_WHILE_TRUE(_c) { \
67 for (_i=0; _i<RELAX_SPIN_COUNT && (_c); _i++) { \
70 if (unlikely(_c)) yield(); \
76 #define POLL_WHILE_FALSE(_c) POLL_WHILE_TRUE(!(_c))
78 static inline void acquire_spu_lock(struct spu *spu)
82 * Acquire SPU-specific mutual exclusion lock.
87 static inline void release_spu_lock(struct spu *spu)
90 * Release SPU-specific mutual exclusion lock.
95 static inline int check_spu_isolate(struct spu_state *csa, struct spu *spu)
97 struct spu_problem __iomem *prob = spu->problem;
102 * If SPU_Status[E,L,IS] any field is '1', this
103 * SPU is in isolate state and cannot be context
104 * saved at this time.
106 isolate_state = SPU_STATUS_ISOLATED_STATE |
107 SPU_STATUS_ISOLATED_LOAD_STATUS | SPU_STATUS_ISOLATED_EXIT_STATUS;
108 return (in_be32(&prob->spu_status_R) & isolate_state) ? 1 : 0;
111 static inline void disable_interrupts(struct spu_state *csa, struct spu *spu)
115 * Save INT_Mask_class0 in CSA.
116 * Write INT_MASK_class0 with value of 0.
117 * Save INT_Mask_class1 in CSA.
118 * Write INT_MASK_class1 with value of 0.
119 * Save INT_Mask_class2 in CSA.
120 * Write INT_MASK_class2 with value of 0.
121 * Synchronize all three interrupts to be sure
122 * we no longer execute a handler on another CPU.
124 spin_lock_irq(&spu->register_lock);
126 csa->priv1.int_mask_class0_RW = spu_int_mask_get(spu, 0);
127 csa->priv1.int_mask_class1_RW = spu_int_mask_get(spu, 1);
128 csa->priv1.int_mask_class2_RW = spu_int_mask_get(spu, 2);
130 spu_int_mask_set(spu, 0, 0ul);
131 spu_int_mask_set(spu, 1, 0ul);
132 spu_int_mask_set(spu, 2, 0ul);
134 spin_unlock_irq(&spu->register_lock);
137 * This flag needs to be set before calling synchronize_irq so
138 * that the update will be visible to the relevant handlers
141 set_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);
142 synchronize_irq(spu->irqs[0]);
143 synchronize_irq(spu->irqs[1]);
144 synchronize_irq(spu->irqs[2]);
147 static inline void set_watchdog_timer(struct spu_state *csa, struct spu *spu)
151 * Set a software watchdog timer, which specifies the
152 * maximum allowable time for a context save sequence.
154 * For present, this implementation will not set a global
155 * watchdog timer, as virtualization & variable system load
156 * may cause unpredictable execution times.
160 static inline void inhibit_user_access(struct spu_state *csa, struct spu *spu)
164 * Inhibit user-space access (if provided) to this
165 * SPU by unmapping the virtual pages assigned to
166 * the SPU memory-mapped I/O (MMIO) for problem
171 static inline void set_switch_pending(struct spu_state *csa, struct spu *spu)
175 * Set a software context switch pending flag.
176 * Done above in Step 3 - disable_interrupts().
180 static inline void save_mfc_cntl(struct spu_state *csa, struct spu *spu)
182 struct spu_priv2 __iomem *priv2 = spu->priv2;
185 * Suspend DMA and save MFC_CNTL.
187 switch (in_be64(&priv2->mfc_control_RW) &
188 MFC_CNTL_SUSPEND_DMA_STATUS_MASK) {
189 case MFC_CNTL_SUSPEND_IN_PROGRESS:
190 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
191 MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
192 MFC_CNTL_SUSPEND_COMPLETE);
194 case MFC_CNTL_SUSPEND_COMPLETE:
196 csa->priv2.mfc_control_RW =
197 in_be64(&priv2->mfc_control_RW) |
198 MFC_CNTL_SUSPEND_DMA_QUEUE;
200 case MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION:
201 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
202 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
203 MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
204 MFC_CNTL_SUSPEND_COMPLETE);
206 csa->priv2.mfc_control_RW =
207 in_be64(&priv2->mfc_control_RW) &
208 ~MFC_CNTL_SUSPEND_DMA_QUEUE &
209 ~MFC_CNTL_SUSPEND_MASK;
214 static inline void save_spu_runcntl(struct spu_state *csa, struct spu *spu)
216 struct spu_problem __iomem *prob = spu->problem;
219 * Save SPU_Runcntl in the CSA. This value contains
220 * the "Application Desired State".
222 csa->prob.spu_runcntl_RW = in_be32(&prob->spu_runcntl_RW);
225 static inline void save_mfc_sr1(struct spu_state *csa, struct spu *spu)
228 * Save MFC_SR1 in the CSA.
230 csa->priv1.mfc_sr1_RW = spu_mfc_sr1_get(spu);
233 static inline void save_spu_status(struct spu_state *csa, struct spu *spu)
235 struct spu_problem __iomem *prob = spu->problem;
238 * Read SPU_Status[R], and save to CSA.
240 if ((in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) == 0) {
241 csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
245 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
247 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
250 SPU_STATUS_INVALID_INSTR | SPU_STATUS_SINGLE_STEP |
251 SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP;
252 if ((in_be32(&prob->spu_status_R) & stopped) == 0)
253 csa->prob.spu_status_R = SPU_STATUS_RUNNING;
255 csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
259 static inline void save_mfc_stopped_status(struct spu_state *csa,
262 struct spu_priv2 __iomem *priv2 = spu->priv2;
263 const u64 mask = MFC_CNTL_DECREMENTER_RUNNING |
264 MFC_CNTL_DMA_QUEUES_EMPTY;
267 * Read MFC_CNTL[Ds]. Update saved copy of
270 * update: do the same with MFC_CNTL[Q].
272 csa->priv2.mfc_control_RW &= ~mask;
273 csa->priv2.mfc_control_RW |= in_be64(&priv2->mfc_control_RW) & mask;
276 static inline void halt_mfc_decr(struct spu_state *csa, struct spu *spu)
278 struct spu_priv2 __iomem *priv2 = spu->priv2;
281 * Write MFC_CNTL[Dh] set to a '1' to halt
284 out_be64(&priv2->mfc_control_RW,
285 MFC_CNTL_DECREMENTER_HALTED | MFC_CNTL_SUSPEND_MASK);
289 static inline void save_timebase(struct spu_state *csa, struct spu *spu)
292 * Read PPE Timebase High and Timebase low registers
293 * and save in CSA. TBD.
295 csa->suspend_time = get_cycles();
298 static inline void remove_other_spu_access(struct spu_state *csa,
302 * Remove other SPU access to this SPU by unmapping
303 * this SPU's pages from their address space. TBD.
307 static inline void do_mfc_mssync(struct spu_state *csa, struct spu *spu)
309 struct spu_problem __iomem *prob = spu->problem;
313 * Write SPU_MSSync register. Poll SPU_MSSync[P]
316 out_be64(&prob->spc_mssync_RW, 1UL);
317 POLL_WHILE_TRUE(in_be64(&prob->spc_mssync_RW) & MS_SYNC_PENDING);
320 static inline void issue_mfc_tlbie(struct spu_state *csa, struct spu *spu)
325 * Write TLB_Invalidate_Entry[IS,VPN,L,Lp]=0 register.
326 * Then issue a PPE sync instruction.
328 spu_tlb_invalidate(spu);
332 static inline void handle_pending_interrupts(struct spu_state *csa,
336 * Handle any pending interrupts from this SPU
337 * here. This is OS or hypervisor specific. One
338 * option is to re-enable interrupts to handle any
339 * pending interrupts, with the interrupt handlers
340 * recognizing the software Context Switch Pending
341 * flag, to ensure the SPU execution or MFC command
342 * queue is not restarted. TBD.
346 static inline void save_mfc_queues(struct spu_state *csa, struct spu *spu)
348 struct spu_priv2 __iomem *priv2 = spu->priv2;
352 * If MFC_Cntl[Se]=0 then save
353 * MFC command queues.
355 if ((in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DMA_QUEUES_EMPTY) == 0) {
356 for (i = 0; i < 8; i++) {
357 csa->priv2.puq[i].mfc_cq_data0_RW =
358 in_be64(&priv2->puq[i].mfc_cq_data0_RW);
359 csa->priv2.puq[i].mfc_cq_data1_RW =
360 in_be64(&priv2->puq[i].mfc_cq_data1_RW);
361 csa->priv2.puq[i].mfc_cq_data2_RW =
362 in_be64(&priv2->puq[i].mfc_cq_data2_RW);
363 csa->priv2.puq[i].mfc_cq_data3_RW =
364 in_be64(&priv2->puq[i].mfc_cq_data3_RW);
366 for (i = 0; i < 16; i++) {
367 csa->priv2.spuq[i].mfc_cq_data0_RW =
368 in_be64(&priv2->spuq[i].mfc_cq_data0_RW);
369 csa->priv2.spuq[i].mfc_cq_data1_RW =
370 in_be64(&priv2->spuq[i].mfc_cq_data1_RW);
371 csa->priv2.spuq[i].mfc_cq_data2_RW =
372 in_be64(&priv2->spuq[i].mfc_cq_data2_RW);
373 csa->priv2.spuq[i].mfc_cq_data3_RW =
374 in_be64(&priv2->spuq[i].mfc_cq_data3_RW);
379 static inline void save_ppu_querymask(struct spu_state *csa, struct spu *spu)
381 struct spu_problem __iomem *prob = spu->problem;
384 * Save the PPU_QueryMask register
387 csa->prob.dma_querymask_RW = in_be32(&prob->dma_querymask_RW);
390 static inline void save_ppu_querytype(struct spu_state *csa, struct spu *spu)
392 struct spu_problem __iomem *prob = spu->problem;
395 * Save the PPU_QueryType register
398 csa->prob.dma_querytype_RW = in_be32(&prob->dma_querytype_RW);
401 static inline void save_ppu_tagstatus(struct spu_state *csa, struct spu *spu)
403 struct spu_problem __iomem *prob = spu->problem;
405 /* Save the Prxy_TagStatus register in the CSA.
407 * It is unnecessary to restore dma_tagstatus_R, however,
408 * dma_tagstatus_R in the CSA is accessed via backing_ops, so
411 csa->prob.dma_tagstatus_R = in_be32(&prob->dma_tagstatus_R);
414 static inline void save_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
416 struct spu_priv2 __iomem *priv2 = spu->priv2;
419 * Save the MFC_CSR_TSQ register
422 csa->priv2.spu_tag_status_query_RW =
423 in_be64(&priv2->spu_tag_status_query_RW);
426 static inline void save_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
428 struct spu_priv2 __iomem *priv2 = spu->priv2;
431 * Save the MFC_CSR_CMD1 and MFC_CSR_CMD2
432 * registers in the CSA.
434 csa->priv2.spu_cmd_buf1_RW = in_be64(&priv2->spu_cmd_buf1_RW);
435 csa->priv2.spu_cmd_buf2_RW = in_be64(&priv2->spu_cmd_buf2_RW);
438 static inline void save_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
440 struct spu_priv2 __iomem *priv2 = spu->priv2;
443 * Save the MFC_CSR_ATO register in
446 csa->priv2.spu_atomic_status_RW = in_be64(&priv2->spu_atomic_status_RW);
449 static inline void save_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
452 * Save the MFC_TCLASS_ID register in
455 csa->priv1.mfc_tclass_id_RW = spu_mfc_tclass_id_get(spu);
458 static inline void set_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
462 * Write the MFC_TCLASS_ID register with
463 * the value 0x10000000.
465 spu_mfc_tclass_id_set(spu, 0x10000000);
469 static inline void purge_mfc_queue(struct spu_state *csa, struct spu *spu)
471 struct spu_priv2 __iomem *priv2 = spu->priv2;
475 * Write MFC_CNTL[Pc]=1 (purge queue).
477 out_be64(&priv2->mfc_control_RW,
478 MFC_CNTL_PURGE_DMA_REQUEST |
479 MFC_CNTL_SUSPEND_MASK);
483 static inline void wait_purge_complete(struct spu_state *csa, struct spu *spu)
485 struct spu_priv2 __iomem *priv2 = spu->priv2;
488 * Poll MFC_CNTL[Ps] until value '11' is read
491 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
492 MFC_CNTL_PURGE_DMA_STATUS_MASK) ==
493 MFC_CNTL_PURGE_DMA_COMPLETE);
496 static inline void setup_mfc_sr1(struct spu_state *csa, struct spu *spu)
500 * Write MFC_SR1 with MFC_SR1[D=0,S=1] and
501 * MFC_SR1[TL,R,Pr,T] set correctly for the
502 * OS specific environment.
504 * Implementation note: The SPU-side code
505 * for save/restore is privileged, so the
506 * MFC_SR1[Pr] bit is not set.
509 spu_mfc_sr1_set(spu, (MFC_STATE1_MASTER_RUN_CONTROL_MASK |
510 MFC_STATE1_RELOCATE_MASK |
511 MFC_STATE1_BUS_TLBIE_MASK));
514 static inline void save_spu_npc(struct spu_state *csa, struct spu *spu)
516 struct spu_problem __iomem *prob = spu->problem;
519 * Save SPU_NPC in the CSA.
521 csa->prob.spu_npc_RW = in_be32(&prob->spu_npc_RW);
524 static inline void save_spu_privcntl(struct spu_state *csa, struct spu *spu)
526 struct spu_priv2 __iomem *priv2 = spu->priv2;
529 * Save SPU_PrivCntl in the CSA.
531 csa->priv2.spu_privcntl_RW = in_be64(&priv2->spu_privcntl_RW);
534 static inline void reset_spu_privcntl(struct spu_state *csa, struct spu *spu)
536 struct spu_priv2 __iomem *priv2 = spu->priv2;
540 * Write SPU_PrivCntl[S,Le,A] fields reset to 0.
542 out_be64(&priv2->spu_privcntl_RW, 0UL);
546 static inline void save_spu_lslr(struct spu_state *csa, struct spu *spu)
548 struct spu_priv2 __iomem *priv2 = spu->priv2;
551 * Save SPU_LSLR in the CSA.
553 csa->priv2.spu_lslr_RW = in_be64(&priv2->spu_lslr_RW);
556 static inline void reset_spu_lslr(struct spu_state *csa, struct spu *spu)
558 struct spu_priv2 __iomem *priv2 = spu->priv2;
564 out_be64(&priv2->spu_lslr_RW, LS_ADDR_MASK);
568 static inline void save_spu_cfg(struct spu_state *csa, struct spu *spu)
570 struct spu_priv2 __iomem *priv2 = spu->priv2;
573 * Save SPU_Cfg in the CSA.
575 csa->priv2.spu_cfg_RW = in_be64(&priv2->spu_cfg_RW);
578 static inline void save_pm_trace(struct spu_state *csa, struct spu *spu)
581 * Save PM_Trace_Tag_Wait_Mask in the CSA.
582 * Not performed by this implementation.
586 static inline void save_mfc_rag(struct spu_state *csa, struct spu *spu)
589 * Save RA_GROUP_ID register and the
590 * RA_ENABLE reigster in the CSA.
592 csa->priv1.resource_allocation_groupID_RW =
593 spu_resource_allocation_groupID_get(spu);
594 csa->priv1.resource_allocation_enable_RW =
595 spu_resource_allocation_enable_get(spu);
598 static inline void save_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
600 struct spu_problem __iomem *prob = spu->problem;
603 * Save MB_Stat register in the CSA.
605 csa->prob.mb_stat_R = in_be32(&prob->mb_stat_R);
608 static inline void save_ppu_mb(struct spu_state *csa, struct spu *spu)
610 struct spu_problem __iomem *prob = spu->problem;
613 * Save the PPU_MB register in the CSA.
615 csa->prob.pu_mb_R = in_be32(&prob->pu_mb_R);
618 static inline void save_ppuint_mb(struct spu_state *csa, struct spu *spu)
620 struct spu_priv2 __iomem *priv2 = spu->priv2;
623 * Save the PPUINT_MB register in the CSA.
625 csa->priv2.puint_mb_R = in_be64(&priv2->puint_mb_R);
628 static inline void save_ch_part1(struct spu_state *csa, struct spu *spu)
630 struct spu_priv2 __iomem *priv2 = spu->priv2;
631 u64 idx, ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
637 /* Save CH 1, without channel count */
638 out_be64(&priv2->spu_chnlcntptr_RW, 1);
639 csa->spu_chnldata_RW[1] = in_be64(&priv2->spu_chnldata_RW);
641 /* Save the following CH: [0,3,4,24,25,27] */
642 for (i = 0; i < ARRAY_SIZE(ch_indices); i++) {
644 out_be64(&priv2->spu_chnlcntptr_RW, idx);
646 csa->spu_chnldata_RW[idx] = in_be64(&priv2->spu_chnldata_RW);
647 csa->spu_chnlcnt_RW[idx] = in_be64(&priv2->spu_chnlcnt_RW);
648 out_be64(&priv2->spu_chnldata_RW, 0UL);
649 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
654 static inline void save_spu_mb(struct spu_state *csa, struct spu *spu)
656 struct spu_priv2 __iomem *priv2 = spu->priv2;
660 * Save SPU Read Mailbox Channel.
662 out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
664 csa->spu_chnlcnt_RW[29] = in_be64(&priv2->spu_chnlcnt_RW);
665 for (i = 0; i < 4; i++) {
666 csa->spu_mailbox_data[i] = in_be64(&priv2->spu_chnldata_RW);
668 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
672 static inline void save_mfc_cmd(struct spu_state *csa, struct spu *spu)
674 struct spu_priv2 __iomem *priv2 = spu->priv2;
677 * Save MFC_CMD Channel.
679 out_be64(&priv2->spu_chnlcntptr_RW, 21UL);
681 csa->spu_chnlcnt_RW[21] = in_be64(&priv2->spu_chnlcnt_RW);
685 static inline void reset_ch(struct spu_state *csa, struct spu *spu)
687 struct spu_priv2 __iomem *priv2 = spu->priv2;
688 u64 ch_indices[4] = { 21UL, 23UL, 28UL, 30UL };
689 u64 ch_counts[4] = { 16UL, 1UL, 1UL, 1UL };
694 * Reset the following CH: [21, 23, 28, 30]
696 for (i = 0; i < 4; i++) {
698 out_be64(&priv2->spu_chnlcntptr_RW, idx);
700 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
705 static inline void resume_mfc_queue(struct spu_state *csa, struct spu *spu)
707 struct spu_priv2 __iomem *priv2 = spu->priv2;
711 * Write MFC_CNTL[Sc]=0 (resume queue processing).
713 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESUME_DMA_QUEUE);
716 static inline void setup_mfc_slbs(struct spu_state *csa, struct spu *spu,
717 unsigned int *code, int code_size)
721 * If MFC_SR1[R]=1, write 0 to SLB_Invalidate_All
722 * register, then initialize SLB_VSID and SLB_ESID
723 * to provide access to SPU context save code and
726 * This implementation places both the context
727 * switch code and LSCSA in kernel address space.
729 * Further this implementation assumes that the
730 * MFC_SR1[R]=1 (in other words, assume that
731 * translation is desired by OS environment).
733 spu_invalidate_slbs(spu);
734 spu_setup_kernel_slbs(spu, csa->lscsa, code, code_size);
737 static inline void set_switch_active(struct spu_state *csa, struct spu *spu)
741 * Change the software context switch pending flag
742 * to context switch active.
744 * This implementation does not uses a switch active flag.
746 clear_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);
750 static inline void enable_interrupts(struct spu_state *csa, struct spu *spu)
752 unsigned long class1_mask = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
753 CLASS1_ENABLE_STORAGE_FAULT_INTR;
757 * Reset and then enable interrupts, as
760 * This implementation enables only class1
761 * (translation) interrupts.
763 spin_lock_irq(&spu->register_lock);
764 spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
765 spu_int_stat_clear(spu, 1, CLASS1_INTR_MASK);
766 spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
767 spu_int_mask_set(spu, 0, 0ul);
768 spu_int_mask_set(spu, 1, class1_mask);
769 spu_int_mask_set(spu, 2, 0ul);
770 spin_unlock_irq(&spu->register_lock);
773 static inline int send_mfc_dma(struct spu *spu, unsigned long ea,
774 unsigned int ls_offset, unsigned int size,
775 unsigned int tag, unsigned int rclass,
778 struct spu_problem __iomem *prob = spu->problem;
779 union mfc_tag_size_class_cmd command;
780 unsigned int transfer_size;
781 volatile unsigned int status = 0x0;
785 (size > MFC_MAX_DMA_SIZE) ? MFC_MAX_DMA_SIZE : size;
786 command.u.mfc_size = transfer_size;
787 command.u.mfc_tag = tag;
788 command.u.mfc_rclassid = rclass;
789 command.u.mfc_cmd = cmd;
791 out_be32(&prob->mfc_lsa_W, ls_offset);
792 out_be64(&prob->mfc_ea_W, ea);
793 out_be64(&prob->mfc_union_W.all64, command.all64);
795 in_be32(&prob->mfc_union_W.by32.mfc_class_cmd32);
796 if (unlikely(status & 0x2)) {
799 } while (status & 0x3);
800 size -= transfer_size;
802 ls_offset += transfer_size;
807 static inline void save_ls_16kb(struct spu_state *csa, struct spu *spu)
809 unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
810 unsigned int ls_offset = 0x0;
811 unsigned int size = 16384;
812 unsigned int tag = 0;
813 unsigned int rclass = 0;
814 unsigned int cmd = MFC_PUT_CMD;
817 * Issue a DMA command to copy the first 16K bytes
818 * of local storage to the CSA.
820 send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
823 static inline void set_spu_npc(struct spu_state *csa, struct spu *spu)
825 struct spu_problem __iomem *prob = spu->problem;
829 * Write SPU_NPC[IE]=0 and SPU_NPC[LSA] to entry
830 * point address of context save code in local
833 * This implementation uses SPU-side save/restore
834 * programs with entry points at LSA of 0.
836 out_be32(&prob->spu_npc_RW, 0);
840 static inline void set_signot1(struct spu_state *csa, struct spu *spu)
842 struct spu_problem __iomem *prob = spu->problem;
850 * Write SPU_Sig_Notify_1 register with upper 32-bits
851 * of the CSA.LSCSA effective address.
853 addr64.ull = (u64) csa->lscsa;
854 out_be32(&prob->signal_notify1, addr64.ui[0]);
858 static inline void set_signot2(struct spu_state *csa, struct spu *spu)
860 struct spu_problem __iomem *prob = spu->problem;
868 * Write SPU_Sig_Notify_2 register with lower 32-bits
869 * of the CSA.LSCSA effective address.
871 addr64.ull = (u64) csa->lscsa;
872 out_be32(&prob->signal_notify2, addr64.ui[1]);
876 static inline void send_save_code(struct spu_state *csa, struct spu *spu)
878 unsigned long addr = (unsigned long)&spu_save_code[0];
879 unsigned int ls_offset = 0x0;
880 unsigned int size = sizeof(spu_save_code);
881 unsigned int tag = 0;
882 unsigned int rclass = 0;
883 unsigned int cmd = MFC_GETFS_CMD;
886 * Issue a DMA command to copy context save code
887 * to local storage and start SPU.
889 send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
892 static inline void set_ppu_querymask(struct spu_state *csa, struct spu *spu)
894 struct spu_problem __iomem *prob = spu->problem;
898 * Write PPU_QueryMask=1 (enable Tag Group 0)
899 * and issue eieio instruction.
901 out_be32(&prob->dma_querymask_RW, MFC_TAGID_TO_TAGMASK(0));
905 static inline void wait_tag_complete(struct spu_state *csa, struct spu *spu)
907 struct spu_problem __iomem *prob = spu->problem;
908 u32 mask = MFC_TAGID_TO_TAGMASK(0);
915 * Poll PPU_TagStatus[gn] until 01 (Tag group 0 complete)
916 * or write PPU_QueryType[TS]=01 and wait for Tag Group
917 * Complete Interrupt. Write INT_Stat_Class0 or
918 * INT_Stat_Class2 with value of 'handled'.
920 POLL_WHILE_FALSE(in_be32(&prob->dma_tagstatus_R) & mask);
922 local_irq_save(flags);
923 spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
924 spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
925 local_irq_restore(flags);
928 static inline void wait_spu_stopped(struct spu_state *csa, struct spu *spu)
930 struct spu_problem __iomem *prob = spu->problem;
935 * Poll until SPU_Status[R]=0 or wait for SPU Class 0
936 * or SPU Class 2 interrupt. Write INT_Stat_class0
937 * or INT_Stat_class2 with value of handled.
939 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
941 local_irq_save(flags);
942 spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
943 spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
944 local_irq_restore(flags);
947 static inline int check_save_status(struct spu_state *csa, struct spu *spu)
949 struct spu_problem __iomem *prob = spu->problem;
953 * If SPU_Status[P]=1 and SPU_Status[SC] = "success",
954 * context save succeeded, otherwise context save
957 complete = ((SPU_SAVE_COMPLETE << SPU_STOP_STATUS_SHIFT) |
958 SPU_STATUS_STOPPED_BY_STOP);
959 return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0;
962 static inline void terminate_spu_app(struct spu_state *csa, struct spu *spu)
965 * If required, notify the "using application" that
966 * the SPU task has been terminated. TBD.
970 static inline void suspend_mfc_and_halt_decr(struct spu_state *csa,
973 struct spu_priv2 __iomem *priv2 = spu->priv2;
976 * Write MFC_Cntl[Dh,Sc,Sm]='1','1','0' to suspend
977 * the queue and halt the decrementer.
979 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE |
980 MFC_CNTL_DECREMENTER_HALTED);
984 static inline void wait_suspend_mfc_complete(struct spu_state *csa,
987 struct spu_priv2 __iomem *priv2 = spu->priv2;
991 * Poll MFC_CNTL[Ss] until 11 is returned.
993 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
994 MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
995 MFC_CNTL_SUSPEND_COMPLETE);
998 static inline int suspend_spe(struct spu_state *csa, struct spu *spu)
1000 struct spu_problem __iomem *prob = spu->problem;
1003 * If SPU_Status[R]=1, stop SPU execution
1004 * and wait for stop to complete.
1006 * Returns 1 if SPU_Status[R]=1 on entry.
1009 if (in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) {
1010 if (in_be32(&prob->spu_status_R) &
1011 SPU_STATUS_ISOLATED_EXIT_STATUS) {
1012 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1013 SPU_STATUS_RUNNING);
1015 if ((in_be32(&prob->spu_status_R) &
1016 SPU_STATUS_ISOLATED_LOAD_STATUS)
1017 || (in_be32(&prob->spu_status_R) &
1018 SPU_STATUS_ISOLATED_STATE)) {
1019 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1021 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1022 SPU_STATUS_RUNNING);
1023 out_be32(&prob->spu_runcntl_RW, 0x2);
1025 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1026 SPU_STATUS_RUNNING);
1028 if (in_be32(&prob->spu_status_R) &
1029 SPU_STATUS_WAITING_FOR_CHANNEL) {
1030 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1032 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1033 SPU_STATUS_RUNNING);
1040 static inline void clear_spu_status(struct spu_state *csa, struct spu *spu)
1042 struct spu_problem __iomem *prob = spu->problem;
1044 /* Restore, Step 10:
1045 * If SPU_Status[R]=0 and SPU_Status[E,L,IS]=1,
1046 * release SPU from isolate state.
1048 if (!(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING)) {
1049 if (in_be32(&prob->spu_status_R) &
1050 SPU_STATUS_ISOLATED_EXIT_STATUS) {
1051 spu_mfc_sr1_set(spu,
1052 MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1054 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1056 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1057 SPU_STATUS_RUNNING);
1059 if ((in_be32(&prob->spu_status_R) &
1060 SPU_STATUS_ISOLATED_LOAD_STATUS)
1061 || (in_be32(&prob->spu_status_R) &
1062 SPU_STATUS_ISOLATED_STATE)) {
1063 spu_mfc_sr1_set(spu,
1064 MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1066 out_be32(&prob->spu_runcntl_RW, 0x2);
1068 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1069 SPU_STATUS_RUNNING);
1074 static inline void reset_ch_part1(struct spu_state *csa, struct spu *spu)
1076 struct spu_priv2 __iomem *priv2 = spu->priv2;
1077 u64 ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
1081 /* Restore, Step 20:
1085 out_be64(&priv2->spu_chnlcntptr_RW, 1);
1086 out_be64(&priv2->spu_chnldata_RW, 0UL);
1088 /* Reset the following CH: [0,3,4,24,25,27] */
1089 for (i = 0; i < ARRAY_SIZE(ch_indices); i++) {
1090 idx = ch_indices[i];
1091 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1093 out_be64(&priv2->spu_chnldata_RW, 0UL);
1094 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
1099 static inline void reset_ch_part2(struct spu_state *csa, struct spu *spu)
1101 struct spu_priv2 __iomem *priv2 = spu->priv2;
1102 u64 ch_indices[5] = { 21UL, 23UL, 28UL, 29UL, 30UL };
1103 u64 ch_counts[5] = { 16UL, 1UL, 1UL, 0UL, 1UL };
1107 /* Restore, Step 21:
1108 * Reset the following CH: [21, 23, 28, 29, 30]
1110 for (i = 0; i < 5; i++) {
1111 idx = ch_indices[i];
1112 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1114 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1119 static inline void setup_spu_status_part1(struct spu_state *csa,
1122 u32 status_P = SPU_STATUS_STOPPED_BY_STOP;
1123 u32 status_I = SPU_STATUS_INVALID_INSTR;
1124 u32 status_H = SPU_STATUS_STOPPED_BY_HALT;
1125 u32 status_S = SPU_STATUS_SINGLE_STEP;
1126 u32 status_S_I = SPU_STATUS_SINGLE_STEP | SPU_STATUS_INVALID_INSTR;
1127 u32 status_S_P = SPU_STATUS_SINGLE_STEP | SPU_STATUS_STOPPED_BY_STOP;
1128 u32 status_P_H = SPU_STATUS_STOPPED_BY_HALT |SPU_STATUS_STOPPED_BY_STOP;
1129 u32 status_P_I = SPU_STATUS_STOPPED_BY_STOP |SPU_STATUS_INVALID_INSTR;
1132 /* Restore, Step 27:
1133 * If the CSA.SPU_Status[I,S,H,P]=1 then add the correct
1134 * instruction sequence to the end of the SPU based restore
1135 * code (after the "context restored" stop and signal) to
1136 * restore the correct SPU status.
1138 * NOTE: Rather than modifying the SPU executable, we
1139 * instead add a new 'stopped_status' field to the
1140 * LSCSA. The SPU-side restore reads this field and
1141 * takes the appropriate action when exiting.
1145 (csa->prob.spu_status_R >> SPU_STOP_STATUS_SHIFT) & 0xFFFF;
1146 if ((csa->prob.spu_status_R & status_P_I) == status_P_I) {
1148 /* SPU_Status[P,I]=1 - Illegal Instruction followed
1149 * by Stop and Signal instruction, followed by 'br -4'.
1152 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_I;
1153 csa->lscsa->stopped_status.slot[1] = status_code;
1155 } else if ((csa->prob.spu_status_R & status_P_H) == status_P_H) {
1157 /* SPU_Status[P,H]=1 - Halt Conditional, followed
1158 * by Stop and Signal instruction, followed by
1161 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_H;
1162 csa->lscsa->stopped_status.slot[1] = status_code;
1164 } else if ((csa->prob.spu_status_R & status_S_P) == status_S_P) {
1166 /* SPU_Status[S,P]=1 - Stop and Signal instruction
1167 * followed by 'br -4'.
1169 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_P;
1170 csa->lscsa->stopped_status.slot[1] = status_code;
1172 } else if ((csa->prob.spu_status_R & status_S_I) == status_S_I) {
1174 /* SPU_Status[S,I]=1 - Illegal instruction followed
1177 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_I;
1178 csa->lscsa->stopped_status.slot[1] = status_code;
1180 } else if ((csa->prob.spu_status_R & status_P) == status_P) {
1182 /* SPU_Status[P]=1 - Stop and Signal instruction
1183 * followed by 'br -4'.
1185 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P;
1186 csa->lscsa->stopped_status.slot[1] = status_code;
1188 } else if ((csa->prob.spu_status_R & status_H) == status_H) {
1190 /* SPU_Status[H]=1 - Halt Conditional, followed
1193 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_H;
1195 } else if ((csa->prob.spu_status_R & status_S) == status_S) {
1197 /* SPU_Status[S]=1 - Two nop instructions.
1199 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S;
1201 } else if ((csa->prob.spu_status_R & status_I) == status_I) {
1203 /* SPU_Status[I]=1 - Illegal instruction followed
1206 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_I;
1211 static inline void setup_spu_status_part2(struct spu_state *csa,
1216 /* Restore, Step 28:
1217 * If the CSA.SPU_Status[I,S,H,P,R]=0 then
1218 * add a 'br *' instruction to the end of
1219 * the SPU based restore code.
1221 * NOTE: Rather than modifying the SPU executable, we
1222 * instead add a new 'stopped_status' field to the
1223 * LSCSA. The SPU-side restore reads this field and
1224 * takes the appropriate action when exiting.
1226 mask = SPU_STATUS_INVALID_INSTR |
1227 SPU_STATUS_SINGLE_STEP |
1228 SPU_STATUS_STOPPED_BY_HALT |
1229 SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING;
1230 if (!(csa->prob.spu_status_R & mask)) {
1231 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_R;
1235 static inline void restore_mfc_rag(struct spu_state *csa, struct spu *spu)
1237 /* Restore, Step 29:
1238 * Restore RA_GROUP_ID register and the
1239 * RA_ENABLE reigster from the CSA.
1241 spu_resource_allocation_groupID_set(spu,
1242 csa->priv1.resource_allocation_groupID_RW);
1243 spu_resource_allocation_enable_set(spu,
1244 csa->priv1.resource_allocation_enable_RW);
1247 static inline void send_restore_code(struct spu_state *csa, struct spu *spu)
1249 unsigned long addr = (unsigned long)&spu_restore_code[0];
1250 unsigned int ls_offset = 0x0;
1251 unsigned int size = sizeof(spu_restore_code);
1252 unsigned int tag = 0;
1253 unsigned int rclass = 0;
1254 unsigned int cmd = MFC_GETFS_CMD;
1256 /* Restore, Step 37:
1257 * Issue MFC DMA command to copy context
1258 * restore code to local storage.
1260 send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
1263 static inline void setup_decr(struct spu_state *csa, struct spu *spu)
1265 /* Restore, Step 34:
1266 * If CSA.MFC_CNTL[Ds]=1 (decrementer was
1267 * running) then adjust decrementer, set
1268 * decrementer running status in LSCSA,
1269 * and set decrementer "wrapped" status
1272 if (csa->priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) {
1273 cycles_t resume_time = get_cycles();
1274 cycles_t delta_time = resume_time - csa->suspend_time;
1276 csa->lscsa->decr_status.slot[0] = SPU_DECR_STATUS_RUNNING;
1277 if (csa->lscsa->decr.slot[0] < delta_time) {
1278 csa->lscsa->decr_status.slot[0] |=
1279 SPU_DECR_STATUS_WRAPPED;
1282 csa->lscsa->decr.slot[0] -= delta_time;
1284 csa->lscsa->decr_status.slot[0] = 0;
1288 static inline void setup_ppu_mb(struct spu_state *csa, struct spu *spu)
1290 /* Restore, Step 35:
1291 * Copy the CSA.PU_MB data into the LSCSA.
1293 csa->lscsa->ppu_mb.slot[0] = csa->prob.pu_mb_R;
1296 static inline void setup_ppuint_mb(struct spu_state *csa, struct spu *spu)
1298 /* Restore, Step 36:
1299 * Copy the CSA.PUINT_MB data into the LSCSA.
1301 csa->lscsa->ppuint_mb.slot[0] = csa->priv2.puint_mb_R;
1304 static inline int check_restore_status(struct spu_state *csa, struct spu *spu)
1306 struct spu_problem __iomem *prob = spu->problem;
1309 /* Restore, Step 40:
1310 * If SPU_Status[P]=1 and SPU_Status[SC] = "success",
1311 * context restore succeeded, otherwise context restore
1314 complete = ((SPU_RESTORE_COMPLETE << SPU_STOP_STATUS_SHIFT) |
1315 SPU_STATUS_STOPPED_BY_STOP);
1316 return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0;
1319 static inline void restore_spu_privcntl(struct spu_state *csa, struct spu *spu)
1321 struct spu_priv2 __iomem *priv2 = spu->priv2;
1323 /* Restore, Step 41:
1324 * Restore SPU_PrivCntl from the CSA.
1326 out_be64(&priv2->spu_privcntl_RW, csa->priv2.spu_privcntl_RW);
1330 static inline void restore_status_part1(struct spu_state *csa, struct spu *spu)
1332 struct spu_problem __iomem *prob = spu->problem;
1335 /* Restore, Step 42:
1336 * If any CSA.SPU_Status[I,S,H,P]=1, then
1337 * restore the error or single step state.
1339 mask = SPU_STATUS_INVALID_INSTR |
1340 SPU_STATUS_SINGLE_STEP |
1341 SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP;
1342 if (csa->prob.spu_status_R & mask) {
1343 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1345 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1346 SPU_STATUS_RUNNING);
1350 static inline void restore_status_part2(struct spu_state *csa, struct spu *spu)
1352 struct spu_problem __iomem *prob = spu->problem;
1355 /* Restore, Step 43:
1356 * If all CSA.SPU_Status[I,S,H,P,R]=0 then write
1357 * SPU_RunCntl[R0R1]='01', wait for SPU_Status[R]=1,
1358 * then write '00' to SPU_RunCntl[R0R1] and wait
1359 * for SPU_Status[R]=0.
1361 mask = SPU_STATUS_INVALID_INSTR |
1362 SPU_STATUS_SINGLE_STEP |
1363 SPU_STATUS_STOPPED_BY_HALT |
1364 SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING;
1365 if (!(csa->prob.spu_status_R & mask)) {
1366 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1368 POLL_WHILE_FALSE(in_be32(&prob->spu_status_R) &
1369 SPU_STATUS_RUNNING);
1370 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1372 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1373 SPU_STATUS_RUNNING);
1377 static inline void restore_ls_16kb(struct spu_state *csa, struct spu *spu)
1379 unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
1380 unsigned int ls_offset = 0x0;
1381 unsigned int size = 16384;
1382 unsigned int tag = 0;
1383 unsigned int rclass = 0;
1384 unsigned int cmd = MFC_GET_CMD;
1386 /* Restore, Step 44:
1387 * Issue a DMA command to restore the first
1388 * 16kb of local storage from CSA.
1390 send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
1393 static inline void suspend_mfc(struct spu_state *csa, struct spu *spu)
1395 struct spu_priv2 __iomem *priv2 = spu->priv2;
1397 /* Restore, Step 47.
1398 * Write MFC_Cntl[Sc,Sm]='1','0' to suspend
1401 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
1405 static inline void clear_interrupts(struct spu_state *csa, struct spu *spu)
1407 /* Restore, Step 49:
1408 * Write INT_MASK_class0 with value of 0.
1409 * Write INT_MASK_class1 with value of 0.
1410 * Write INT_MASK_class2 with value of 0.
1411 * Write INT_STAT_class0 with value of -1.
1412 * Write INT_STAT_class1 with value of -1.
1413 * Write INT_STAT_class2 with value of -1.
1415 spin_lock_irq(&spu->register_lock);
1416 spu_int_mask_set(spu, 0, 0ul);
1417 spu_int_mask_set(spu, 1, 0ul);
1418 spu_int_mask_set(spu, 2, 0ul);
1419 spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
1420 spu_int_stat_clear(spu, 1, CLASS1_INTR_MASK);
1421 spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
1422 spin_unlock_irq(&spu->register_lock);
1425 static inline void restore_mfc_queues(struct spu_state *csa, struct spu *spu)
1427 struct spu_priv2 __iomem *priv2 = spu->priv2;
1430 /* Restore, Step 50:
1431 * If MFC_Cntl[Se]!=0 then restore
1432 * MFC command queues.
1434 if ((csa->priv2.mfc_control_RW & MFC_CNTL_DMA_QUEUES_EMPTY_MASK) == 0) {
1435 for (i = 0; i < 8; i++) {
1436 out_be64(&priv2->puq[i].mfc_cq_data0_RW,
1437 csa->priv2.puq[i].mfc_cq_data0_RW);
1438 out_be64(&priv2->puq[i].mfc_cq_data1_RW,
1439 csa->priv2.puq[i].mfc_cq_data1_RW);
1440 out_be64(&priv2->puq[i].mfc_cq_data2_RW,
1441 csa->priv2.puq[i].mfc_cq_data2_RW);
1442 out_be64(&priv2->puq[i].mfc_cq_data3_RW,
1443 csa->priv2.puq[i].mfc_cq_data3_RW);
1445 for (i = 0; i < 16; i++) {
1446 out_be64(&priv2->spuq[i].mfc_cq_data0_RW,
1447 csa->priv2.spuq[i].mfc_cq_data0_RW);
1448 out_be64(&priv2->spuq[i].mfc_cq_data1_RW,
1449 csa->priv2.spuq[i].mfc_cq_data1_RW);
1450 out_be64(&priv2->spuq[i].mfc_cq_data2_RW,
1451 csa->priv2.spuq[i].mfc_cq_data2_RW);
1452 out_be64(&priv2->spuq[i].mfc_cq_data3_RW,
1453 csa->priv2.spuq[i].mfc_cq_data3_RW);
1459 static inline void restore_ppu_querymask(struct spu_state *csa, struct spu *spu)
1461 struct spu_problem __iomem *prob = spu->problem;
1463 /* Restore, Step 51:
1464 * Restore the PPU_QueryMask register from CSA.
1466 out_be32(&prob->dma_querymask_RW, csa->prob.dma_querymask_RW);
1470 static inline void restore_ppu_querytype(struct spu_state *csa, struct spu *spu)
1472 struct spu_problem __iomem *prob = spu->problem;
1474 /* Restore, Step 52:
1475 * Restore the PPU_QueryType register from CSA.
1477 out_be32(&prob->dma_querytype_RW, csa->prob.dma_querytype_RW);
1481 static inline void restore_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
1483 struct spu_priv2 __iomem *priv2 = spu->priv2;
1485 /* Restore, Step 53:
1486 * Restore the MFC_CSR_TSQ register from CSA.
1488 out_be64(&priv2->spu_tag_status_query_RW,
1489 csa->priv2.spu_tag_status_query_RW);
1493 static inline void restore_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
1495 struct spu_priv2 __iomem *priv2 = spu->priv2;
1497 /* Restore, Step 54:
1498 * Restore the MFC_CSR_CMD1 and MFC_CSR_CMD2
1499 * registers from CSA.
1501 out_be64(&priv2->spu_cmd_buf1_RW, csa->priv2.spu_cmd_buf1_RW);
1502 out_be64(&priv2->spu_cmd_buf2_RW, csa->priv2.spu_cmd_buf2_RW);
1506 static inline void restore_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
1508 struct spu_priv2 __iomem *priv2 = spu->priv2;
1510 /* Restore, Step 55:
1511 * Restore the MFC_CSR_ATO register from CSA.
1513 out_be64(&priv2->spu_atomic_status_RW, csa->priv2.spu_atomic_status_RW);
1516 static inline void restore_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
1518 /* Restore, Step 56:
1519 * Restore the MFC_TCLASS_ID register from CSA.
1521 spu_mfc_tclass_id_set(spu, csa->priv1.mfc_tclass_id_RW);
1525 static inline void set_llr_event(struct spu_state *csa, struct spu *spu)
1527 u64 ch0_cnt, ch0_data;
1530 /* Restore, Step 57:
1531 * Set the Lock Line Reservation Lost Event by:
1532 * 1. OR CSA.SPU_Event_Status with bit 21 (Lr) set to 1.
1533 * 2. If CSA.SPU_Channel_0_Count=0 and
1534 * CSA.SPU_Wr_Event_Mask[Lr]=1 and
1535 * CSA.SPU_Event_Status[Lr]=0 then set
1536 * CSA.SPU_Event_Status_Count=1.
1538 ch0_cnt = csa->spu_chnlcnt_RW[0];
1539 ch0_data = csa->spu_chnldata_RW[0];
1540 ch1_data = csa->spu_chnldata_RW[1];
1541 csa->spu_chnldata_RW[0] |= MFC_LLR_LOST_EVENT;
1542 if ((ch0_cnt == 0) && !(ch0_data & MFC_LLR_LOST_EVENT) &&
1543 (ch1_data & MFC_LLR_LOST_EVENT)) {
1544 csa->spu_chnlcnt_RW[0] = 1;
1548 static inline void restore_decr_wrapped(struct spu_state *csa, struct spu *spu)
1550 /* Restore, Step 58:
1551 * If the status of the CSA software decrementer
1552 * "wrapped" flag is set, OR in a '1' to
1553 * CSA.SPU_Event_Status[Tm].
1555 if (!(csa->lscsa->decr_status.slot[0] & SPU_DECR_STATUS_WRAPPED))
1558 if ((csa->spu_chnlcnt_RW[0] == 0) &&
1559 (csa->spu_chnldata_RW[1] & 0x20) &&
1560 !(csa->spu_chnldata_RW[0] & 0x20))
1561 csa->spu_chnlcnt_RW[0] = 1;
1563 csa->spu_chnldata_RW[0] |= 0x20;
1566 static inline void restore_ch_part1(struct spu_state *csa, struct spu *spu)
1568 struct spu_priv2 __iomem *priv2 = spu->priv2;
1569 u64 idx, ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
1572 /* Restore, Step 59:
1573 * Restore the following CH: [0,3,4,24,25,27]
1575 for (i = 0; i < ARRAY_SIZE(ch_indices); i++) {
1576 idx = ch_indices[i];
1577 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1579 out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[idx]);
1580 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[idx]);
1585 static inline void restore_ch_part2(struct spu_state *csa, struct spu *spu)
1587 struct spu_priv2 __iomem *priv2 = spu->priv2;
1588 u64 ch_indices[3] = { 9UL, 21UL, 23UL };
1589 u64 ch_counts[3] = { 1UL, 16UL, 1UL };
1593 /* Restore, Step 60:
1594 * Restore the following CH: [9,21,23].
1597 ch_counts[1] = csa->spu_chnlcnt_RW[21];
1599 for (i = 0; i < 3; i++) {
1600 idx = ch_indices[i];
1601 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1603 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1608 static inline void restore_spu_lslr(struct spu_state *csa, struct spu *spu)
1610 struct spu_priv2 __iomem *priv2 = spu->priv2;
1612 /* Restore, Step 61:
1613 * Restore the SPU_LSLR register from CSA.
1615 out_be64(&priv2->spu_lslr_RW, csa->priv2.spu_lslr_RW);
1619 static inline void restore_spu_cfg(struct spu_state *csa, struct spu *spu)
1621 struct spu_priv2 __iomem *priv2 = spu->priv2;
1623 /* Restore, Step 62:
1624 * Restore the SPU_Cfg register from CSA.
1626 out_be64(&priv2->spu_cfg_RW, csa->priv2.spu_cfg_RW);
1630 static inline void restore_pm_trace(struct spu_state *csa, struct spu *spu)
1632 /* Restore, Step 63:
1633 * Restore PM_Trace_Tag_Wait_Mask from CSA.
1634 * Not performed by this implementation.
1638 static inline void restore_spu_npc(struct spu_state *csa, struct spu *spu)
1640 struct spu_problem __iomem *prob = spu->problem;
1642 /* Restore, Step 64:
1643 * Restore SPU_NPC from CSA.
1645 out_be32(&prob->spu_npc_RW, csa->prob.spu_npc_RW);
1649 static inline void restore_spu_mb(struct spu_state *csa, struct spu *spu)
1651 struct spu_priv2 __iomem *priv2 = spu->priv2;
1654 /* Restore, Step 65:
1655 * Restore MFC_RdSPU_MB from CSA.
1657 out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
1659 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[29]);
1660 for (i = 0; i < 4; i++) {
1661 out_be64(&priv2->spu_chnldata_RW, csa->spu_mailbox_data[i]);
1666 static inline void check_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
1668 struct spu_problem __iomem *prob = spu->problem;
1671 /* Restore, Step 66:
1672 * If CSA.MB_Stat[P]=0 (mailbox empty) then
1673 * read from the PPU_MB register.
1675 if ((csa->prob.mb_stat_R & 0xFF) == 0) {
1676 dummy = in_be32(&prob->pu_mb_R);
1681 static inline void check_ppuint_mb_stat(struct spu_state *csa, struct spu *spu)
1683 struct spu_priv2 __iomem *priv2 = spu->priv2;
1686 /* Restore, Step 66:
1687 * If CSA.MB_Stat[I]=0 (mailbox empty) then
1688 * read from the PPUINT_MB register.
1690 if ((csa->prob.mb_stat_R & 0xFF0000) == 0) {
1691 dummy = in_be64(&priv2->puint_mb_R);
1693 spu_int_stat_clear(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
1698 static inline void restore_mfc_sr1(struct spu_state *csa, struct spu *spu)
1700 /* Restore, Step 69:
1701 * Restore the MFC_SR1 register from CSA.
1703 spu_mfc_sr1_set(spu, csa->priv1.mfc_sr1_RW);
1707 static inline void restore_other_spu_access(struct spu_state *csa,
1710 /* Restore, Step 70:
1711 * Restore other SPU mappings to this SPU. TBD.
1715 static inline void restore_spu_runcntl(struct spu_state *csa, struct spu *spu)
1717 struct spu_problem __iomem *prob = spu->problem;
1719 /* Restore, Step 71:
1720 * If CSA.SPU_Status[R]=1 then write
1721 * SPU_RunCntl[R0R1]='01'.
1723 if (csa->prob.spu_status_R & SPU_STATUS_RUNNING) {
1724 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1729 static inline void restore_mfc_cntl(struct spu_state *csa, struct spu *spu)
1731 struct spu_priv2 __iomem *priv2 = spu->priv2;
1733 /* Restore, Step 72:
1734 * Restore the MFC_CNTL register for the CSA.
1736 out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW);
1739 * FIXME: this is to restart a DMA that we were processing
1740 * before the save. better remember the fault information
1741 * in the csa instead.
1743 if ((csa->priv2.mfc_control_RW & MFC_CNTL_SUSPEND_DMA_QUEUE_MASK)) {
1744 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
1749 static inline void enable_user_access(struct spu_state *csa, struct spu *spu)
1751 /* Restore, Step 73:
1752 * Enable user-space access (if provided) to this
1753 * SPU by mapping the virtual pages assigned to
1754 * the SPU memory-mapped I/O (MMIO) for problem
1759 static inline void reset_switch_active(struct spu_state *csa, struct spu *spu)
1761 /* Restore, Step 74:
1762 * Reset the "context switch active" flag.
1763 * Not performed by this implementation.
1767 static inline void reenable_interrupts(struct spu_state *csa, struct spu *spu)
1769 /* Restore, Step 75:
1770 * Re-enable SPU interrupts.
1772 spin_lock_irq(&spu->register_lock);
1773 spu_int_mask_set(spu, 0, csa->priv1.int_mask_class0_RW);
1774 spu_int_mask_set(spu, 1, csa->priv1.int_mask_class1_RW);
1775 spu_int_mask_set(spu, 2, csa->priv1.int_mask_class2_RW);
1776 spin_unlock_irq(&spu->register_lock);
1779 static int quiece_spu(struct spu_state *prev, struct spu *spu)
1782 * Combined steps 2-18 of SPU context save sequence, which
1783 * quiesce the SPU state (disable SPU execution, MFC command
1784 * queues, decrementer, SPU interrupts, etc.).
1786 * Returns 0 on success.
1787 * 2 if failed step 2.
1788 * 6 if failed step 6.
1791 if (check_spu_isolate(prev, spu)) { /* Step 2. */
1794 disable_interrupts(prev, spu); /* Step 3. */
1795 set_watchdog_timer(prev, spu); /* Step 4. */
1796 inhibit_user_access(prev, spu); /* Step 5. */
1797 if (check_spu_isolate(prev, spu)) { /* Step 6. */
1800 set_switch_pending(prev, spu); /* Step 7. */
1801 save_mfc_cntl(prev, spu); /* Step 8. */
1802 save_spu_runcntl(prev, spu); /* Step 9. */
1803 save_mfc_sr1(prev, spu); /* Step 10. */
1804 save_spu_status(prev, spu); /* Step 11. */
1805 save_mfc_stopped_status(prev, spu); /* Step 12. */
1806 halt_mfc_decr(prev, spu); /* Step 13. */
1807 save_timebase(prev, spu); /* Step 14. */
1808 remove_other_spu_access(prev, spu); /* Step 15. */
1809 do_mfc_mssync(prev, spu); /* Step 16. */
1810 issue_mfc_tlbie(prev, spu); /* Step 17. */
1811 handle_pending_interrupts(prev, spu); /* Step 18. */
1816 static void save_csa(struct spu_state *prev, struct spu *spu)
1819 * Combine steps 19-44 of SPU context save sequence, which
1820 * save regions of the privileged & problem state areas.
1823 save_mfc_queues(prev, spu); /* Step 19. */
1824 save_ppu_querymask(prev, spu); /* Step 20. */
1825 save_ppu_querytype(prev, spu); /* Step 21. */
1826 save_ppu_tagstatus(prev, spu); /* NEW. */
1827 save_mfc_csr_tsq(prev, spu); /* Step 22. */
1828 save_mfc_csr_cmd(prev, spu); /* Step 23. */
1829 save_mfc_csr_ato(prev, spu); /* Step 24. */
1830 save_mfc_tclass_id(prev, spu); /* Step 25. */
1831 set_mfc_tclass_id(prev, spu); /* Step 26. */
1832 save_mfc_cmd(prev, spu); /* Step 26a - moved from 44. */
1833 purge_mfc_queue(prev, spu); /* Step 27. */
1834 wait_purge_complete(prev, spu); /* Step 28. */
1835 setup_mfc_sr1(prev, spu); /* Step 30. */
1836 save_spu_npc(prev, spu); /* Step 31. */
1837 save_spu_privcntl(prev, spu); /* Step 32. */
1838 reset_spu_privcntl(prev, spu); /* Step 33. */
1839 save_spu_lslr(prev, spu); /* Step 34. */
1840 reset_spu_lslr(prev, spu); /* Step 35. */
1841 save_spu_cfg(prev, spu); /* Step 36. */
1842 save_pm_trace(prev, spu); /* Step 37. */
1843 save_mfc_rag(prev, spu); /* Step 38. */
1844 save_ppu_mb_stat(prev, spu); /* Step 39. */
1845 save_ppu_mb(prev, spu); /* Step 40. */
1846 save_ppuint_mb(prev, spu); /* Step 41. */
1847 save_ch_part1(prev, spu); /* Step 42. */
1848 save_spu_mb(prev, spu); /* Step 43. */
1849 reset_ch(prev, spu); /* Step 45. */
1852 static void save_lscsa(struct spu_state *prev, struct spu *spu)
1855 * Perform steps 46-57 of SPU context save sequence,
1856 * which save regions of the local store and register
1860 resume_mfc_queue(prev, spu); /* Step 46. */
1862 setup_mfc_slbs(prev, spu, spu_save_code, sizeof(spu_save_code));
1863 set_switch_active(prev, spu); /* Step 48. */
1864 enable_interrupts(prev, spu); /* Step 49. */
1865 save_ls_16kb(prev, spu); /* Step 50. */
1866 set_spu_npc(prev, spu); /* Step 51. */
1867 set_signot1(prev, spu); /* Step 52. */
1868 set_signot2(prev, spu); /* Step 53. */
1869 send_save_code(prev, spu); /* Step 54. */
1870 set_ppu_querymask(prev, spu); /* Step 55. */
1871 wait_tag_complete(prev, spu); /* Step 56. */
1872 wait_spu_stopped(prev, spu); /* Step 57. */
1875 static void force_spu_isolate_exit(struct spu *spu)
1877 struct spu_problem __iomem *prob = spu->problem;
1878 struct spu_priv2 __iomem *priv2 = spu->priv2;
1880 /* Stop SPE execution and wait for completion. */
1881 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1883 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
1885 /* Restart SPE master runcntl. */
1886 spu_mfc_sr1_set(spu, MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1889 /* Initiate isolate exit request and wait for completion. */
1890 out_be64(&priv2->spu_privcntl_RW, 4LL);
1892 out_be32(&prob->spu_runcntl_RW, 2);
1894 POLL_WHILE_FALSE((in_be32(&prob->spu_status_R)
1895 & SPU_STATUS_STOPPED_BY_STOP));
1897 /* Reset load request to normal. */
1898 out_be64(&priv2->spu_privcntl_RW, SPU_PRIVCNT_LOAD_REQUEST_NORMAL);
1904 * Check SPU run-control state and force isolated
1905 * exit function as necessary.
1907 static void stop_spu_isolate(struct spu *spu)
1909 struct spu_problem __iomem *prob = spu->problem;
1911 if (in_be32(&prob->spu_status_R) & SPU_STATUS_ISOLATED_STATE) {
1912 /* The SPU is in isolated state; the only way
1913 * to get it out is to perform an isolated
1914 * exit (clean) operation.
1916 force_spu_isolate_exit(spu);
1920 static void harvest(struct spu_state *prev, struct spu *spu)
1923 * Perform steps 2-25 of SPU context restore sequence,
1924 * which resets an SPU either after a failed save, or
1925 * when using SPU for first time.
1928 disable_interrupts(prev, spu); /* Step 2. */
1929 inhibit_user_access(prev, spu); /* Step 3. */
1930 terminate_spu_app(prev, spu); /* Step 4. */
1931 set_switch_pending(prev, spu); /* Step 5. */
1932 stop_spu_isolate(spu); /* NEW. */
1933 remove_other_spu_access(prev, spu); /* Step 6. */
1934 suspend_mfc_and_halt_decr(prev, spu); /* Step 7. */
1935 wait_suspend_mfc_complete(prev, spu); /* Step 8. */
1936 if (!suspend_spe(prev, spu)) /* Step 9. */
1937 clear_spu_status(prev, spu); /* Step 10. */
1938 do_mfc_mssync(prev, spu); /* Step 11. */
1939 issue_mfc_tlbie(prev, spu); /* Step 12. */
1940 handle_pending_interrupts(prev, spu); /* Step 13. */
1941 purge_mfc_queue(prev, spu); /* Step 14. */
1942 wait_purge_complete(prev, spu); /* Step 15. */
1943 reset_spu_privcntl(prev, spu); /* Step 16. */
1944 reset_spu_lslr(prev, spu); /* Step 17. */
1945 setup_mfc_sr1(prev, spu); /* Step 18. */
1946 spu_invalidate_slbs(spu); /* Step 19. */
1947 reset_ch_part1(prev, spu); /* Step 20. */
1948 reset_ch_part2(prev, spu); /* Step 21. */
1949 enable_interrupts(prev, spu); /* Step 22. */
1950 set_switch_active(prev, spu); /* Step 23. */
1951 set_mfc_tclass_id(prev, spu); /* Step 24. */
1952 resume_mfc_queue(prev, spu); /* Step 25. */
1955 static void restore_lscsa(struct spu_state *next, struct spu *spu)
1958 * Perform steps 26-40 of SPU context restore sequence,
1959 * which restores regions of the local store and register
1963 set_watchdog_timer(next, spu); /* Step 26. */
1964 setup_spu_status_part1(next, spu); /* Step 27. */
1965 setup_spu_status_part2(next, spu); /* Step 28. */
1966 restore_mfc_rag(next, spu); /* Step 29. */
1968 setup_mfc_slbs(next, spu, spu_restore_code, sizeof(spu_restore_code));
1969 set_spu_npc(next, spu); /* Step 31. */
1970 set_signot1(next, spu); /* Step 32. */
1971 set_signot2(next, spu); /* Step 33. */
1972 setup_decr(next, spu); /* Step 34. */
1973 setup_ppu_mb(next, spu); /* Step 35. */
1974 setup_ppuint_mb(next, spu); /* Step 36. */
1975 send_restore_code(next, spu); /* Step 37. */
1976 set_ppu_querymask(next, spu); /* Step 38. */
1977 wait_tag_complete(next, spu); /* Step 39. */
1978 wait_spu_stopped(next, spu); /* Step 40. */
1981 static void restore_csa(struct spu_state *next, struct spu *spu)
1984 * Combine steps 41-76 of SPU context restore sequence, which
1985 * restore regions of the privileged & problem state areas.
1988 restore_spu_privcntl(next, spu); /* Step 41. */
1989 restore_status_part1(next, spu); /* Step 42. */
1990 restore_status_part2(next, spu); /* Step 43. */
1991 restore_ls_16kb(next, spu); /* Step 44. */
1992 wait_tag_complete(next, spu); /* Step 45. */
1993 suspend_mfc(next, spu); /* Step 46. */
1994 wait_suspend_mfc_complete(next, spu); /* Step 47. */
1995 issue_mfc_tlbie(next, spu); /* Step 48. */
1996 clear_interrupts(next, spu); /* Step 49. */
1997 restore_mfc_queues(next, spu); /* Step 50. */
1998 restore_ppu_querymask(next, spu); /* Step 51. */
1999 restore_ppu_querytype(next, spu); /* Step 52. */
2000 restore_mfc_csr_tsq(next, spu); /* Step 53. */
2001 restore_mfc_csr_cmd(next, spu); /* Step 54. */
2002 restore_mfc_csr_ato(next, spu); /* Step 55. */
2003 restore_mfc_tclass_id(next, spu); /* Step 56. */
2004 set_llr_event(next, spu); /* Step 57. */
2005 restore_decr_wrapped(next, spu); /* Step 58. */
2006 restore_ch_part1(next, spu); /* Step 59. */
2007 restore_ch_part2(next, spu); /* Step 60. */
2008 restore_spu_lslr(next, spu); /* Step 61. */
2009 restore_spu_cfg(next, spu); /* Step 62. */
2010 restore_pm_trace(next, spu); /* Step 63. */
2011 restore_spu_npc(next, spu); /* Step 64. */
2012 restore_spu_mb(next, spu); /* Step 65. */
2013 check_ppu_mb_stat(next, spu); /* Step 66. */
2014 check_ppuint_mb_stat(next, spu); /* Step 67. */
2015 spu_invalidate_slbs(spu); /* Modified Step 68. */
2016 restore_mfc_sr1(next, spu); /* Step 69. */
2017 restore_other_spu_access(next, spu); /* Step 70. */
2018 restore_spu_runcntl(next, spu); /* Step 71. */
2019 restore_mfc_cntl(next, spu); /* Step 72. */
2020 enable_user_access(next, spu); /* Step 73. */
2021 reset_switch_active(next, spu); /* Step 74. */
2022 reenable_interrupts(next, spu); /* Step 75. */
2025 static int __do_spu_save(struct spu_state *prev, struct spu *spu)
2030 * SPU context save can be broken into three phases:
2032 * (a) quiesce [steps 2-16].
2033 * (b) save of CSA, performed by PPE [steps 17-42]
2034 * (c) save of LSCSA, mostly performed by SPU [steps 43-52].
2036 * Returns 0 on success.
2037 * 2,6 if failed to quiece SPU
2038 * 53 if SPU-side of save failed.
2041 rc = quiece_spu(prev, spu); /* Steps 2-16. */
2052 save_csa(prev, spu); /* Steps 17-43. */
2053 save_lscsa(prev, spu); /* Steps 44-53. */
2054 return check_save_status(prev, spu); /* Step 54. */
2057 static int __do_spu_restore(struct spu_state *next, struct spu *spu)
2062 * SPU context restore can be broken into three phases:
2064 * (a) harvest (or reset) SPU [steps 2-24].
2065 * (b) restore LSCSA [steps 25-40], mostly performed by SPU.
2066 * (c) restore CSA [steps 41-76], performed by PPE.
2068 * The 'harvest' step is not performed here, but rather
2072 restore_lscsa(next, spu); /* Steps 24-39. */
2073 rc = check_restore_status(next, spu); /* Step 40. */
2076 /* Failed. Return now. */
2080 /* Fall through to next step. */
2083 restore_csa(next, spu);
2089 * spu_save - SPU context save, with locking.
2090 * @prev: pointer to SPU context save area, to be saved.
2091 * @spu: pointer to SPU iomem structure.
2093 * Acquire locks, perform the save operation then return.
2095 int spu_save(struct spu_state *prev, struct spu *spu)
2099 acquire_spu_lock(spu); /* Step 1. */
2100 rc = __do_spu_save(prev, spu); /* Steps 2-53. */
2101 release_spu_lock(spu);
2102 if (rc != 0 && rc != 2 && rc != 6) {
2103 panic("%s failed on SPU[%d], rc=%d.\n",
2104 __func__, spu->number, rc);
2108 EXPORT_SYMBOL_GPL(spu_save);
2111 * spu_restore - SPU context restore, with harvest and locking.
2112 * @new: pointer to SPU context save area, to be restored.
2113 * @spu: pointer to SPU iomem structure.
2115 * Perform harvest + restore, as we may not be coming
2116 * from a previous successful save operation, and the
2117 * hardware state is unknown.
2119 int spu_restore(struct spu_state *new, struct spu *spu)
2123 acquire_spu_lock(spu);
2125 spu->slb_replace = 0;
2126 rc = __do_spu_restore(new, spu);
2127 release_spu_lock(spu);
2129 panic("%s failed on SPU[%d] rc=%d.\n",
2130 __func__, spu->number, rc);
2134 EXPORT_SYMBOL_GPL(spu_restore);
2136 static void init_prob(struct spu_state *csa)
2138 csa->spu_chnlcnt_RW[9] = 1;
2139 csa->spu_chnlcnt_RW[21] = 16;
2140 csa->spu_chnlcnt_RW[23] = 1;
2141 csa->spu_chnlcnt_RW[28] = 1;
2142 csa->spu_chnlcnt_RW[30] = 1;
2143 csa->prob.spu_runcntl_RW = SPU_RUNCNTL_STOP;
2144 csa->prob.mb_stat_R = 0x000400;
2147 static void init_priv1(struct spu_state *csa)
2149 /* Enable decode, relocate, tlbie response, master runcntl. */
2150 csa->priv1.mfc_sr1_RW = MFC_STATE1_LOCAL_STORAGE_DECODE_MASK |
2151 MFC_STATE1_MASTER_RUN_CONTROL_MASK |
2152 MFC_STATE1_PROBLEM_STATE_MASK |
2153 MFC_STATE1_RELOCATE_MASK | MFC_STATE1_BUS_TLBIE_MASK;
2155 /* Enable OS-specific set of interrupts. */
2156 csa->priv1.int_mask_class0_RW = CLASS0_ENABLE_DMA_ALIGNMENT_INTR |
2157 CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR |
2158 CLASS0_ENABLE_SPU_ERROR_INTR;
2159 csa->priv1.int_mask_class1_RW = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
2160 CLASS1_ENABLE_STORAGE_FAULT_INTR;
2161 csa->priv1.int_mask_class2_RW = CLASS2_ENABLE_SPU_STOP_INTR |
2162 CLASS2_ENABLE_SPU_HALT_INTR |
2163 CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR;
2166 static void init_priv2(struct spu_state *csa)
2168 csa->priv2.spu_lslr_RW = LS_ADDR_MASK;
2169 csa->priv2.mfc_control_RW = MFC_CNTL_RESUME_DMA_QUEUE |
2170 MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION |
2171 MFC_CNTL_DMA_QUEUES_EMPTY_MASK;
2175 * spu_alloc_csa - allocate and initialize an SPU context save area.
2177 * Allocate and initialize the contents of an SPU context save area.
2178 * This includes enabling address translation, interrupt masks, etc.,
2179 * as appropriate for the given OS environment.
2181 * Note that storage for the 'lscsa' is allocated separately,
2182 * as it is by far the largest of the context save regions,
2183 * and may need to be pinned or otherwise specially aligned.
2185 int spu_init_csa(struct spu_state *csa)
2191 memset(csa, 0, sizeof(struct spu_state));
2193 rc = spu_alloc_lscsa(csa);
2197 spin_lock_init(&csa->register_lock);
2206 void spu_fini_csa(struct spu_state *csa)
2208 spu_free_lscsa(csa);