2 * Copyright (C) 2002 Benjamin Herrenschmidt (benh@kernel.crashing.org)
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
9 * Todo: - add support for the OF persistent properties
11 #include <linux/export.h>
12 #include <linux/kernel.h>
13 #include <linux/stddef.h>
14 #include <linux/string.h>
15 #include <linux/nvram.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/errno.h>
19 #include <linux/adb.h>
20 #include <linux/pmu.h>
21 #include <linux/bootmem.h>
22 #include <linux/completion.h>
23 #include <linux/spinlock.h>
24 #include <asm/sections.h>
26 #include <asm/system.h>
28 #include <asm/machdep.h>
29 #include <asm/nvram.h>
36 #define DBG(x...) printk(x)
41 #define NVRAM_SIZE 0x2000 /* 8kB of non-volatile RAM */
43 #define CORE99_SIGNATURE 0x5a
44 #define CORE99_ADLER_START 0x14
46 /* On Core99, nvram is either a sharp, a micron or an AMD flash */
47 #define SM_FLASH_STATUS_DONE 0x80
48 #define SM_FLASH_STATUS_ERR 0x38
50 #define SM_FLASH_CMD_ERASE_CONFIRM 0xd0
51 #define SM_FLASH_CMD_ERASE_SETUP 0x20
52 #define SM_FLASH_CMD_RESET 0xff
53 #define SM_FLASH_CMD_WRITE_SETUP 0x40
54 #define SM_FLASH_CMD_CLEAR_STATUS 0x50
55 #define SM_FLASH_CMD_READ_STATUS 0x70
57 /* CHRP NVRAM header */
66 struct core99_header {
67 struct chrp_header hdr;
74 * Read and write the non-volatile RAM on PowerMacs and CHRP machines.
76 static int nvram_naddrs;
77 static volatile unsigned char __iomem *nvram_data;
78 static int is_core_99;
79 static int core99_bank = 0;
80 static int nvram_partitions[3];
81 // XXX Turn that into a sem
82 static DEFINE_RAW_SPINLOCK(nv_lock);
84 static int (*core99_write_bank)(int bank, u8* datas);
85 static int (*core99_erase_bank)(int bank);
87 static char *nvram_image;
90 static unsigned char core99_nvram_read_byte(int addr)
92 if (nvram_image == NULL)
94 return nvram_image[addr];
97 static void core99_nvram_write_byte(int addr, unsigned char val)
99 if (nvram_image == NULL)
101 nvram_image[addr] = val;
104 static ssize_t core99_nvram_read(char *buf, size_t count, loff_t *index)
108 if (nvram_image == NULL)
110 if (*index > NVRAM_SIZE)
114 if (i + count > NVRAM_SIZE)
115 count = NVRAM_SIZE - i;
117 memcpy(buf, &nvram_image[i], count);
122 static ssize_t core99_nvram_write(char *buf, size_t count, loff_t *index)
126 if (nvram_image == NULL)
128 if (*index > NVRAM_SIZE)
132 if (i + count > NVRAM_SIZE)
133 count = NVRAM_SIZE - i;
135 memcpy(&nvram_image[i], buf, count);
140 static ssize_t core99_nvram_size(void)
142 if (nvram_image == NULL)
148 static volatile unsigned char __iomem *nvram_addr;
149 static int nvram_mult;
151 static unsigned char direct_nvram_read_byte(int addr)
153 return in_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult]);
156 static void direct_nvram_write_byte(int addr, unsigned char val)
158 out_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult], val);
162 static unsigned char indirect_nvram_read_byte(int addr)
167 raw_spin_lock_irqsave(&nv_lock, flags);
168 out_8(nvram_addr, addr >> 5);
169 val = in_8(&nvram_data[(addr & 0x1f) << 4]);
170 raw_spin_unlock_irqrestore(&nv_lock, flags);
175 static void indirect_nvram_write_byte(int addr, unsigned char val)
179 raw_spin_lock_irqsave(&nv_lock, flags);
180 out_8(nvram_addr, addr >> 5);
181 out_8(&nvram_data[(addr & 0x1f) << 4], val);
182 raw_spin_unlock_irqrestore(&nv_lock, flags);
186 #ifdef CONFIG_ADB_PMU
188 static void pmu_nvram_complete(struct adb_request *req)
191 complete((struct completion *)req->arg);
194 static unsigned char pmu_nvram_read_byte(int addr)
196 struct adb_request req;
197 DECLARE_COMPLETION_ONSTACK(req_complete);
199 req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
200 if (pmu_request(&req, pmu_nvram_complete, 3, PMU_READ_NVRAM,
201 (addr >> 8) & 0xff, addr & 0xff))
203 if (system_state == SYSTEM_RUNNING)
204 wait_for_completion(&req_complete);
205 while (!req.complete)
210 static void pmu_nvram_write_byte(int addr, unsigned char val)
212 struct adb_request req;
213 DECLARE_COMPLETION_ONSTACK(req_complete);
215 req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
216 if (pmu_request(&req, pmu_nvram_complete, 4, PMU_WRITE_NVRAM,
217 (addr >> 8) & 0xff, addr & 0xff, val))
219 if (system_state == SYSTEM_RUNNING)
220 wait_for_completion(&req_complete);
221 while (!req.complete)
225 #endif /* CONFIG_ADB_PMU */
226 #endif /* CONFIG_PPC32 */
228 static u8 chrp_checksum(struct chrp_header* hdr)
231 u16 sum = hdr->signature;
232 for (ptr = (u8 *)&hdr->len; ptr < hdr->data; ptr++)
235 sum = (sum & 0xFF) + (sum>>8);
239 static u32 core99_calc_adler(u8 *buffer)
244 buffer += CORE99_ADLER_START;
247 for (cnt=0; cnt<(NVRAM_SIZE-CORE99_ADLER_START); cnt++) {
248 if ((cnt % 5000) == 0) {
258 return (high << 16) | low;
261 static u32 core99_check(u8* datas)
263 struct core99_header* hdr99 = (struct core99_header*)datas;
265 if (hdr99->hdr.signature != CORE99_SIGNATURE) {
266 DBG("Invalid signature\n");
269 if (hdr99->hdr.cksum != chrp_checksum(&hdr99->hdr)) {
270 DBG("Invalid checksum\n");
273 if (hdr99->adler != core99_calc_adler(datas)) {
274 DBG("Invalid adler\n");
277 return hdr99->generation;
280 static int sm_erase_bank(int bank)
283 unsigned long timeout;
285 u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
287 DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank);
289 out_8(base, SM_FLASH_CMD_ERASE_SETUP);
290 out_8(base, SM_FLASH_CMD_ERASE_CONFIRM);
293 if (++timeout > 1000000) {
294 printk(KERN_ERR "nvram: Sharp/Micron flash erase timeout !\n");
297 out_8(base, SM_FLASH_CMD_READ_STATUS);
299 } while (!(stat & SM_FLASH_STATUS_DONE));
301 out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
302 out_8(base, SM_FLASH_CMD_RESET);
304 if (memchr_inv(base, 0xff, NVRAM_SIZE)) {
305 printk(KERN_ERR "nvram: Sharp/Micron flash erase failed !\n");
311 static int sm_write_bank(int bank, u8* datas)
314 unsigned long timeout;
316 u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
318 DBG("nvram: Sharp/Micron Writing bank %d...\n", bank);
320 for (i=0; i<NVRAM_SIZE; i++) {
321 out_8(base+i, SM_FLASH_CMD_WRITE_SETUP);
323 out_8(base+i, datas[i]);
326 if (++timeout > 1000000) {
327 printk(KERN_ERR "nvram: Sharp/Micron flash write timeout !\n");
330 out_8(base, SM_FLASH_CMD_READ_STATUS);
332 } while (!(stat & SM_FLASH_STATUS_DONE));
333 if (!(stat & SM_FLASH_STATUS_DONE))
336 out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
337 out_8(base, SM_FLASH_CMD_RESET);
338 if (memcmp(base, datas, NVRAM_SIZE)) {
339 printk(KERN_ERR "nvram: Sharp/Micron flash write failed !\n");
345 static int amd_erase_bank(int bank)
348 unsigned long timeout;
350 u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
352 DBG("nvram: AMD Erasing bank %d...\n", bank);
355 out_8(base+0x555, 0xaa);
358 out_8(base+0x2aa, 0x55);
362 out_8(base+0x555, 0x80);
364 out_8(base+0x555, 0xaa);
366 out_8(base+0x2aa, 0x55);
373 if (++timeout > 1000000) {
374 printk(KERN_ERR "nvram: AMD flash erase timeout !\n");
377 stat = in_8(base) ^ in_8(base);
384 if (memchr_inv(base, 0xff, NVRAM_SIZE)) {
385 printk(KERN_ERR "nvram: AMD flash erase failed !\n");
391 static int amd_write_bank(int bank, u8* datas)
394 unsigned long timeout;
396 u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
398 DBG("nvram: AMD Writing bank %d...\n", bank);
400 for (i=0; i<NVRAM_SIZE; i++) {
402 out_8(base+0x555, 0xaa);
405 out_8(base+0x2aa, 0x55);
408 /* Write single word */
409 out_8(base+0x555, 0xa0);
411 out_8(base+i, datas[i]);
415 if (++timeout > 1000000) {
416 printk(KERN_ERR "nvram: AMD flash write timeout !\n");
419 stat = in_8(base) ^ in_8(base);
429 if (memcmp(base, datas, NVRAM_SIZE)) {
430 printk(KERN_ERR "nvram: AMD flash write failed !\n");
436 static void __init lookup_partitions(void)
440 struct chrp_header* hdr;
443 nvram_partitions[pmac_nvram_OF] = -1;
444 nvram_partitions[pmac_nvram_XPRAM] = -1;
445 nvram_partitions[pmac_nvram_NR] = -1;
446 hdr = (struct chrp_header *)buffer;
452 buffer[i] = ppc_md.nvram_read_val(offset+i);
453 if (!strcmp(hdr->name, "common"))
454 nvram_partitions[pmac_nvram_OF] = offset + 0x10;
455 if (!strcmp(hdr->name, "APL,MacOS75")) {
456 nvram_partitions[pmac_nvram_XPRAM] = offset + 0x10;
457 nvram_partitions[pmac_nvram_NR] = offset + 0x110;
459 offset += (hdr->len * 0x10);
460 } while(offset < NVRAM_SIZE);
462 nvram_partitions[pmac_nvram_OF] = 0x1800;
463 nvram_partitions[pmac_nvram_XPRAM] = 0x1300;
464 nvram_partitions[pmac_nvram_NR] = 0x1400;
466 DBG("nvram: OF partition at 0x%x\n", nvram_partitions[pmac_nvram_OF]);
467 DBG("nvram: XP partition at 0x%x\n", nvram_partitions[pmac_nvram_XPRAM]);
468 DBG("nvram: NR partition at 0x%x\n", nvram_partitions[pmac_nvram_NR]);
471 static void core99_nvram_sync(void)
473 struct core99_header* hdr99;
476 if (!is_core_99 || !nvram_data || !nvram_image)
479 raw_spin_lock_irqsave(&nv_lock, flags);
480 if (!memcmp(nvram_image, (u8*)nvram_data + core99_bank*NVRAM_SIZE,
484 DBG("Updating nvram...\n");
486 hdr99 = (struct core99_header*)nvram_image;
488 hdr99->hdr.signature = CORE99_SIGNATURE;
489 hdr99->hdr.cksum = chrp_checksum(&hdr99->hdr);
490 hdr99->adler = core99_calc_adler(nvram_image);
491 core99_bank = core99_bank ? 0 : 1;
492 if (core99_erase_bank)
493 if (core99_erase_bank(core99_bank)) {
494 printk("nvram: Error erasing bank %d\n", core99_bank);
497 if (core99_write_bank)
498 if (core99_write_bank(core99_bank, nvram_image))
499 printk("nvram: Error writing bank %d\n", core99_bank);
501 raw_spin_unlock_irqrestore(&nv_lock, flags);
508 static int __init core99_nvram_setup(struct device_node *dp, unsigned long addr)
511 u32 gen_bank0, gen_bank1;
513 if (nvram_naddrs < 1) {
514 printk(KERN_ERR "nvram: no address\n");
517 nvram_image = alloc_bootmem(NVRAM_SIZE);
518 if (nvram_image == NULL) {
519 printk(KERN_ERR "nvram: can't allocate ram image\n");
522 nvram_data = ioremap(addr, NVRAM_SIZE*2);
523 nvram_naddrs = 1; /* Make sure we get the correct case */
525 DBG("nvram: Checking bank 0...\n");
527 gen_bank0 = core99_check((u8 *)nvram_data);
528 gen_bank1 = core99_check((u8 *)nvram_data + NVRAM_SIZE);
529 core99_bank = (gen_bank0 < gen_bank1) ? 1 : 0;
531 DBG("nvram: gen0=%d, gen1=%d\n", gen_bank0, gen_bank1);
532 DBG("nvram: Active bank is: %d\n", core99_bank);
534 for (i=0; i<NVRAM_SIZE; i++)
535 nvram_image[i] = nvram_data[i + core99_bank*NVRAM_SIZE];
537 ppc_md.nvram_read_val = core99_nvram_read_byte;
538 ppc_md.nvram_write_val = core99_nvram_write_byte;
539 ppc_md.nvram_read = core99_nvram_read;
540 ppc_md.nvram_write = core99_nvram_write;
541 ppc_md.nvram_size = core99_nvram_size;
542 ppc_md.nvram_sync = core99_nvram_sync;
543 ppc_md.machine_shutdown = core99_nvram_sync;
545 * Maybe we could be smarter here though making an exclusive list
546 * of known flash chips is a bit nasty as older OF didn't provide us
547 * with a useful "compatible" entry. A solution would be to really
548 * identify the chip using flash id commands and base ourselves on
549 * a list of known chips IDs
551 if (of_device_is_compatible(dp, "amd-0137")) {
552 core99_erase_bank = amd_erase_bank;
553 core99_write_bank = amd_write_bank;
555 core99_erase_bank = sm_erase_bank;
556 core99_write_bank = sm_write_bank;
561 int __init pmac_nvram_init(void)
563 struct device_node *dp;
564 struct resource r1, r2;
565 unsigned int s1 = 0, s2 = 0;
570 dp = of_find_node_by_name(NULL, "nvram");
572 printk(KERN_ERR "Can't find NVRAM device\n");
576 /* Try to obtain an address */
577 if (of_address_to_resource(dp, 0, &r1) == 0) {
579 s1 = resource_size(&r1);
580 if (of_address_to_resource(dp, 1, &r2) == 0) {
582 s2 = resource_size(&r2);
586 is_core_99 = of_device_is_compatible(dp, "nvram,flash");
588 err = core99_nvram_setup(dp, r1.start);
593 if (machine_is(chrp) && nvram_naddrs == 1) {
594 nvram_data = ioremap(r1.start, s1);
596 ppc_md.nvram_read_val = direct_nvram_read_byte;
597 ppc_md.nvram_write_val = direct_nvram_write_byte;
598 } else if (nvram_naddrs == 1) {
599 nvram_data = ioremap(r1.start, s1);
600 nvram_mult = (s1 + NVRAM_SIZE - 1) / NVRAM_SIZE;
601 ppc_md.nvram_read_val = direct_nvram_read_byte;
602 ppc_md.nvram_write_val = direct_nvram_write_byte;
603 } else if (nvram_naddrs == 2) {
604 nvram_addr = ioremap(r1.start, s1);
605 nvram_data = ioremap(r2.start, s2);
606 ppc_md.nvram_read_val = indirect_nvram_read_byte;
607 ppc_md.nvram_write_val = indirect_nvram_write_byte;
608 } else if (nvram_naddrs == 0 && sys_ctrler == SYS_CTRLER_PMU) {
609 #ifdef CONFIG_ADB_PMU
611 ppc_md.nvram_read_val = pmu_nvram_read_byte;
612 ppc_md.nvram_write_val = pmu_nvram_write_byte;
613 #endif /* CONFIG_ADB_PMU */
615 printk(KERN_ERR "Incompatible type of NVRAM\n");
618 #endif /* CONFIG_PPC32 */
626 int pmac_get_partition(int partition)
628 return nvram_partitions[partition];
631 u8 pmac_xpram_read(int xpaddr)
633 int offset = pmac_get_partition(pmac_nvram_XPRAM);
635 if (offset < 0 || xpaddr < 0 || xpaddr > 0x100)
638 return ppc_md.nvram_read_val(xpaddr + offset);
641 void pmac_xpram_write(int xpaddr, u8 data)
643 int offset = pmac_get_partition(pmac_nvram_XPRAM);
645 if (offset < 0 || xpaddr < 0 || xpaddr > 0x100)
648 ppc_md.nvram_write_val(xpaddr + offset, data);
651 EXPORT_SYMBOL(pmac_get_partition);
652 EXPORT_SYMBOL(pmac_xpram_read);
653 EXPORT_SYMBOL(pmac_xpram_write);