2 * Support for the interrupt controllers found on Power Macintosh,
3 * currently Apple's "Grand Central" interrupt controller in all
4 * it's incarnations. OpenPIC support used on newer machines is
7 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
8 * Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
18 #include <linux/stddef.h>
19 #include <linux/init.h>
20 #include <linux/sched.h>
21 #include <linux/signal.h>
22 #include <linux/pci.h>
23 #include <linux/interrupt.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/adb.h>
26 #include <linux/pmu.h>
28 #include <asm/sections.h>
32 #include <asm/pci-bridge.h>
34 #include <asm/pmac_feature.h>
48 /* Workaround flags for 32bit powermac machines */
49 unsigned int of_irq_workarounds;
50 struct device_node *of_irq_dflt_pic;
52 /* Default addresses */
53 static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4];
55 #define GC_LEVEL_MASK 0x3ff00000
56 #define OHARE_LEVEL_MASK 0x1ff00000
57 #define HEATHROW_LEVEL_MASK 0x1ff00000
60 static int max_real_irqs;
61 static u32 level_mask[4];
63 static DEFINE_RAW_SPINLOCK(pmac_pic_lock);
65 #define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
66 static unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
67 static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
68 static int pmac_irq_cascade = -1;
69 static struct irq_host *pmac_pic_host;
71 static void __pmac_retrigger(unsigned int irq_nr)
73 if (irq_nr >= max_real_irqs && pmac_irq_cascade > 0) {
74 __set_bit(irq_nr, ppc_lost_interrupts);
75 irq_nr = pmac_irq_cascade;
78 if (!__test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
79 atomic_inc(&ppc_n_lost_interrupts);
84 static void pmac_mask_and_ack_irq(struct irq_data *d)
86 unsigned int src = irqd_to_hwirq(d);
87 unsigned long bit = 1UL << (src & 0x1f);
91 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
92 __clear_bit(src, ppc_cached_irq_mask);
93 if (__test_and_clear_bit(src, ppc_lost_interrupts))
94 atomic_dec(&ppc_n_lost_interrupts);
95 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
96 out_le32(&pmac_irq_hw[i]->ack, bit);
98 /* make sure ack gets to controller before we enable
101 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
102 != (ppc_cached_irq_mask[i] & bit));
103 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
106 static void pmac_ack_irq(struct irq_data *d)
108 unsigned int src = irqd_to_hwirq(d);
109 unsigned long bit = 1UL << (src & 0x1f);
113 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
114 if (__test_and_clear_bit(src, ppc_lost_interrupts))
115 atomic_dec(&ppc_n_lost_interrupts);
116 out_le32(&pmac_irq_hw[i]->ack, bit);
117 (void)in_le32(&pmac_irq_hw[i]->ack);
118 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
121 static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
123 unsigned long bit = 1UL << (irq_nr & 0x1f);
126 if ((unsigned)irq_nr >= max_irqs)
129 /* enable unmasked interrupts */
130 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
133 /* make sure mask gets to controller before we
136 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
137 != (ppc_cached_irq_mask[i] & bit));
140 * Unfortunately, setting the bit in the enable register
141 * when the device interrupt is already on *doesn't* set
142 * the bit in the flag register or request another interrupt.
144 if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
145 __pmac_retrigger(irq_nr);
148 /* When an irq gets requested for the first client, if it's an
149 * edge interrupt, we clear any previous one on the controller
151 static unsigned int pmac_startup_irq(struct irq_data *d)
154 unsigned int src = irqd_to_hwirq(d);
155 unsigned long bit = 1UL << (src & 0x1f);
158 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
159 if (!irqd_is_level_type(d))
160 out_le32(&pmac_irq_hw[i]->ack, bit);
161 __set_bit(src, ppc_cached_irq_mask);
162 __pmac_set_irq_mask(src, 0);
163 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
168 static void pmac_mask_irq(struct irq_data *d)
171 unsigned int src = irqd_to_hwirq(d);
173 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
174 __clear_bit(src, ppc_cached_irq_mask);
175 __pmac_set_irq_mask(src, 1);
176 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
179 static void pmac_unmask_irq(struct irq_data *d)
182 unsigned int src = irqd_to_hwirq(d);
184 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
185 __set_bit(src, ppc_cached_irq_mask);
186 __pmac_set_irq_mask(src, 0);
187 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
190 static int pmac_retrigger(struct irq_data *d)
194 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
195 __pmac_retrigger(irqd_to_hwirq(d));
196 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
200 static struct irq_chip pmac_pic = {
202 .irq_startup = pmac_startup_irq,
203 .irq_mask = pmac_mask_irq,
204 .irq_ack = pmac_ack_irq,
205 .irq_mask_ack = pmac_mask_and_ack_irq,
206 .irq_unmask = pmac_unmask_irq,
207 .irq_retrigger = pmac_retrigger,
210 static irqreturn_t gatwick_action(int cpl, void *dev_id)
216 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
217 for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
219 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
220 /* We must read level interrupts from the level register */
221 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
222 bits &= ppc_cached_irq_mask[i];
225 irq += __ilog2(bits);
226 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
227 generic_handle_irq(irq);
228 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
231 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
235 static unsigned int pmac_pic_get_irq(void)
238 unsigned long bits = 0;
241 #ifdef CONFIG_PPC_PMAC32_PSURGE
242 /* IPI's are a hack on the powersurge -- Cort */
243 if (smp_processor_id() != 0) {
244 return psurge_secondary_virq;
246 #endif /* CONFIG_PPC_PMAC32_PSURGE */
247 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
248 for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
250 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
251 /* We must read level interrupts from the level register */
252 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
253 bits &= ppc_cached_irq_mask[i];
256 irq += __ilog2(bits);
259 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
260 if (unlikely(irq < 0))
262 return irq_linear_revmap(pmac_pic_host, irq);
266 static struct irqaction xmon_action = {
273 static struct irqaction gatwick_cascade_action = {
274 .handler = gatwick_action,
278 static int pmac_pic_host_match(struct irq_host *h, struct device_node *node)
280 /* We match all, we don't always have a node anyway */
284 static int pmac_pic_host_map(struct irq_host *h, unsigned int virq,
292 /* Mark level interrupts, set delayed disable for edge ones and set
295 level = !!(level_mask[hw >> 5] & (1UL << (hw & 0x1f)));
297 irq_set_status_flags(virq, IRQ_LEVEL);
298 irq_set_chip_and_handler(virq, &pmac_pic,
299 level ? handle_level_irq : handle_edge_irq);
303 static int pmac_pic_host_xlate(struct irq_host *h, struct device_node *ct,
304 const u32 *intspec, unsigned int intsize,
305 irq_hw_number_t *out_hwirq,
306 unsigned int *out_flags)
309 *out_flags = IRQ_TYPE_NONE;
310 *out_hwirq = *intspec;
314 static struct irq_host_ops pmac_pic_host_ops = {
315 .match = pmac_pic_host_match,
316 .map = pmac_pic_host_map,
317 .xlate = pmac_pic_host_xlate,
320 static void __init pmac_pic_probe_oldstyle(void)
323 struct device_node *master = NULL;
324 struct device_node *slave = NULL;
328 /* Set our get_irq function */
329 ppc_md.get_irq = pmac_pic_get_irq;
332 * Find the interrupt controller type & node
335 if ((master = of_find_node_by_name(NULL, "gc")) != NULL) {
336 max_irqs = max_real_irqs = 32;
337 level_mask[0] = GC_LEVEL_MASK;
338 } else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) {
339 max_irqs = max_real_irqs = 32;
340 level_mask[0] = OHARE_LEVEL_MASK;
342 /* We might have a second cascaded ohare */
343 slave = of_find_node_by_name(NULL, "pci106b,7");
346 level_mask[1] = OHARE_LEVEL_MASK;
348 } else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) {
349 max_irqs = max_real_irqs = 64;
350 level_mask[0] = HEATHROW_LEVEL_MASK;
353 /* We might have a second cascaded heathrow */
354 slave = of_find_node_by_name(master, "mac-io");
356 /* Check ordering of master & slave */
357 if (of_device_is_compatible(master, "gatwick")) {
358 struct device_node *tmp;
359 BUG_ON(slave == NULL);
365 /* We found a slave */
368 level_mask[2] = HEATHROW_LEVEL_MASK;
372 BUG_ON(master == NULL);
375 * Allocate an irq host
377 pmac_pic_host = irq_alloc_host(master, IRQ_HOST_MAP_LINEAR, max_irqs,
380 BUG_ON(pmac_pic_host == NULL);
381 irq_set_default_host(pmac_pic_host);
383 /* Get addresses of first controller if we have a node for it */
384 BUG_ON(of_address_to_resource(master, 0, &r));
386 /* Map interrupts of primary controller */
387 addr = (u8 __iomem *) ioremap(r.start, 0x40);
389 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
391 if (max_real_irqs > 32)
392 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
396 printk(KERN_INFO "irq: Found primary Apple PIC %s for %d irqs\n",
397 master->full_name, max_real_irqs);
399 /* Map interrupts of cascaded controller */
400 if (slave && !of_address_to_resource(slave, 0, &r)) {
401 addr = (u8 __iomem *)ioremap(r.start, 0x40);
402 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
406 (volatile struct pmac_irq_hw __iomem *)
408 pmac_irq_cascade = irq_of_parse_and_map(slave, 0);
410 printk(KERN_INFO "irq: Found slave Apple PIC %s for %d irqs"
411 " cascade: %d\n", slave->full_name,
412 max_irqs - max_real_irqs, pmac_irq_cascade);
416 /* Disable all interrupts in all controllers */
417 for (i = 0; i * 32 < max_irqs; ++i)
418 out_le32(&pmac_irq_hw[i]->enable, 0);
420 /* Hookup cascade irq */
421 if (slave && pmac_irq_cascade != NO_IRQ)
422 setup_irq(pmac_irq_cascade, &gatwick_cascade_action);
424 printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs);
426 setup_irq(irq_create_mapping(NULL, 20), &xmon_action);
430 int of_irq_map_oldworld(struct device_node *device, int index,
431 struct of_irq *out_irq)
433 const u32 *ints = NULL;
437 * Old machines just have a list of interrupt numbers
438 * and no interrupt-controller nodes. We also have dodgy
439 * cases where the APPL,interrupts property is completely
440 * missing behind pci-pci bridges and we have to get it
441 * from the parent (the bridge itself, as apple just wired
442 * everything together on these)
445 ints = of_get_property(device, "AAPL,interrupts", &intlen);
448 device = device->parent;
449 if (device && strcmp(device->type, "pci") != 0)
454 intlen /= sizeof(u32);
459 out_irq->controller = NULL;
460 out_irq->specifier[0] = ints[index];
465 #endif /* CONFIG_PPC32 */
467 static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic)
469 #if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
470 struct device_node* pswitch;
473 pswitch = of_find_node_by_name(NULL, "programmer-switch");
475 nmi_irq = irq_of_parse_and_map(pswitch, 0);
476 if (nmi_irq != NO_IRQ) {
477 mpic_irq_set_priority(nmi_irq, 9);
478 setup_irq(nmi_irq, &xmon_action);
480 of_node_put(pswitch);
482 #endif /* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */
485 static struct mpic * __init pmac_setup_one_mpic(struct device_node *np,
488 const char *name = master ? " MPIC 1 " : " MPIC 2 ";
490 unsigned int flags = master ? 0 : MPIC_SECONDARY;
492 pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0);
494 flags |= MPIC_WANTS_RESET;
495 if (of_get_property(np, "big-endian", NULL))
496 flags |= MPIC_BIG_ENDIAN;
498 /* Primary Big Endian means HT interrupts. This is quite dodgy
499 * but works until I find a better way
501 if (master && (flags & MPIC_BIG_ENDIAN))
502 flags |= MPIC_U3_HT_IRQS;
504 mpic = mpic_alloc(np, 0, flags, 0, 0, name);
513 static int __init pmac_pic_probe_mpic(void)
515 struct mpic *mpic1, *mpic2;
516 struct device_node *np, *master = NULL, *slave = NULL;
518 /* We can have up to 2 MPICs cascaded */
519 for (np = NULL; (np = of_find_node_by_type(np, "open-pic"))
521 if (master == NULL &&
522 of_get_property(np, "interrupts", NULL) == NULL)
523 master = of_node_get(np);
524 else if (slave == NULL)
525 slave = of_node_get(np);
530 /* Check for bogus setups */
531 if (master == NULL && slave != NULL) {
536 /* Not found, default to good old pmac pic */
540 /* Set master handler */
541 ppc_md.get_irq = mpic_get_irq;
544 mpic1 = pmac_setup_one_mpic(master, 1);
545 BUG_ON(mpic1 == NULL);
547 /* Install NMI if any */
548 pmac_pic_setup_mpic_nmi(mpic1);
552 /* Set up a cascaded controller, if present */
554 mpic2 = pmac_setup_one_mpic(slave, 0);
556 printk(KERN_ERR "Failed to setup slave MPIC\n");
564 void __init pmac_pic_init(void)
566 /* We configure the OF parsing based on our oldworld vs. newworld
567 * platform type and wether we were booted by BootX.
571 of_irq_workarounds |= OF_IMAP_OLDWORLD_MAC;
572 if (of_get_property(of_chosen, "linux,bootx", NULL) != NULL)
573 of_irq_workarounds |= OF_IMAP_NO_PHANDLE;
575 /* If we don't have phandles on a newworld, then try to locate a
576 * default interrupt controller (happens when booting with BootX).
577 * We do a first match here, hopefully, that only ever happens on
578 * machines with one controller.
580 if (pmac_newworld && (of_irq_workarounds & OF_IMAP_NO_PHANDLE)) {
581 struct device_node *np;
583 for_each_node_with_property(np, "interrupt-controller") {
584 /* Skip /chosen/interrupt-controller */
585 if (strcmp(np->name, "chosen") == 0)
587 /* It seems like at least one person wants
588 * to use BootX on a machine with an AppleKiwi
589 * controller which happens to pretend to be an
590 * interrupt controller too. */
591 if (strcmp(np->name, "AppleKiwi") == 0)
593 /* I think we found one ! */
594 of_irq_dflt_pic = np;
598 #endif /* CONFIG_PPC32 */
600 /* We first try to detect Apple's new Core99 chipset, since mac-io
601 * is quite different on those machines and contains an IBM MPIC2.
603 if (pmac_pic_probe_mpic() == 0)
607 pmac_pic_probe_oldstyle();
611 #if defined(CONFIG_PM) && defined(CONFIG_PPC32)
613 * These procedures are used in implementing sleep on the powerbooks.
614 * sleep_save_intrs() saves the states of all interrupt enables
615 * and disables all interrupts except for the nominated one.
616 * sleep_restore_intrs() restores the states of all interrupt enables.
618 unsigned long sleep_save_mask[2];
620 /* This used to be passed by the PMU driver but that link got
621 * broken with the new driver model. We use this tweak for now...
622 * We really want to do things differently though...
624 static int pmacpic_find_viaint(void)
628 #ifdef CONFIG_ADB_PMU
629 struct device_node *np;
631 if (pmu_get_model() != PMU_OHARE_BASED)
633 np = of_find_node_by_name(NULL, "via-pmu");
636 viaint = irq_of_parse_and_map(np, 0);
639 #endif /* CONFIG_ADB_PMU */
643 static int pmacpic_suspend(void)
645 int viaint = pmacpic_find_viaint();
647 sleep_save_mask[0] = ppc_cached_irq_mask[0];
648 sleep_save_mask[1] = ppc_cached_irq_mask[1];
649 ppc_cached_irq_mask[0] = 0;
650 ppc_cached_irq_mask[1] = 0;
652 set_bit(viaint, ppc_cached_irq_mask);
653 out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
654 if (max_real_irqs > 32)
655 out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
656 (void)in_le32(&pmac_irq_hw[0]->event);
657 /* make sure mask gets to controller before we return to caller */
659 (void)in_le32(&pmac_irq_hw[0]->enable);
664 static void pmacpic_resume(void)
668 out_le32(&pmac_irq_hw[0]->enable, 0);
669 if (max_real_irqs > 32)
670 out_le32(&pmac_irq_hw[1]->enable, 0);
672 for (i = 0; i < max_real_irqs; ++i)
673 if (test_bit(i, sleep_save_mask))
674 pmac_unmask_irq(irq_get_irq_data(i));
677 static struct syscore_ops pmacpic_syscore_ops = {
678 .suspend = pmacpic_suspend,
679 .resume = pmacpic_resume,
682 static int __init init_pmacpic_syscore(void)
685 register_syscore_ops(&pmacpic_syscore_ops);
689 machine_subsys_initcall(powermac, init_pmacpic_syscore);
691 #endif /* CONFIG_PM && CONFIG_PPC32 */