arch/powerpc/platforms/powernv/eeh-ioda.c

   1 /*
   2  * The file intends to implement the functions needed by EEH, which is
   3  * built on IODA compliant chip. Actually, lots of functions related
   4  * to EEH would be built based on the OPAL APIs.
   5  *
   6  * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/bootmem.h>
  15 #include <linux/debugfs.h>
  16 #include <linux/delay.h>
  17 #include <linux/io.h>
  18 #include <linux/irq.h>
  19 #include <linux/kernel.h>
  20 #include <linux/msi.h>
  21 #include <linux/notifier.h>
  22 #include <linux/pci.h>
  23 #include <linux/string.h>
  24
  25 #include <asm/eeh.h>
  26 #include <asm/eeh_event.h>
  27 #include <asm/io.h>
  28 #include <asm/iommu.h>
  29 #include <asm/msi_bitmap.h>
  30 #include <asm/opal.h>
  31 #include <asm/pci-bridge.h>
  32 #include <asm/ppc-pci.h>
  33 #include <asm/tce.h>
  34
  35 #include "powernv.h"
  36 #include "pci.h"
  37
  38 static int ioda_eeh_nb_init = 0;
  39
  40 static int ioda_eeh_event(struct notifier_block *nb,
  41                           unsigned long events, void *change)
  42 {
  43         uint64_t changed_evts = (uint64_t)change;
  44
  45         /*
  46          * We simply send special EEH event if EEH has
  47          * been enabled, or clear pending events in
  48          * case that we enable EEH soon
  49          */
  50         if (!(changed_evts & OPAL_EVENT_PCI_ERROR) ||
  51             !(events & OPAL_EVENT_PCI_ERROR))
  52                 return 0;
  53
  54         if (eeh_enabled())
  55                 eeh_send_failure_event(NULL);
  56         else
  57                 opal_notifier_update_evt(OPAL_EVENT_PCI_ERROR, 0x0ul);
  58
  59         return 0;
  60 }
  61
  62 static struct notifier_block ioda_eeh_nb = {
  63         .notifier_call  = ioda_eeh_event,
  64         .next           = NULL,
  65         .priority       = 0
  66 };
  67
  68 #ifdef CONFIG_DEBUG_FS
  69 static int ioda_eeh_dbgfs_set(void *data, int offset, u64 val)
  70 {
  71         struct pci_controller *hose = data;
  72         struct pnv_phb *phb = hose->private_data;
  73
  74         out_be64(phb->regs + offset, val);
  75         return 0;
  76 }
  77
  78 static int ioda_eeh_dbgfs_get(void *data, int offset, u64 *val)
  79 {
  80         struct pci_controller *hose = data;
  81         struct pnv_phb *phb = hose->private_data;
  82
  83         *val = in_be64(phb->regs + offset);
  84         return 0;
  85 }
  86
  87 static int ioda_eeh_outb_dbgfs_set(void *data, u64 val)
  88 {
  89         return ioda_eeh_dbgfs_set(data, 0xD10, val);
  90 }
  91
  92 static int ioda_eeh_outb_dbgfs_get(void *data, u64 *val)
  93 {
  94         return ioda_eeh_dbgfs_get(data, 0xD10, val);
  95 }
  96
  97 static int ioda_eeh_inbA_dbgfs_set(void *data, u64 val)
  98 {
  99         return ioda_eeh_dbgfs_set(data, 0xD90, val);
 100 }
 101
 102 static int ioda_eeh_inbA_dbgfs_get(void *data, u64 *val)
 103 {
 104         return ioda_eeh_dbgfs_get(data, 0xD90, val);
 105 }
 106
 107 static int ioda_eeh_inbB_dbgfs_set(void *data, u64 val)
 108 {
 109         return ioda_eeh_dbgfs_set(data, 0xE10, val);
 110 }
 111
 112 static int ioda_eeh_inbB_dbgfs_get(void *data, u64 *val)
 113 {
 114         return ioda_eeh_dbgfs_get(data, 0xE10, val);
 115 }
 116
 117 DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_outb_dbgfs_ops, ioda_eeh_outb_dbgfs_get,
 118                         ioda_eeh_outb_dbgfs_set, "0x%llx\n");
 119 DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_inbA_dbgfs_ops, ioda_eeh_inbA_dbgfs_get,
 120                         ioda_eeh_inbA_dbgfs_set, "0x%llx\n");
 121 DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_inbB_dbgfs_ops, ioda_eeh_inbB_dbgfs_get,
 122                         ioda_eeh_inbB_dbgfs_set, "0x%llx\n");
 123 #endif /* CONFIG_DEBUG_FS */
 124
 125
 126 /**
 127  * ioda_eeh_post_init - Chip dependent post initialization
 128  * @hose: PCI controller
 129  *
 130  * The function will be called after eeh PEs and devices
 131  * have been built. That means the EEH is ready to supply
 132  * service with I/O cache.
 133  */
 134 static int ioda_eeh_post_init(struct pci_controller *hose)
 135 {
 136         struct pnv_phb *phb = hose->private_data;
 137         int ret;
 138
 139         /* Register OPAL event notifier */
 140         if (!ioda_eeh_nb_init) {
 141                 ret = opal_notifier_register(&ioda_eeh_nb);
 142                 if (ret) {
 143                         pr_err("%s: Can't register OPAL event notifier (%d)\n",
 144                                __func__, ret);
 145                         return ret;
 146                 }
 147
 148                 ioda_eeh_nb_init = 1;
 149         }
 150
 151 #ifdef CONFIG_DEBUG_FS
 152         if (!phb->has_dbgfs && phb->dbgfs) {
 153                 phb->has_dbgfs = 1;
 154
 155                 debugfs_create_file("err_injct_outbound", 0600,
 156                                     phb->dbgfs, hose,
 157                                     &ioda_eeh_outb_dbgfs_ops);
 158                 debugfs_create_file("err_injct_inboundA", 0600,
 159                                     phb->dbgfs, hose,
 160                                     &ioda_eeh_inbA_dbgfs_ops);
 161                 debugfs_create_file("err_injct_inboundB", 0600,
 162                                     phb->dbgfs, hose,
 163                                     &ioda_eeh_inbB_dbgfs_ops);
 164         }
 165 #endif
 166
 167         /* If EEH is enabled, we're going to rely on that.
 168          * Otherwise, we restore to conventional mechanism
 169          * to clear frozen PE during PCI config access.
 170          */
 171         if (eeh_enabled())
 172                 phb->flags |= PNV_PHB_FLAG_EEH;
 173         else
 174                 phb->flags &= ~PNV_PHB_FLAG_EEH;
 175
 176         return 0;
 177 }
 178
 179 /**
 180  * ioda_eeh_set_option - Set EEH operation or I/O setting
 181  * @pe: EEH PE
 182  * @option: options
 183  *
 184  * Enable or disable EEH option for the indicated PE. The
 185  * function also can be used to enable I/O or DMA for the
 186  * PE.
 187  */
 188 static int ioda_eeh_set_option(struct eeh_pe *pe, int option)
 189 {
 190         s64 ret;
 191         u32 pe_no;
 192         struct pci_controller *hose = pe->phb;
 193         struct pnv_phb *phb = hose->private_data;
 194
 195         /* Check on PE number */
 196         if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
 197                 pr_err("%s: PE address %x out of range [0, %x] "
 198                        "on PHB#%x\n",
 199                         __func__, pe->addr, phb->ioda.total_pe,
 200                         hose->global_number);
 201                 return -EINVAL;
 202         }
 203
 204         pe_no = pe->addr;
 205         switch (option) {
 206         case EEH_OPT_DISABLE:
 207                 ret = -EEXIST;
 208                 break;
 209         case EEH_OPT_ENABLE:
 210                 ret = 0;
 211                 break;
 212         case EEH_OPT_THAW_MMIO:
 213                 ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
 214                                 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO);
 215                 if (ret) {
 216                         pr_warning("%s: Failed to enable MMIO for "
 217                                    "PHB#%x-PE#%x, err=%lld\n",
 218                                 __func__, hose->global_number, pe_no, ret);
 219                         return -EIO;
 220                 }
 221
 222                 break;
 223         case EEH_OPT_THAW_DMA:
 224                 ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
 225                                 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA);
 226                 if (ret) {
 227                         pr_warning("%s: Failed to enable DMA for "
 228                                    "PHB#%x-PE#%x, err=%lld\n",
 229                                 __func__, hose->global_number, pe_no, ret);
 230                         return -EIO;
 231                 }
 232
 233                 break;
 234         default:
 235                 pr_warning("%s: Invalid option %d\n", __func__, option);
 236                 return -EINVAL;
 237         }
 238
 239         return ret;
 240 }
 241
 242 static void ioda_eeh_phb_diag(struct pci_controller *hose)
 243 {
 244         struct pnv_phb *phb = hose->private_data;
 245         long rc;
 246
 247         rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
 248                                          PNV_PCI_DIAG_BUF_SIZE);
 249         if (rc != OPAL_SUCCESS) {
 250                 pr_warning("%s: Failed to get diag-data for PHB#%x (%ld)\n",
 251                             __func__, hose->global_number, rc);
 252                 return;
 253         }
 254
 255         pnv_pci_dump_phb_diag_data(hose, phb->diag.blob);
 256 }
 257
 258 /**
 259  * ioda_eeh_get_state - Retrieve the state of PE
 260  * @pe: EEH PE
 261  *
 262  * The PE's state should be retrieved from the PEEV, PEST
 263  * IODA tables. Since the OPAL has exported the function
 264  * to do it, it'd better to use that.
 265  */
 266 static int ioda_eeh_get_state(struct eeh_pe *pe)
 267 {
 268         s64 ret = 0;
 269         u8 fstate;
 270         u16 pcierr;
 271         u32 pe_no;
 272         int result;
 273         struct pci_controller *hose = pe->phb;
 274         struct pnv_phb *phb = hose->private_data;
 275
 276         /*
 277          * Sanity check on PE address. The PHB PE address should
 278          * be zero.
 279          */
 280         if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
 281                 pr_err("%s: PE address %x out of range [0, %x] "
 282                        "on PHB#%x\n",
 283                        __func__, pe->addr, phb->ioda.total_pe,
 284                        hose->global_number);
 285                 return EEH_STATE_NOT_SUPPORT;
 286         }
 287
 288         /*
 289          * If we're in middle of PE reset, return normal
 290          * state to keep EEH core going. For PHB reset, we
 291          * still expect to have fenced PHB cleared with
 292          * PHB reset.
 293          */
 294         if (!(pe->type & EEH_PE_PHB) &&
 295             (pe->state & EEH_PE_RESET)) {
 296                 result = (EEH_STATE_MMIO_ACTIVE |
 297                           EEH_STATE_DMA_ACTIVE |
 298                           EEH_STATE_MMIO_ENABLED |
 299                           EEH_STATE_DMA_ENABLED);
 300                 return result;
 301         }
 302
 303         /* Retrieve PE status through OPAL */
 304         pe_no = pe->addr;
 305         ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 306                         &fstate, &pcierr, NULL);
 307         if (ret) {
 308                 pr_err("%s: Failed to get EEH status on "
 309                        "PHB#%x-PE#%x\n, err=%lld\n",
 310                        __func__, hose->global_number, pe_no, ret);
 311                 return EEH_STATE_NOT_SUPPORT;
 312         }
 313
 314         /* Check PHB status */
 315         if (pe->type & EEH_PE_PHB) {
 316                 result = 0;
 317                 result &= ~EEH_STATE_RESET_ACTIVE;
 318
 319                 if (pcierr != OPAL_EEH_PHB_ERROR) {
 320                         result |= EEH_STATE_MMIO_ACTIVE;
 321                         result |= EEH_STATE_DMA_ACTIVE;
 322                         result |= EEH_STATE_MMIO_ENABLED;
 323                         result |= EEH_STATE_DMA_ENABLED;
 324                 } else if (!(pe->state & EEH_PE_ISOLATED)) {
 325                         eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
 326                         ioda_eeh_phb_diag(hose);
 327                 }
 328
 329                 return result;
 330         }
 331
 332         /* Parse result out */
 333         result = 0;
 334         switch (fstate) {
 335         case OPAL_EEH_STOPPED_NOT_FROZEN:
 336                 result &= ~EEH_STATE_RESET_ACTIVE;
 337                 result |= EEH_STATE_MMIO_ACTIVE;
 338                 result |= EEH_STATE_DMA_ACTIVE;
 339                 result |= EEH_STATE_MMIO_ENABLED;
 340                 result |= EEH_STATE_DMA_ENABLED;
 341                 break;
 342         case OPAL_EEH_STOPPED_MMIO_FREEZE:
 343                 result &= ~EEH_STATE_RESET_ACTIVE;
 344                 result |= EEH_STATE_DMA_ACTIVE;
 345                 result |= EEH_STATE_DMA_ENABLED;
 346                 break;
 347         case OPAL_EEH_STOPPED_DMA_FREEZE:
 348                 result &= ~EEH_STATE_RESET_ACTIVE;
 349                 result |= EEH_STATE_MMIO_ACTIVE;
 350                 result |= EEH_STATE_MMIO_ENABLED;
 351                 break;
 352         case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
 353                 result &= ~EEH_STATE_RESET_ACTIVE;
 354                 break;
 355         case OPAL_EEH_STOPPED_RESET:
 356                 result |= EEH_STATE_RESET_ACTIVE;
 357                 break;
 358         case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
 359                 result |= EEH_STATE_UNAVAILABLE;
 360                 break;
 361         case OPAL_EEH_STOPPED_PERM_UNAVAIL:
 362                 result |= EEH_STATE_NOT_SUPPORT;
 363                 break;
 364         default:
 365                 pr_warning("%s: Unexpected EEH status 0x%x "
 366                            "on PHB#%x-PE#%x\n",
 367                            __func__, fstate, hose->global_number, pe_no);
 368         }
 369
 370         /* Dump PHB diag-data for frozen PE */
 371         if (result != EEH_STATE_NOT_SUPPORT &&
 372             (result & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) !=
 373             (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE) &&
 374             !(pe->state & EEH_PE_ISOLATED)) {
 375                 eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
 376                 ioda_eeh_phb_diag(hose);
 377         }
 378
 379         return result;
 380 }
 381
 382 static s64 ioda_eeh_phb_poll(struct pnv_phb *phb)
 383 {
 384         s64 rc = OPAL_HARDWARE;
 385
 386         while (1) {
 387                 rc = opal_pci_poll(phb->opal_id);
 388                 if (rc <= 0)
 389                         break;
 390
 391                 if (system_state < SYSTEM_RUNNING)
 392                         udelay(1000 * rc);
 393                 else
 394                         msleep(rc);
 395         }
 396
 397         return rc;
 398 }
 399
 400 int ioda_eeh_phb_reset(struct pci_controller *hose, int option)
 401 {
 402         struct pnv_phb *phb = hose->private_data;
 403         s64 rc = OPAL_HARDWARE;
 404
 405         pr_debug("%s: Reset PHB#%x, option=%d\n",
 406                  __func__, hose->global_number, option);
 407
 408         /* Issue PHB complete reset request */
 409         if (option == EEH_RESET_FUNDAMENTAL ||
 410             option == EEH_RESET_HOT)
 411                 rc = opal_pci_reset(phb->opal_id,
 412                                 OPAL_PHB_COMPLETE,
 413                                 OPAL_ASSERT_RESET);
 414         else if (option == EEH_RESET_DEACTIVATE)
 415                 rc = opal_pci_reset(phb->opal_id,
 416                                 OPAL_PHB_COMPLETE,
 417                                 OPAL_DEASSERT_RESET);
 418         if (rc < 0)
 419                 goto out;
 420
 421         /*
 422          * Poll state of the PHB until the request is done
 423          * successfully. The PHB reset is usually PHB complete
 424          * reset followed by hot reset on root bus. So we also
 425          * need the PCI bus settlement delay.
 426          */
 427         rc = ioda_eeh_phb_poll(phb);
 428         if (option == EEH_RESET_DEACTIVATE) {
 429                 if (system_state < SYSTEM_RUNNING)
 430                         udelay(1000 * EEH_PE_RST_SETTLE_TIME);
 431                 else
 432                         msleep(EEH_PE_RST_SETTLE_TIME);
 433         }
 434 out:
 435         if (rc != OPAL_SUCCESS)
 436                 return -EIO;
 437
 438         return 0;
 439 }
 440
 441 static int ioda_eeh_root_reset(struct pci_controller *hose, int option)
 442 {
 443         struct pnv_phb *phb = hose->private_data;
 444         s64 rc = OPAL_SUCCESS;
 445
 446         pr_debug("%s: Reset PHB#%x, option=%d\n",
 447                  __func__, hose->global_number, option);
 448
 449         /*
 450          * During the reset deassert time, we needn't care
 451          * the reset scope because the firmware does nothing
 452          * for fundamental or hot reset during deassert phase.
 453          */
 454         if (option == EEH_RESET_FUNDAMENTAL)
 455                 rc = opal_pci_reset(phb->opal_id,
 456                                 OPAL_PCI_FUNDAMENTAL_RESET,
 457                                 OPAL_ASSERT_RESET);
 458         else if (option == EEH_RESET_HOT)
 459                 rc = opal_pci_reset(phb->opal_id,
 460                                 OPAL_PCI_HOT_RESET,
 461                                 OPAL_ASSERT_RESET);
 462         else if (option == EEH_RESET_DEACTIVATE)
 463                 rc = opal_pci_reset(phb->opal_id,
 464                                 OPAL_PCI_HOT_RESET,
 465                                 OPAL_DEASSERT_RESET);
 466         if (rc < 0)
 467                 goto out;
 468
 469         /* Poll state of the PHB until the request is done */
 470         rc = ioda_eeh_phb_poll(phb);
 471         if (option == EEH_RESET_DEACTIVATE)
 472                 msleep(EEH_PE_RST_SETTLE_TIME);
 473 out:
 474         if (rc != OPAL_SUCCESS)
 475                 return -EIO;
 476
 477         return 0;
 478 }
 479
 480 static bool ioda_eeh_is_plx_dnport(struct pci_dev *dev, int *reg,
 481                                    int *mask, int *len)
 482 {
 483         unsigned short *pid;
 484         unsigned short ids[] = {
 485                 0x10b5, 0x8748, 0x0080, 0x0400, /* PLX#8748     */
 486                 0x0000, 0x0000, 0x0000, 0x0000, /* End flag     */
 487         };
 488
 489         if (!pci_is_pcie(dev))
 490                 return false;
 491         if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
 492                 return false;
 493
 494         pid = &ids[0];
 495         while (!reg) {
 496                 if (pid[0] == 0x0)
 497                         break;
 498
 499                 if (dev->vendor == pid[0] &&
 500                     dev->device == pid[1]) {
 501                         *reg  = pid[2];
 502                         *mask = pid[3];
 503                         *len  = 2;
 504                         return true;
 505                 }
 506         }
 507
 508         *reg  = PCI_BRIDGE_CONTROL;
 509         *mask = PCI_BRIDGE_CTL_BUS_RESET;
 510         *len  = 2;
 511         return false;
 512 }
 513
 514 static int ioda_eeh_bridge_reset(struct pci_dev *dev, int option)
 515
 516 {
 517         struct device_node *dn = pci_device_to_OF_node(dev);
 518         struct eeh_dev *edev = of_node_to_eeh_dev(dn);
 519         int aer = edev ? edev->aer_cap : 0;
 520         int reg, mask, val, len;
 521         bool is_plx_dnport;
 522
 523         pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n",
 524                  __func__, pci_domain_nr(dev->bus),
 525                  dev->bus->number, option);
 526
 527
 528         is_plx_dnport = ioda_eeh_is_plx_dnport(dev, &reg, &mask, &len);
 529         if (option == EEH_RESET_FUNDAMENTAL)
 530                 if (!is_plx_dnport || !edev)
 531                         option = EEH_RESET_HOT;
 532
 533         if (option == EEH_RESET_HOT) {
 534                 reg  = PCI_BRIDGE_CONTROL;
 535                 mask = PCI_BRIDGE_CTL_BUS_RESET;
 536                 len  = 2;
 537         }
 538
 539         if (option == EEH_RESET_DEACTIVATE) {
 540                 if (!is_plx_dnport || !edev ||
 541                     !(edev->mode & EEH_DEV_FRESET)) {
 542                         reg  = PCI_BRIDGE_CONTROL;
 543                         mask = PCI_BRIDGE_CTL_BUS_RESET;
 544                         len  = 2;
 545                 }
 546         }
 547
 548         switch (option) {
 549         case EEH_RESET_FUNDAMENTAL:
 550                 edev->mode |= EEH_DEV_FRESET;
 551                 /* Fall through */
 552         case EEH_RESET_HOT:
 553                 if (aer) {
 554                         /* Mask receiver error */
 555                         eeh_ops->read_config(dn, aer + PCI_ERR_COR_MASK,
 556                                              4, &val);
 557                         val |= PCI_ERR_COR_RCVR;
 558                         eeh_ops->write_config(dn, aer + PCI_ERR_COR_MASK,
 559                                               4, val);
 560
 561                         /* Mask linkDown */
 562                         eeh_ops->read_config(dn, aer + PCI_ERR_UNCOR_MASK,
 563                                              4, &val);
 564                         val |= PCI_ERR_UNC_SURPDN;
 565                         eeh_ops->write_config(dn, aer + PCI_ERR_UNCOR_MASK,
 566                                               4, val);
 567                 }
 568
 569                 eeh_ops->read_config(dn, reg, len, &val);
 570                 val |= mask;
 571                 eeh_ops->write_config(dn, reg, len, val);
 572                 msleep(EEH_PE_RST_HOLD_TIME);
 573
 574                 break;
 575         case EEH_RESET_DEACTIVATE:
 576                 eeh_ops->read_config(dn, reg, len, &val);
 577                 val &= ~mask;
 578                 eeh_ops->write_config(dn, reg, len, val);
 579                 msleep(EEH_PE_RST_SETTLE_TIME);
 580
 581                 if (edev)
 582                         edev->mode &= ~EEH_DEV_FRESET;
 583                 if (aer) {
 584                         /* Clear receive error and enable it */
 585                         eeh_ops->write_config(dn, aer + PCI_ERR_COR_STATUS,
 586                                               4, PCI_ERR_COR_RCVR);
 587                         eeh_ops->read_config(dn, aer + PCI_ERR_COR_MASK,
 588                                              4, &val);
 589                         val &= ~PCI_ERR_COR_RCVR;
 590                         eeh_ops->write_config(dn, aer + PCI_ERR_COR_MASK,
 591                                               4, val);
 592
 593                         /* Clear linkDown and enable it */
 594                         eeh_ops->write_config(dn, aer + PCI_ERR_UNCOR_STATUS,
 595                                               4, PCI_ERR_UNC_SURPDN);
 596                         eeh_ops->read_config(dn, aer + PCI_ERR_UNCOR_MASK,
 597                                              4, &val);
 598                         val &= ~PCI_ERR_UNC_SURPDN;
 599                         eeh_ops->write_config(dn, aer + PCI_ERR_UNCOR_MASK,
 600                                               4, val);
 601                 }
 602
 603                 break;
 604         }
 605
 606         return 0;
 607 }
 608
 609 void pnv_pci_reset_secondary_bus(struct pci_dev *dev)
 610 {
 611         struct pci_controller *hose;
 612
 613         if (pci_is_root_bus(dev->bus)) {
 614                 hose = pci_bus_to_host(dev->bus);
 615                 ioda_eeh_root_reset(hose, EEH_RESET_HOT);
 616                 ioda_eeh_root_reset(hose, EEH_RESET_DEACTIVATE);
 617         } else {
 618                 ioda_eeh_bridge_reset(dev, EEH_RESET_HOT);
 619                 ioda_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE);
 620         }
 621 }
 622
 623 /**
 624  * ioda_eeh_reset - Reset the indicated PE
 625  * @pe: EEH PE
 626  * @option: reset option
 627  *
 628  * Do reset on the indicated PE. For PCI bus sensitive PE,
 629  * we need to reset the parent p2p bridge. The PHB has to
 630  * be reinitialized if the p2p bridge is root bridge. For
 631  * PCI device sensitive PE, we will try to reset the device
 632  * through FLR. For now, we don't have OPAL APIs to do HARD
 633  * reset yet, so all reset would be SOFT (HOT) reset.
 634  */
 635 static int ioda_eeh_reset(struct eeh_pe *pe, int option)
 636 {
 637         struct pci_controller *hose = pe->phb;
 638         struct pci_bus *bus;
 639         int ret;
 640
 641         /*
 642          * For PHB reset, we always have complete reset. For those PEs whose
 643          * primary bus derived from root complex (root bus) or root port
 644          * (usually bus#1), we apply hot or fundamental reset on the root port.
 645          * For other PEs, we always have hot reset on the PE primary bus.
 646          *
 647          * Here, we have different design to pHyp, which always clear the
 648          * frozen state during PE reset. However, the good idea here from
 649          * benh is to keep frozen state before we get PE reset done completely
 650          * (until BAR restore). With the frozen state, HW drops illegal IO
 651          * or MMIO access, which can incur recrusive frozen PE during PE
 652          * reset. The side effect is that EEH core has to clear the frozen
 653          * state explicitly after BAR restore.
 654          */
 655         if (pe->type & EEH_PE_PHB) {
 656                 ret = ioda_eeh_phb_reset(hose, option);
 657         } else {
 658                 bus = eeh_pe_bus_get(pe);
 659                 if (pci_is_root_bus(bus) ||
 660                     pci_is_root_bus(bus->parent))
 661                         ret = ioda_eeh_root_reset(hose, option);
 662                 else
 663                         ret = ioda_eeh_bridge_reset(bus->self, option);
 664         }
 665
 666         return ret;
 667 }
 668
 669 /**
 670  * ioda_eeh_configure_bridge - Configure the PCI bridges for the indicated PE
 671  * @pe: EEH PE
 672  *
 673  * For particular PE, it might have included PCI bridges. In order
 674  * to make the PE work properly, those PCI bridges should be configured
 675  * correctly. However, we need do nothing on P7IOC since the reset
 676  * function will do everything that should be covered by the function.
 677  */
 678 static int ioda_eeh_configure_bridge(struct eeh_pe *pe)
 679 {
 680         return 0;
 681 }
 682
 683 static void ioda_eeh_hub_diag_common(struct OpalIoP7IOCErrorData *data)
 684 {
 685         /* GEM */
 686         pr_info("  GEM XFIR:        %016llx\n", data->gemXfir);
 687         pr_info("  GEM RFIR:        %016llx\n", data->gemRfir);
 688         pr_info("  GEM RIRQFIR:     %016llx\n", data->gemRirqfir);
 689         pr_info("  GEM Mask:        %016llx\n", data->gemMask);
 690         pr_info("  GEM RWOF:        %016llx\n", data->gemRwof);
 691
 692         /* LEM */
 693         pr_info("  LEM FIR:         %016llx\n", data->lemFir);
 694         pr_info("  LEM Error Mask:  %016llx\n", data->lemErrMask);
 695         pr_info("  LEM Action 0:    %016llx\n", data->lemAction0);
 696         pr_info("  LEM Action 1:    %016llx\n", data->lemAction1);
 697         pr_info("  LEM WOF:         %016llx\n", data->lemWof);
 698 }
 699
 700 static void ioda_eeh_hub_diag(struct pci_controller *hose)
 701 {
 702         struct pnv_phb *phb = hose->private_data;
 703         struct OpalIoP7IOCErrorData *data = &phb->diag.hub_diag;
 704         long rc;
 705
 706         rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data));
 707         if (rc != OPAL_SUCCESS) {
 708                 pr_warning("%s: Failed to get HUB#%llx diag-data (%ld)\n",
 709                            __func__, phb->hub_id, rc);
 710                 return;
 711         }
 712
 713         switch (data->type) {
 714         case OPAL_P7IOC_DIAG_TYPE_RGC:
 715                 pr_info("P7IOC diag-data for RGC\n\n");
 716                 ioda_eeh_hub_diag_common(data);
 717                 pr_info("  RGC Status:      %016llx\n", data->rgc.rgcStatus);
 718                 pr_info("  RGC LDCP:        %016llx\n", data->rgc.rgcLdcp);
 719                 break;
 720         case OPAL_P7IOC_DIAG_TYPE_BI:
 721                 pr_info("P7IOC diag-data for BI %s\n\n",
 722                         data->bi.biDownbound ? "Downbound" : "Upbound");
 723                 ioda_eeh_hub_diag_common(data);
 724                 pr_info("  BI LDCP 0:       %016llx\n", data->bi.biLdcp0);
 725                 pr_info("  BI LDCP 1:       %016llx\n", data->bi.biLdcp1);
 726                 pr_info("  BI LDCP 2:       %016llx\n", data->bi.biLdcp2);
 727                 pr_info("  BI Fence Status: %016llx\n", data->bi.biFenceStatus);
 728                 break;
 729         case OPAL_P7IOC_DIAG_TYPE_CI:
 730                 pr_info("P7IOC diag-data for CI Port %d\\nn",
 731                         data->ci.ciPort);
 732                 ioda_eeh_hub_diag_common(data);
 733                 pr_info("  CI Port Status:  %016llx\n", data->ci.ciPortStatus);
 734                 pr_info("  CI Port LDCP:    %016llx\n", data->ci.ciPortLdcp);
 735                 break;
 736         case OPAL_P7IOC_DIAG_TYPE_MISC:
 737                 pr_info("P7IOC diag-data for MISC\n\n");
 738                 ioda_eeh_hub_diag_common(data);
 739                 break;
 740         case OPAL_P7IOC_DIAG_TYPE_I2C:
 741                 pr_info("P7IOC diag-data for I2C\n\n");
 742                 ioda_eeh_hub_diag_common(data);
 743                 break;
 744         default:
 745                 pr_warning("%s: Invalid type of HUB#%llx diag-data (%d)\n",
 746                            __func__, phb->hub_id, data->type);
 747         }
 748 }
 749
 750 static int ioda_eeh_get_pe(struct pci_controller *hose,
 751                            u16 pe_no, struct eeh_pe **pe)
 752 {
 753         struct eeh_pe *phb_pe, *dev_pe;
 754         struct eeh_dev dev;
 755
 756         /* Find the PHB PE */
 757         phb_pe = eeh_phb_pe_get(hose);
 758         if (!phb_pe)
 759                 return -EEXIST;
 760
 761         /* Find the PE according to PE# */
 762         memset(&dev, 0, sizeof(struct eeh_dev));
 763         dev.phb = hose;
 764         dev.pe_config_addr = pe_no;
 765         dev_pe = eeh_pe_get(&dev);
 766         if (!dev_pe) return -EEXIST;
 767
 768         *pe = dev_pe;
 769         return 0;
 770 }
 771
 772 /**
 773  * ioda_eeh_next_error - Retrieve next error for EEH core to handle
 774  * @pe: The affected PE
 775  *
 776  * The function is expected to be called by EEH core while it gets
 777  * special EEH event (without binding PE). The function calls to
 778  * OPAL APIs for next error to handle. The informational error is
 779  * handled internally by platform. However, the dead IOC, dead PHB,
 780  * fenced PHB and frozen PE should be handled by EEH core eventually.
 781  */
 782 static int ioda_eeh_next_error(struct eeh_pe **pe)
 783 {
 784         struct pci_controller *hose;
 785         struct pnv_phb *phb;
 786         struct eeh_pe *phb_pe;
 787         u64 frozen_pe_no;
 788         u16 err_type, severity;
 789         long rc;
 790         int ret = EEH_NEXT_ERR_NONE;
 791
 792         /*
 793          * While running here, it's safe to purge the event queue.
 794          * And we should keep the cached OPAL notifier event sychronized
 795          * between the kernel and firmware.
 796          */
 797         eeh_remove_event(NULL);
 798         opal_notifier_update_evt(OPAL_EVENT_PCI_ERROR, 0x0ul);
 799
 800         list_for_each_entry(hose, &hose_list, list_node) {
 801                 /*
 802                  * If the subordinate PCI buses of the PHB has been
 803                  * removed or is exactly under error recovery, we
 804                  * needn't take care of it any more.
 805                  */
 806                 phb = hose->private_data;
 807                 phb_pe = eeh_phb_pe_get(hose);
 808                 if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED))
 809                         continue;
 810
 811                 rc = opal_pci_next_error(phb->opal_id,
 812                                 &frozen_pe_no, &err_type, &severity);
 813
 814                 /* If OPAL API returns error, we needn't proceed */
 815                 if (rc != OPAL_SUCCESS) {
 816                         pr_devel("%s: Invalid return value on "
 817                                  "PHB#%x (0x%lx) from opal_pci_next_error",
 818                                  __func__, hose->global_number, rc);
 819                         continue;
 820                 }
 821
 822                 /* If the PHB doesn't have error, stop processing */
 823                 if (err_type == OPAL_EEH_NO_ERROR ||
 824                     severity == OPAL_EEH_SEV_NO_ERROR) {
 825                         pr_devel("%s: No error found on PHB#%x\n",
 826                                  __func__, hose->global_number);
 827                         continue;
 828                 }
 829
 830                 /*
 831                  * Processing the error. We're expecting the error with
 832                  * highest priority reported upon multiple errors on the
 833                  * specific PHB.
 834                  */
 835                 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n",
 836                          __func__, err_type, severity,
 837                          frozen_pe_no, hose->global_number);
 838                 switch (err_type) {
 839                 case OPAL_EEH_IOC_ERROR:
 840                         if (severity == OPAL_EEH_SEV_IOC_DEAD) {
 841                                 pr_err("EEH: dead IOC detected\n");
 842                                 ret = EEH_NEXT_ERR_DEAD_IOC;
 843                         } else if (severity == OPAL_EEH_SEV_INF) {
 844                                 pr_info("EEH: IOC informative error "
 845                                         "detected\n");
 846                                 ioda_eeh_hub_diag(hose);
 847                                 ret = EEH_NEXT_ERR_NONE;
 848                         }
 849
 850                         break;
 851                 case OPAL_EEH_PHB_ERROR:
 852                         if (severity == OPAL_EEH_SEV_PHB_DEAD) {
 853                                 *pe = phb_pe;
 854                                 pr_err("EEH: dead PHB#%x detected\n",
 855                                         hose->global_number);
 856                                 ret = EEH_NEXT_ERR_DEAD_PHB;
 857                         } else if (severity == OPAL_EEH_SEV_PHB_FENCED) {
 858                                 *pe = phb_pe;
 859                                 pr_err("EEH: fenced PHB#%x detected\n",
 860                                         hose->global_number);
 861                                 ret = EEH_NEXT_ERR_FENCED_PHB;
 862                         } else if (severity == OPAL_EEH_SEV_INF) {
 863                                 pr_info("EEH: PHB#%x informative error "
 864                                         "detected\n",
 865                                         hose->global_number);
 866                                 ioda_eeh_phb_diag(hose);
 867                                 ret = EEH_NEXT_ERR_NONE;
 868                         }
 869
 870                         break;
 871                 case OPAL_EEH_PE_ERROR:
 872                         /*
 873                          * If we can't find the corresponding PE, the
 874                          * PEEV / PEST would be messy. So we force an
 875                          * fenced PHB so that it can be recovered.
 876                          *
 877                          * If the PE has been marked as isolated, that
 878                          * should have been removed permanently or in
 879                          * progress with recovery. We needn't report
 880                          * it again.
 881                          */
 882                         if (ioda_eeh_get_pe(hose, frozen_pe_no, pe)) {
 883                                 *pe = phb_pe;
 884                                 pr_err("EEH: Escalated fenced PHB#%x "
 885                                        "detected for PE#%llx\n",
 886                                         hose->global_number,
 887                                         frozen_pe_no);
 888                                 ret = EEH_NEXT_ERR_FENCED_PHB;
 889                         } else if ((*pe)->state & EEH_PE_ISOLATED) {
 890                                 ret = EEH_NEXT_ERR_NONE;
 891                         } else {
 892                                 pr_err("EEH: Frozen PE#%x on PHB#%x detected\n",
 893                                         (*pe)->addr, (*pe)->phb->global_number);
 894                                 ret = EEH_NEXT_ERR_FROZEN_PE;
 895                         }
 896
 897                         break;
 898                 default:
 899                         pr_warn("%s: Unexpected error type %d\n",
 900                                 __func__, err_type);
 901                 }
 902
 903                 /*
 904                  * EEH core will try recover from fenced PHB or
 905                  * frozen PE. In the time for frozen PE, EEH core
 906                  * enable IO path for that before collecting logs,
 907                  * but it ruins the site. So we have to dump the
 908                  * log in advance here.
 909                  */
 910                 if ((ret == EEH_NEXT_ERR_FROZEN_PE  ||
 911                     ret == EEH_NEXT_ERR_FENCED_PHB) &&
 912                     !((*pe)->state & EEH_PE_ISOLATED)) {
 913                         eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);
 914                         ioda_eeh_phb_diag(hose);
 915                 }
 916
 917                 /*
 918                  * If we have no errors on the specific PHB or only
 919                  * informative error there, we continue poking it.
 920                  * Otherwise, we need actions to be taken by upper
 921                  * layer.
 922                  */
 923                 if (ret > EEH_NEXT_ERR_INF)
 924                         break;
 925         }
 926
 927         return ret;
 928 }
 929
 930 struct pnv_eeh_ops ioda_eeh_ops = {
 931         .post_init              = ioda_eeh_post_init,
 932         .set_option             = ioda_eeh_set_option,
 933         .get_state              = ioda_eeh_get_state,
 934         .reset                  = ioda_eeh_reset,
 935         .configure_bridge       = ioda_eeh_configure_bridge,
 936         .next_error             = ioda_eeh_next_error
 937 };