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1 /*
2  * The file intends to implement the functions needed by EEH, which is
3  * built on IODA compliant chip. Actually, lots of functions related
4  * to EEH would be built based on the OPAL APIs.
5  *
6  * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  */
13
14 #include <linux/bootmem.h>
15 #include <linux/delay.h>
16 #include <linux/init.h>
17 #include <linux/io.h>
18 #include <linux/irq.h>
19 #include <linux/kernel.h>
20 #include <linux/msi.h>
21 #include <linux/pci.h>
22 #include <linux/string.h>
23
24 #include <asm/eeh.h>
25 #include <asm/eeh_event.h>
26 #include <asm/io.h>
27 #include <asm/iommu.h>
28 #include <asm/msi_bitmap.h>
29 #include <asm/opal.h>
30 #include <asm/pci-bridge.h>
31 #include <asm/ppc-pci.h>
32 #include <asm/tce.h>
33
34 #include "powernv.h"
35 #include "pci.h"
36
37 /**
38  * ioda_eeh_post_init - Chip dependent post initialization
39  * @hose: PCI controller
40  *
41  * The function will be called after eeh PEs and devices
42  * have been built. That means the EEH is ready to supply
43  * service with I/O cache.
44  */
45 static int ioda_eeh_post_init(struct pci_controller *hose)
46 {
47         struct pnv_phb *phb = hose->private_data;
48
49         /* FIXME: Enable it for PHB3 later */
50         if (phb->type == PNV_PHB_IODA1)
51                 phb->eeh_enabled = 1;
52
53         return 0;
54 }
55
56 /**
57  * ioda_eeh_set_option - Set EEH operation or I/O setting
58  * @pe: EEH PE
59  * @option: options
60  *
61  * Enable or disable EEH option for the indicated PE. The
62  * function also can be used to enable I/O or DMA for the
63  * PE.
64  */
65 static int ioda_eeh_set_option(struct eeh_pe *pe, int option)
66 {
67         s64 ret;
68         u32 pe_no;
69         struct pci_controller *hose = pe->phb;
70         struct pnv_phb *phb = hose->private_data;
71
72         /* Check on PE number */
73         if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
74                 pr_err("%s: PE address %x out of range [0, %x] "
75                        "on PHB#%x\n",
76                         __func__, pe->addr, phb->ioda.total_pe,
77                         hose->global_number);
78                 return -EINVAL;
79         }
80
81         pe_no = pe->addr;
82         switch (option) {
83         case EEH_OPT_DISABLE:
84                 ret = -EEXIST;
85                 break;
86         case EEH_OPT_ENABLE:
87                 ret = 0;
88                 break;
89         case EEH_OPT_THAW_MMIO:
90                 ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
91                                 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO);
92                 if (ret) {
93                         pr_warning("%s: Failed to enable MMIO for "
94                                    "PHB#%x-PE#%x, err=%lld\n",
95                                 __func__, hose->global_number, pe_no, ret);
96                         return -EIO;
97                 }
98
99                 break;
100         case EEH_OPT_THAW_DMA:
101                 ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
102                                 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA);
103                 if (ret) {
104                         pr_warning("%s: Failed to enable DMA for "
105                                    "PHB#%x-PE#%x, err=%lld\n",
106                                 __func__, hose->global_number, pe_no, ret);
107                         return -EIO;
108                 }
109
110                 break;
111         default:
112                 pr_warning("%s: Invalid option %d\n", __func__, option);
113                 return -EINVAL;
114         }
115
116         return ret;
117 }
118
119 /**
120  * ioda_eeh_get_state - Retrieve the state of PE
121  * @pe: EEH PE
122  *
123  * The PE's state should be retrieved from the PEEV, PEST
124  * IODA tables. Since the OPAL has exported the function
125  * to do it, it'd better to use that.
126  */
127 static int ioda_eeh_get_state(struct eeh_pe *pe)
128 {
129         s64 ret = 0;
130         u8 fstate;
131         u16 pcierr;
132         u32 pe_no;
133         int result;
134         struct pci_controller *hose = pe->phb;
135         struct pnv_phb *phb = hose->private_data;
136
137         /*
138          * Sanity check on PE address. The PHB PE address should
139          * be zero.
140          */
141         if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
142                 pr_err("%s: PE address %x out of range [0, %x] "
143                        "on PHB#%x\n",
144                        __func__, pe->addr, phb->ioda.total_pe,
145                        hose->global_number);
146                 return EEH_STATE_NOT_SUPPORT;
147         }
148
149         /* Retrieve PE status through OPAL */
150         pe_no = pe->addr;
151         ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
152                         &fstate, &pcierr, NULL);
153         if (ret) {
154                 pr_err("%s: Failed to get EEH status on "
155                        "PHB#%x-PE#%x\n, err=%lld\n",
156                        __func__, hose->global_number, pe_no, ret);
157                 return EEH_STATE_NOT_SUPPORT;
158         }
159
160         /* Check PHB status */
161         if (pe->type & EEH_PE_PHB) {
162                 result = 0;
163                 result &= ~EEH_STATE_RESET_ACTIVE;
164
165                 if (pcierr != OPAL_EEH_PHB_ERROR) {
166                         result |= EEH_STATE_MMIO_ACTIVE;
167                         result |= EEH_STATE_DMA_ACTIVE;
168                         result |= EEH_STATE_MMIO_ENABLED;
169                         result |= EEH_STATE_DMA_ENABLED;
170                 }
171
172                 return result;
173         }
174
175         /* Parse result out */
176         result = 0;
177         switch (fstate) {
178         case OPAL_EEH_STOPPED_NOT_FROZEN:
179                 result &= ~EEH_STATE_RESET_ACTIVE;
180                 result |= EEH_STATE_MMIO_ACTIVE;
181                 result |= EEH_STATE_DMA_ACTIVE;
182                 result |= EEH_STATE_MMIO_ENABLED;
183                 result |= EEH_STATE_DMA_ENABLED;
184                 break;
185         case OPAL_EEH_STOPPED_MMIO_FREEZE:
186                 result &= ~EEH_STATE_RESET_ACTIVE;
187                 result |= EEH_STATE_DMA_ACTIVE;
188                 result |= EEH_STATE_DMA_ENABLED;
189                 break;
190         case OPAL_EEH_STOPPED_DMA_FREEZE:
191                 result &= ~EEH_STATE_RESET_ACTIVE;
192                 result |= EEH_STATE_MMIO_ACTIVE;
193                 result |= EEH_STATE_MMIO_ENABLED;
194                 break;
195         case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
196                 result &= ~EEH_STATE_RESET_ACTIVE;
197                 break;
198         case OPAL_EEH_STOPPED_RESET:
199                 result |= EEH_STATE_RESET_ACTIVE;
200                 break;
201         case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
202                 result |= EEH_STATE_UNAVAILABLE;
203                 break;
204         case OPAL_EEH_STOPPED_PERM_UNAVAIL:
205                 result |= EEH_STATE_NOT_SUPPORT;
206                 break;
207         default:
208                 pr_warning("%s: Unexpected EEH status 0x%x "
209                            "on PHB#%x-PE#%x\n",
210                            __func__, fstate, hose->global_number, pe_no);
211         }
212
213         return result;
214 }
215
216 struct pnv_eeh_ops ioda_eeh_ops = {
217         .post_init              = ioda_eeh_post_init,
218         .set_option             = ioda_eeh_set_option,
219         .get_state              = ioda_eeh_get_state,
220         .reset                  = NULL,
221         .get_log                = NULL,
222         .configure_bridge       = NULL,
223         .next_error             = NULL
224 };