2 * The file intends to implement the functions needed by EEH, which is
3 * built on IODA compliant chip. Actually, lots of functions related
4 * to EEH would be built based on the OPAL APIs.
6 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/bootmem.h>
15 #include <linux/debugfs.h>
16 #include <linux/delay.h>
18 #include <linux/irq.h>
19 #include <linux/kernel.h>
20 #include <linux/msi.h>
21 #include <linux/notifier.h>
22 #include <linux/pci.h>
23 #include <linux/string.h>
26 #include <asm/eeh_event.h>
28 #include <asm/iommu.h>
29 #include <asm/msi_bitmap.h>
31 #include <asm/pci-bridge.h>
32 #include <asm/ppc-pci.h>
38 static int ioda_eeh_nb_init = 0;
40 static int ioda_eeh_event(struct notifier_block *nb,
41 unsigned long events, void *change)
43 uint64_t changed_evts = (uint64_t)change;
45 /* We simply send special EEH event */
46 if ((changed_evts & OPAL_EVENT_PCI_ERROR) &&
47 (events & OPAL_EVENT_PCI_ERROR))
48 eeh_send_failure_event(NULL);
53 static struct notifier_block ioda_eeh_nb = {
54 .notifier_call = ioda_eeh_event,
59 #ifdef CONFIG_DEBUG_FS
60 static int ioda_eeh_dbgfs_set(void *data, int offset, u64 val)
62 struct pci_controller *hose = data;
63 struct pnv_phb *phb = hose->private_data;
65 out_be64(phb->regs + offset, val);
69 static int ioda_eeh_dbgfs_get(void *data, int offset, u64 *val)
71 struct pci_controller *hose = data;
72 struct pnv_phb *phb = hose->private_data;
74 *val = in_be64(phb->regs + offset);
78 static int ioda_eeh_outb_dbgfs_set(void *data, u64 val)
80 return ioda_eeh_dbgfs_set(data, 0xD10, val);
83 static int ioda_eeh_outb_dbgfs_get(void *data, u64 *val)
85 return ioda_eeh_dbgfs_get(data, 0xD10, val);
88 static int ioda_eeh_inbA_dbgfs_set(void *data, u64 val)
90 return ioda_eeh_dbgfs_set(data, 0xD90, val);
93 static int ioda_eeh_inbA_dbgfs_get(void *data, u64 *val)
95 return ioda_eeh_dbgfs_get(data, 0xD90, val);
98 static int ioda_eeh_inbB_dbgfs_set(void *data, u64 val)
100 return ioda_eeh_dbgfs_set(data, 0xE10, val);
103 static int ioda_eeh_inbB_dbgfs_get(void *data, u64 *val)
105 return ioda_eeh_dbgfs_get(data, 0xE10, val);
108 DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_outb_dbgfs_ops, ioda_eeh_outb_dbgfs_get,
109 ioda_eeh_outb_dbgfs_set, "0x%llx\n");
110 DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_inbA_dbgfs_ops, ioda_eeh_inbA_dbgfs_get,
111 ioda_eeh_inbA_dbgfs_set, "0x%llx\n");
112 DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_inbB_dbgfs_ops, ioda_eeh_inbB_dbgfs_get,
113 ioda_eeh_inbB_dbgfs_set, "0x%llx\n");
114 #endif /* CONFIG_DEBUG_FS */
117 * ioda_eeh_post_init - Chip dependent post initialization
118 * @hose: PCI controller
120 * The function will be called after eeh PEs and devices
121 * have been built. That means the EEH is ready to supply
122 * service with I/O cache.
124 static int ioda_eeh_post_init(struct pci_controller *hose)
126 struct pnv_phb *phb = hose->private_data;
129 /* Register OPAL event notifier */
130 if (!ioda_eeh_nb_init) {
131 ret = opal_notifier_register(&ioda_eeh_nb);
133 pr_err("%s: Can't register OPAL event notifier (%d)\n",
138 ioda_eeh_nb_init = 1;
141 #ifdef CONFIG_DEBUG_FS
143 debugfs_create_file("err_injct_outbound", 0600,
145 &ioda_eeh_outb_dbgfs_ops);
146 debugfs_create_file("err_injct_inboundA", 0600,
148 &ioda_eeh_inbA_dbgfs_ops);
149 debugfs_create_file("err_injct_inboundB", 0600,
151 &ioda_eeh_inbB_dbgfs_ops);
155 phb->eeh_state |= PNV_EEH_STATE_ENABLED;
161 * ioda_eeh_set_option - Set EEH operation or I/O setting
165 * Enable or disable EEH option for the indicated PE. The
166 * function also can be used to enable I/O or DMA for the
169 static int ioda_eeh_set_option(struct eeh_pe *pe, int option)
173 struct pci_controller *hose = pe->phb;
174 struct pnv_phb *phb = hose->private_data;
176 /* Check on PE number */
177 if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
178 pr_err("%s: PE address %x out of range [0, %x] "
180 __func__, pe->addr, phb->ioda.total_pe,
181 hose->global_number);
187 case EEH_OPT_DISABLE:
193 case EEH_OPT_THAW_MMIO:
194 ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
195 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO);
197 pr_warning("%s: Failed to enable MMIO for "
198 "PHB#%x-PE#%x, err=%lld\n",
199 __func__, hose->global_number, pe_no, ret);
204 case EEH_OPT_THAW_DMA:
205 ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
206 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA);
208 pr_warning("%s: Failed to enable DMA for "
209 "PHB#%x-PE#%x, err=%lld\n",
210 __func__, hose->global_number, pe_no, ret);
216 pr_warning("%s: Invalid option %d\n", __func__, option);
224 * ioda_eeh_get_state - Retrieve the state of PE
227 * The PE's state should be retrieved from the PEEV, PEST
228 * IODA tables. Since the OPAL has exported the function
229 * to do it, it'd better to use that.
231 static int ioda_eeh_get_state(struct eeh_pe *pe)
238 struct pci_controller *hose = pe->phb;
239 struct pnv_phb *phb = hose->private_data;
242 * Sanity check on PE address. The PHB PE address should
245 if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
246 pr_err("%s: PE address %x out of range [0, %x] "
248 __func__, pe->addr, phb->ioda.total_pe,
249 hose->global_number);
250 return EEH_STATE_NOT_SUPPORT;
253 /* Retrieve PE status through OPAL */
255 ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
256 &fstate, &pcierr, NULL);
258 pr_err("%s: Failed to get EEH status on "
259 "PHB#%x-PE#%x\n, err=%lld\n",
260 __func__, hose->global_number, pe_no, ret);
261 return EEH_STATE_NOT_SUPPORT;
264 /* Check PHB status */
265 if (pe->type & EEH_PE_PHB) {
267 result &= ~EEH_STATE_RESET_ACTIVE;
269 if (pcierr != OPAL_EEH_PHB_ERROR) {
270 result |= EEH_STATE_MMIO_ACTIVE;
271 result |= EEH_STATE_DMA_ACTIVE;
272 result |= EEH_STATE_MMIO_ENABLED;
273 result |= EEH_STATE_DMA_ENABLED;
279 /* Parse result out */
282 case OPAL_EEH_STOPPED_NOT_FROZEN:
283 result &= ~EEH_STATE_RESET_ACTIVE;
284 result |= EEH_STATE_MMIO_ACTIVE;
285 result |= EEH_STATE_DMA_ACTIVE;
286 result |= EEH_STATE_MMIO_ENABLED;
287 result |= EEH_STATE_DMA_ENABLED;
289 case OPAL_EEH_STOPPED_MMIO_FREEZE:
290 result &= ~EEH_STATE_RESET_ACTIVE;
291 result |= EEH_STATE_DMA_ACTIVE;
292 result |= EEH_STATE_DMA_ENABLED;
294 case OPAL_EEH_STOPPED_DMA_FREEZE:
295 result &= ~EEH_STATE_RESET_ACTIVE;
296 result |= EEH_STATE_MMIO_ACTIVE;
297 result |= EEH_STATE_MMIO_ENABLED;
299 case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
300 result &= ~EEH_STATE_RESET_ACTIVE;
302 case OPAL_EEH_STOPPED_RESET:
303 result |= EEH_STATE_RESET_ACTIVE;
305 case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
306 result |= EEH_STATE_UNAVAILABLE;
308 case OPAL_EEH_STOPPED_PERM_UNAVAIL:
309 result |= EEH_STATE_NOT_SUPPORT;
312 pr_warning("%s: Unexpected EEH status 0x%x "
314 __func__, fstate, hose->global_number, pe_no);
320 static int ioda_eeh_pe_clear(struct eeh_pe *pe)
322 struct pci_controller *hose;
331 phb = pe->phb->private_data;
333 /* Clear the EEH error on the PE */
334 ret = opal_pci_eeh_freeze_clear(phb->opal_id,
335 pe_no, OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
337 pr_err("%s: Failed to clear EEH error for "
338 "PHB#%x-PE#%x, err=%lld\n",
339 __func__, hose->global_number, pe_no, ret);
344 * Read the PE state back and verify that the frozen
345 * state has been removed.
347 ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
348 &fstate, &pcierr, NULL);
350 pr_err("%s: Failed to get EEH status on "
351 "PHB#%x-PE#%x\n, err=%lld\n",
352 __func__, hose->global_number, pe_no, ret);
356 if (fstate != OPAL_EEH_STOPPED_NOT_FROZEN) {
357 pr_err("%s: Frozen state not cleared on "
358 "PHB#%x-PE#%x, sts=%x\n",
359 __func__, hose->global_number, pe_no, fstate);
366 static s64 ioda_eeh_phb_poll(struct pnv_phb *phb)
368 s64 rc = OPAL_HARDWARE;
371 rc = opal_pci_poll(phb->opal_id);
381 static int ioda_eeh_phb_reset(struct pci_controller *hose, int option)
383 struct pnv_phb *phb = hose->private_data;
384 s64 rc = OPAL_HARDWARE;
386 pr_debug("%s: Reset PHB#%x, option=%d\n",
387 __func__, hose->global_number, option);
389 /* Issue PHB complete reset request */
390 if (option == EEH_RESET_FUNDAMENTAL ||
391 option == EEH_RESET_HOT)
392 rc = opal_pci_reset(phb->opal_id,
395 else if (option == EEH_RESET_DEACTIVATE)
396 rc = opal_pci_reset(phb->opal_id,
398 OPAL_DEASSERT_RESET);
403 * Poll state of the PHB until the request is done
406 rc = ioda_eeh_phb_poll(phb);
408 if (rc != OPAL_SUCCESS)
414 static int ioda_eeh_root_reset(struct pci_controller *hose, int option)
416 struct pnv_phb *phb = hose->private_data;
417 s64 rc = OPAL_SUCCESS;
419 pr_debug("%s: Reset PHB#%x, option=%d\n",
420 __func__, hose->global_number, option);
423 * During the reset deassert time, we needn't care
424 * the reset scope because the firmware does nothing
425 * for fundamental or hot reset during deassert phase.
427 if (option == EEH_RESET_FUNDAMENTAL)
428 rc = opal_pci_reset(phb->opal_id,
429 OPAL_PCI_FUNDAMENTAL_RESET,
431 else if (option == EEH_RESET_HOT)
432 rc = opal_pci_reset(phb->opal_id,
435 else if (option == EEH_RESET_DEACTIVATE)
436 rc = opal_pci_reset(phb->opal_id,
438 OPAL_DEASSERT_RESET);
442 /* Poll state of the PHB until the request is done */
443 rc = ioda_eeh_phb_poll(phb);
445 if (rc != OPAL_SUCCESS)
451 static int ioda_eeh_bridge_reset(struct pci_controller *hose,
452 struct pci_dev *dev, int option)
456 pr_debug("%s: Reset device %04x:%02x:%02x.%01x with option %d\n",
457 __func__, hose->global_number, dev->bus->number,
458 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), option);
461 case EEH_RESET_FUNDAMENTAL:
463 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
464 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
465 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
467 case EEH_RESET_DEACTIVATE:
468 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
469 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
470 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
478 * ioda_eeh_reset - Reset the indicated PE
480 * @option: reset option
482 * Do reset on the indicated PE. For PCI bus sensitive PE,
483 * we need to reset the parent p2p bridge. The PHB has to
484 * be reinitialized if the p2p bridge is root bridge. For
485 * PCI device sensitive PE, we will try to reset the device
486 * through FLR. For now, we don't have OPAL APIs to do HARD
487 * reset yet, so all reset would be SOFT (HOT) reset.
489 static int ioda_eeh_reset(struct eeh_pe *pe, int option)
491 struct pci_controller *hose = pe->phb;
492 struct eeh_dev *edev;
497 * Anyway, we have to clear the problematic state for the
498 * corresponding PE. However, we needn't do it if the PE
499 * is PHB associated. That means the PHB is having fatal
500 * errors and it needs reset. Further more, the AIB interface
501 * isn't reliable any more.
503 if (!(pe->type & EEH_PE_PHB) &&
504 (option == EEH_RESET_HOT ||
505 option == EEH_RESET_FUNDAMENTAL)) {
506 ret = ioda_eeh_pe_clear(pe);
512 * The rules applied to reset, either fundamental or hot reset:
514 * We always reset the direct upstream bridge of the PE. If the
515 * direct upstream bridge isn't root bridge, we always take hot
516 * reset no matter what option (fundamental or hot) is. Otherwise,
517 * we should do the reset according to the required option.
519 if (pe->type & EEH_PE_PHB) {
520 ret = ioda_eeh_phb_reset(hose, option);
522 if (pe->type & EEH_PE_DEVICE) {
524 * If it's device PE, we didn't refer to the parent
525 * PCI bus yet. So we have to figure it out indirectly.
527 edev = list_first_entry(&pe->edevs,
528 struct eeh_dev, list);
529 dev = eeh_dev_to_pci_dev(edev);
530 dev = dev->bus->self;
533 * If it's bus PE, the parent PCI bus is already there
534 * and just pick it up.
540 * Do reset based on the fact that the direct upstream bridge
541 * is root bridge (port) or not.
543 if (dev->bus->number == 0)
544 ret = ioda_eeh_root_reset(hose, option);
546 ret = ioda_eeh_bridge_reset(hose, dev, option);
553 * ioda_eeh_get_log - Retrieve error log
555 * @severity: Severity level of the log
556 * @drv_log: buffer to store the log
557 * @len: space of the log buffer
559 * The function is used to retrieve error log from P7IOC.
561 static int ioda_eeh_get_log(struct eeh_pe *pe, int severity,
562 char *drv_log, unsigned long len)
566 struct pci_controller *hose = pe->phb;
567 struct pnv_phb *phb = hose->private_data;
569 spin_lock_irqsave(&phb->lock, flags);
571 ret = opal_pci_get_phb_diag_data2(phb->opal_id,
572 phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE);
574 spin_unlock_irqrestore(&phb->lock, flags);
575 pr_warning("%s: Can't get log for PHB#%x-PE#%x (%lld)\n",
576 __func__, hose->global_number, pe->addr, ret);
580 /* The PHB diag-data is always indicative */
581 pnv_pci_dump_phb_diag_data(hose, phb->diag.blob);
583 spin_unlock_irqrestore(&phb->lock, flags);
589 * ioda_eeh_configure_bridge - Configure the PCI bridges for the indicated PE
592 * For particular PE, it might have included PCI bridges. In order
593 * to make the PE work properly, those PCI bridges should be configured
594 * correctly. However, we need do nothing on P7IOC since the reset
595 * function will do everything that should be covered by the function.
597 static int ioda_eeh_configure_bridge(struct eeh_pe *pe)
602 static void ioda_eeh_hub_diag_common(struct OpalIoP7IOCErrorData *data)
605 pr_info(" GEM XFIR: %016llx\n", data->gemXfir);
606 pr_info(" GEM RFIR: %016llx\n", data->gemRfir);
607 pr_info(" GEM RIRQFIR: %016llx\n", data->gemRirqfir);
608 pr_info(" GEM Mask: %016llx\n", data->gemMask);
609 pr_info(" GEM RWOF: %016llx\n", data->gemRwof);
612 pr_info(" LEM FIR: %016llx\n", data->lemFir);
613 pr_info(" LEM Error Mask: %016llx\n", data->lemErrMask);
614 pr_info(" LEM Action 0: %016llx\n", data->lemAction0);
615 pr_info(" LEM Action 1: %016llx\n", data->lemAction1);
616 pr_info(" LEM WOF: %016llx\n", data->lemWof);
619 static void ioda_eeh_hub_diag(struct pci_controller *hose)
621 struct pnv_phb *phb = hose->private_data;
622 struct OpalIoP7IOCErrorData *data = &phb->diag.hub_diag;
625 rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data));
626 if (rc != OPAL_SUCCESS) {
627 pr_warning("%s: Failed to get HUB#%llx diag-data (%ld)\n",
628 __func__, phb->hub_id, rc);
632 switch (data->type) {
633 case OPAL_P7IOC_DIAG_TYPE_RGC:
634 pr_info("P7IOC diag-data for RGC\n\n");
635 ioda_eeh_hub_diag_common(data);
636 pr_info(" RGC Status: %016llx\n", data->rgc.rgcStatus);
637 pr_info(" RGC LDCP: %016llx\n", data->rgc.rgcLdcp);
639 case OPAL_P7IOC_DIAG_TYPE_BI:
640 pr_info("P7IOC diag-data for BI %s\n\n",
641 data->bi.biDownbound ? "Downbound" : "Upbound");
642 ioda_eeh_hub_diag_common(data);
643 pr_info(" BI LDCP 0: %016llx\n", data->bi.biLdcp0);
644 pr_info(" BI LDCP 1: %016llx\n", data->bi.biLdcp1);
645 pr_info(" BI LDCP 2: %016llx\n", data->bi.biLdcp2);
646 pr_info(" BI Fence Status: %016llx\n", data->bi.biFenceStatus);
648 case OPAL_P7IOC_DIAG_TYPE_CI:
649 pr_info("P7IOC diag-data for CI Port %d\\nn",
651 ioda_eeh_hub_diag_common(data);
652 pr_info(" CI Port Status: %016llx\n", data->ci.ciPortStatus);
653 pr_info(" CI Port LDCP: %016llx\n", data->ci.ciPortLdcp);
655 case OPAL_P7IOC_DIAG_TYPE_MISC:
656 pr_info("P7IOC diag-data for MISC\n\n");
657 ioda_eeh_hub_diag_common(data);
659 case OPAL_P7IOC_DIAG_TYPE_I2C:
660 pr_info("P7IOC diag-data for I2C\n\n");
661 ioda_eeh_hub_diag_common(data);
664 pr_warning("%s: Invalid type of HUB#%llx diag-data (%d)\n",
665 __func__, phb->hub_id, data->type);
669 static void ioda_eeh_phb_diag(struct pci_controller *hose)
671 struct pnv_phb *phb = hose->private_data;
674 rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
675 PNV_PCI_DIAG_BUF_SIZE);
676 if (rc != OPAL_SUCCESS) {
677 pr_warning("%s: Failed to get diag-data for PHB#%x (%ld)\n",
678 __func__, hose->global_number, rc);
682 pnv_pci_dump_phb_diag_data(hose, phb->diag.blob);
685 static int ioda_eeh_get_phb_pe(struct pci_controller *hose,
688 struct eeh_pe *phb_pe;
690 phb_pe = eeh_phb_pe_get(hose);
692 pr_warning("%s Can't find PE for PHB#%d\n",
693 __func__, hose->global_number);
701 static int ioda_eeh_get_pe(struct pci_controller *hose,
702 u16 pe_no, struct eeh_pe **pe)
704 struct eeh_pe *phb_pe, *dev_pe;
707 /* Find the PHB PE */
708 if (ioda_eeh_get_phb_pe(hose, &phb_pe))
711 /* Find the PE according to PE# */
712 memset(&dev, 0, sizeof(struct eeh_dev));
714 dev.pe_config_addr = pe_no;
715 dev_pe = eeh_pe_get(&dev);
716 if (!dev_pe) return -EEXIST;
723 * ioda_eeh_next_error - Retrieve next error for EEH core to handle
724 * @pe: The affected PE
726 * The function is expected to be called by EEH core while it gets
727 * special EEH event (without binding PE). The function calls to
728 * OPAL APIs for next error to handle. The informational error is
729 * handled internally by platform. However, the dead IOC, dead PHB,
730 * fenced PHB and frozen PE should be handled by EEH core eventually.
732 static int ioda_eeh_next_error(struct eeh_pe **pe)
734 struct pci_controller *hose;
737 u16 err_type, severity;
739 int ret = EEH_NEXT_ERR_NONE;
742 * While running here, it's safe to purge the event queue.
743 * And we should keep the cached OPAL notifier event sychronized
744 * between the kernel and firmware.
746 eeh_remove_event(NULL);
747 opal_notifier_update_evt(OPAL_EVENT_PCI_ERROR, 0x0ul);
749 list_for_each_entry(hose, &hose_list, list_node) {
751 * If the subordinate PCI buses of the PHB has been
752 * removed, we needn't take care of it any more.
754 phb = hose->private_data;
755 if (phb->eeh_state & PNV_EEH_STATE_REMOVED)
758 rc = opal_pci_next_error(phb->opal_id,
759 &frozen_pe_no, &err_type, &severity);
761 /* If OPAL API returns error, we needn't proceed */
762 if (rc != OPAL_SUCCESS) {
763 pr_devel("%s: Invalid return value on "
764 "PHB#%x (0x%lx) from opal_pci_next_error",
765 __func__, hose->global_number, rc);
769 /* If the PHB doesn't have error, stop processing */
770 if (err_type == OPAL_EEH_NO_ERROR ||
771 severity == OPAL_EEH_SEV_NO_ERROR) {
772 pr_devel("%s: No error found on PHB#%x\n",
773 __func__, hose->global_number);
778 * Processing the error. We're expecting the error with
779 * highest priority reported upon multiple errors on the
782 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n",
783 __func__, err_type, severity,
784 frozen_pe_no, hose->global_number);
786 case OPAL_EEH_IOC_ERROR:
787 if (severity == OPAL_EEH_SEV_IOC_DEAD) {
788 list_for_each_entry(hose, &hose_list,
790 phb = hose->private_data;
791 phb->eeh_state |= PNV_EEH_STATE_REMOVED;
794 pr_err("EEH: dead IOC detected\n");
795 ret = EEH_NEXT_ERR_DEAD_IOC;
796 } else if (severity == OPAL_EEH_SEV_INF) {
797 pr_info("EEH: IOC informative error "
799 ioda_eeh_hub_diag(hose);
800 ret = EEH_NEXT_ERR_NONE;
804 case OPAL_EEH_PHB_ERROR:
805 if (severity == OPAL_EEH_SEV_PHB_DEAD) {
806 if (ioda_eeh_get_phb_pe(hose, pe))
809 pr_err("EEH: dead PHB#%x detected\n",
810 hose->global_number);
811 phb->eeh_state |= PNV_EEH_STATE_REMOVED;
812 ret = EEH_NEXT_ERR_DEAD_PHB;
813 } else if (severity == OPAL_EEH_SEV_PHB_FENCED) {
814 if (ioda_eeh_get_phb_pe(hose, pe))
817 pr_err("EEH: fenced PHB#%x detected\n",
818 hose->global_number);
819 ret = EEH_NEXT_ERR_FENCED_PHB;
820 } else if (severity == OPAL_EEH_SEV_INF) {
821 pr_info("EEH: PHB#%x informative error "
823 hose->global_number);
824 ioda_eeh_phb_diag(hose);
825 ret = EEH_NEXT_ERR_NONE;
829 case OPAL_EEH_PE_ERROR:
831 * If we can't find the corresponding PE, the
832 * PEEV / PEST would be messy. So we force an
833 * fenced PHB so that it can be recovered.
835 if (ioda_eeh_get_pe(hose, frozen_pe_no, pe)) {
836 if (!ioda_eeh_get_phb_pe(hose, pe)) {
837 pr_err("EEH: Escalated fenced PHB#%x "
838 "detected for PE#%llx\n",
841 ret = EEH_NEXT_ERR_FENCED_PHB;
843 ret = EEH_NEXT_ERR_NONE;
846 pr_err("EEH: Frozen PE#%x on PHB#%x detected\n",
847 (*pe)->addr, (*pe)->phb->global_number);
848 ret = EEH_NEXT_ERR_FROZEN_PE;
853 pr_warn("%s: Unexpected error type %d\n",
858 * If we have no errors on the specific PHB or only
859 * informative error there, we continue poking it.
860 * Otherwise, we need actions to be taken by upper
863 if (ret > EEH_NEXT_ERR_INF)
870 struct pnv_eeh_ops ioda_eeh_ops = {
871 .post_init = ioda_eeh_post_init,
872 .set_option = ioda_eeh_set_option,
873 .get_state = ioda_eeh_get_state,
874 .reset = ioda_eeh_reset,
875 .get_log = ioda_eeh_get_log,
876 .configure_bridge = ioda_eeh_configure_bridge,
877 .next_error = ioda_eeh_next_error