arch/powerpc/platforms/powernv/pci-ioda.c

   1 /*
   2  * Support PCI/PCIe on PowerNV platforms
   3  *
   4  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #undef DEBUG
  13
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/crash_dump.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/delay.h>
  19 #include <linux/string.h>
  20 #include <linux/init.h>
  21 #include <linux/bootmem.h>
  22 #include <linux/irq.h>
  23 #include <linux/io.h>
  24 #include <linux/msi.h>
  25 #include <linux/memblock.h>
  26 #include <linux/iommu.h>
  27 #include <linux/rculist.h>
  28 #include <linux/sizes.h>
  29
  30 #include <asm/sections.h>
  31 #include <asm/io.h>
  32 #include <asm/prom.h>
  33 #include <asm/pci-bridge.h>
  34 #include <asm/machdep.h>
  35 #include <asm/msi_bitmap.h>
  36 #include <asm/ppc-pci.h>
  37 #include <asm/opal.h>
  38 #include <asm/iommu.h>
  39 #include <asm/tce.h>
  40 #include <asm/xics.h>
  41 #include <asm/debug.h>
  42 #include <asm/firmware.h>
  43 #include <asm/pnv-pci.h>
  44 #include <asm/mmzone.h>
  45
  46 #include <misc/cxl-base.h>
  47
  48 #include "powernv.h"
  49 #include "pci.h"
  50
  51 #define PNV_IODA1_M64_NUM       16      /* Number of M64 BARs   */
  52 #define PNV_IODA1_M64_SEGS      8       /* Segments per M64 BAR */
  53 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
  54
  55 #define POWERNV_IOMMU_DEFAULT_LEVELS    1
  56 #define POWERNV_IOMMU_MAX_LEVELS        5
  57
  58 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU" };
  59 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
  60
  61 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
  62                             const char *fmt, ...)
  63 {
  64         struct va_format vaf;
  65         va_list args;
  66         char pfix[32];
  67
  68         va_start(args, fmt);
  69
  70         vaf.fmt = fmt;
  71         vaf.va = &args;
  72
  73         if (pe->flags & PNV_IODA_PE_DEV)
  74                 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
  75         else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
  76                 sprintf(pfix, "%04x:%02x     ",
  77                         pci_domain_nr(pe->pbus), pe->pbus->number);
  78 #ifdef CONFIG_PCI_IOV
  79         else if (pe->flags & PNV_IODA_PE_VF)
  80                 sprintf(pfix, "%04x:%02x:%2x.%d",
  81                         pci_domain_nr(pe->parent_dev->bus),
  82                         (pe->rid & 0xff00) >> 8,
  83                         PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
  84 #endif /* CONFIG_PCI_IOV*/
  85
  86         printk("%spci %s: [PE# %.3d] %pV",
  87                level, pfix, pe->pe_number, &vaf);
  88
  89         va_end(args);
  90 }
  91
  92 static bool pnv_iommu_bypass_disabled __read_mostly;
  93
  94 static int __init iommu_setup(char *str)
  95 {
  96         if (!str)
  97                 return -EINVAL;
  98
  99         while (*str) {
 100                 if (!strncmp(str, "nobypass", 8)) {
 101                         pnv_iommu_bypass_disabled = true;
 102                         pr_info("PowerNV: IOMMU bypass window disabled.\n");
 103                         break;
 104                 }
 105                 str += strcspn(str, ",");
 106                 if (*str == ',')
 107                         str++;
 108         }
 109
 110         return 0;
 111 }
 112 early_param("iommu", iommu_setup);
 113
 114 static inline bool pnv_pci_is_mem_pref_64(unsigned long flags)
 115 {
 116         return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) ==
 117                 (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH));
 118 }
 119
 120 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
 121 {
 122         phb->ioda.pe_array[pe_no].phb = phb;
 123         phb->ioda.pe_array[pe_no].pe_number = pe_no;
 124
 125         return &phb->ioda.pe_array[pe_no];
 126 }
 127
 128 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
 129 {
 130         if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
 131                 pr_warn("%s: Invalid PE %d on PHB#%x\n",
 132                         __func__, pe_no, phb->hose->global_number);
 133                 return;
 134         }
 135
 136         if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
 137                 pr_debug("%s: PE %d was reserved on PHB#%x\n",
 138                          __func__, pe_no, phb->hose->global_number);
 139
 140         pnv_ioda_init_pe(phb, pe_no);
 141 }
 142
 143 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
 144 {
 145         unsigned long pe = phb->ioda.total_pe_num - 1;
 146
 147         for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
 148                 if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
 149                         return pnv_ioda_init_pe(phb, pe);
 150         }
 151
 152         return NULL;
 153 }
 154
 155 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
 156 {
 157         struct pnv_phb *phb = pe->phb;
 158
 159         WARN_ON(pe->pdev);
 160
 161         memset(pe, 0, sizeof(struct pnv_ioda_pe));
 162         clear_bit(pe->pe_number, phb->ioda.pe_alloc);
 163 }
 164
 165 /* The default M64 BAR is shared by all PEs */
 166 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
 167 {
 168         const char *desc;
 169         struct resource *r;
 170         s64 rc;
 171
 172         /* Configure the default M64 BAR */
 173         rc = opal_pci_set_phb_mem_window(phb->opal_id,
 174                                          OPAL_M64_WINDOW_TYPE,
 175                                          phb->ioda.m64_bar_idx,
 176                                          phb->ioda.m64_base,
 177                                          0, /* unused */
 178                                          phb->ioda.m64_size);
 179         if (rc != OPAL_SUCCESS) {
 180                 desc = "configuring";
 181                 goto fail;
 182         }
 183
 184         /* Enable the default M64 BAR */
 185         rc = opal_pci_phb_mmio_enable(phb->opal_id,
 186                                       OPAL_M64_WINDOW_TYPE,
 187                                       phb->ioda.m64_bar_idx,
 188                                       OPAL_ENABLE_M64_SPLIT);
 189         if (rc != OPAL_SUCCESS) {
 190                 desc = "enabling";
 191                 goto fail;
 192         }
 193
 194         /* Mark the M64 BAR assigned */
 195         set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc);
 196
 197         /*
 198          * Exclude the segments for reserved and root bus PE, which
 199          * are first or last two PEs.
 200          */
 201         r = &phb->hose->mem_resources[1];
 202         if (phb->ioda.reserved_pe_idx == 0)
 203                 r->start += (2 * phb->ioda.m64_segsize);
 204         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
 205                 r->end -= (2 * phb->ioda.m64_segsize);
 206         else
 207                 pr_warn("  Cannot strip M64 segment for reserved PE#%d\n",
 208                         phb->ioda.reserved_pe_idx);
 209
 210         return 0;
 211
 212 fail:
 213         pr_warn("  Failure %lld %s M64 BAR#%d\n",
 214                 rc, desc, phb->ioda.m64_bar_idx);
 215         opal_pci_phb_mmio_enable(phb->opal_id,
 216                                  OPAL_M64_WINDOW_TYPE,
 217                                  phb->ioda.m64_bar_idx,
 218                                  OPAL_DISABLE_M64);
 219         return -EIO;
 220 }
 221
 222 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
 223                                          unsigned long *pe_bitmap)
 224 {
 225         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
 226         struct pnv_phb *phb = hose->private_data;
 227         struct resource *r;
 228         resource_size_t base, sgsz, start, end;
 229         int segno, i;
 230
 231         base = phb->ioda.m64_base;
 232         sgsz = phb->ioda.m64_segsize;
 233         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 234                 r = &pdev->resource[i];
 235                 if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags))
 236                         continue;
 237
 238                 start = _ALIGN_DOWN(r->start - base, sgsz);
 239                 end = _ALIGN_UP(r->end - base, sgsz);
 240                 for (segno = start / sgsz; segno < end / sgsz; segno++) {
 241                         if (pe_bitmap)
 242                                 set_bit(segno, pe_bitmap);
 243                         else
 244                                 pnv_ioda_reserve_pe(phb, segno);
 245                 }
 246         }
 247 }
 248
 249 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
 250 {
 251         struct resource *r;
 252         int index;
 253
 254         /*
 255          * There are 16 M64 BARs, each of which has 8 segments. So
 256          * there are as many M64 segments as the maximum number of
 257          * PEs, which is 128.
 258          */
 259         for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
 260                 unsigned long base, segsz = phb->ioda.m64_segsize;
 261                 int64_t rc;
 262
 263                 base = phb->ioda.m64_base +
 264                        index * PNV_IODA1_M64_SEGS * segsz;
 265                 rc = opal_pci_set_phb_mem_window(phb->opal_id,
 266                                 OPAL_M64_WINDOW_TYPE, index, base, 0,
 267                                 PNV_IODA1_M64_SEGS * segsz);
 268                 if (rc != OPAL_SUCCESS) {
 269                         pr_warn("  Error %lld setting M64 PHB#%d-BAR#%d\n",
 270                                 rc, phb->hose->global_number, index);
 271                         goto fail;
 272                 }
 273
 274                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
 275                                 OPAL_M64_WINDOW_TYPE, index,
 276                                 OPAL_ENABLE_M64_SPLIT);
 277                 if (rc != OPAL_SUCCESS) {
 278                         pr_warn("  Error %lld enabling M64 PHB#%d-BAR#%d\n",
 279                                 rc, phb->hose->global_number, index);
 280                         goto fail;
 281                 }
 282         }
 283
 284         /*
 285          * Exclude the segments for reserved and root bus PE, which
 286          * are first or last two PEs.
 287          */
 288         r = &phb->hose->mem_resources[1];
 289         if (phb->ioda.reserved_pe_idx == 0)
 290                 r->start += (2 * phb->ioda.m64_segsize);
 291         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
 292                 r->end -= (2 * phb->ioda.m64_segsize);
 293         else
 294                 WARN(1, "Wrong reserved PE#%d on PHB#%d\n",
 295                      phb->ioda.reserved_pe_idx, phb->hose->global_number);
 296
 297         return 0;
 298
 299 fail:
 300         for ( ; index >= 0; index--)
 301                 opal_pci_phb_mmio_enable(phb->opal_id,
 302                         OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
 303
 304         return -EIO;
 305 }
 306
 307 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
 308                                     unsigned long *pe_bitmap,
 309                                     bool all)
 310 {
 311         struct pci_dev *pdev;
 312
 313         list_for_each_entry(pdev, &bus->devices, bus_list) {
 314                 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
 315
 316                 if (all && pdev->subordinate)
 317                         pnv_ioda_reserve_m64_pe(pdev->subordinate,
 318                                                 pe_bitmap, all);
 319         }
 320 }
 321
 322 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
 323 {
 324         struct pci_controller *hose = pci_bus_to_host(bus);
 325         struct pnv_phb *phb = hose->private_data;
 326         struct pnv_ioda_pe *master_pe, *pe;
 327         unsigned long size, *pe_alloc;
 328         int i;
 329
 330         /* Root bus shouldn't use M64 */
 331         if (pci_is_root_bus(bus))
 332                 return NULL;
 333
 334         /* Allocate bitmap */
 335         size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
 336         pe_alloc = kzalloc(size, GFP_KERNEL);
 337         if (!pe_alloc) {
 338                 pr_warn("%s: Out of memory !\n",
 339                         __func__);
 340                 return NULL;
 341         }
 342
 343         /* Figure out reserved PE numbers by the PE */
 344         pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
 345
 346         /*
 347          * the current bus might not own M64 window and that's all
 348          * contributed by its child buses. For the case, we needn't
 349          * pick M64 dependent PE#.
 350          */
 351         if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
 352                 kfree(pe_alloc);
 353                 return NULL;
 354         }
 355
 356         /*
 357          * Figure out the master PE and put all slave PEs to master
 358          * PE's list to form compound PE.
 359          */
 360         master_pe = NULL;
 361         i = -1;
 362         while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
 363                 phb->ioda.total_pe_num) {
 364                 pe = &phb->ioda.pe_array[i];
 365
 366                 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
 367                 if (!master_pe) {
 368                         pe->flags |= PNV_IODA_PE_MASTER;
 369                         INIT_LIST_HEAD(&pe->slaves);
 370                         master_pe = pe;
 371                 } else {
 372                         pe->flags |= PNV_IODA_PE_SLAVE;
 373                         pe->master = master_pe;
 374                         list_add_tail(&pe->list, &master_pe->slaves);
 375                 }
 376
 377                 /*
 378                  * P7IOC supports M64DT, which helps mapping M64 segment
 379                  * to one particular PE#. However, PHB3 has fixed mapping
 380                  * between M64 segment and PE#. In order to have same logic
 381                  * for P7IOC and PHB3, we enforce fixed mapping between M64
 382                  * segment and PE# on P7IOC.
 383                  */
 384                 if (phb->type == PNV_PHB_IODA1) {
 385                         int64_t rc;
 386
 387                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
 388                                         pe->pe_number, OPAL_M64_WINDOW_TYPE,
 389                                         pe->pe_number / PNV_IODA1_M64_SEGS,
 390                                         pe->pe_number % PNV_IODA1_M64_SEGS);
 391                         if (rc != OPAL_SUCCESS)
 392                                 pr_warn("%s: Error %lld mapping M64 for PHB#%d-PE#%d\n",
 393                                         __func__, rc, phb->hose->global_number,
 394                                         pe->pe_number);
 395                 }
 396         }
 397
 398         kfree(pe_alloc);
 399         return master_pe;
 400 }
 401
 402 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
 403 {
 404         struct pci_controller *hose = phb->hose;
 405         struct device_node *dn = hose->dn;
 406         struct resource *res;
 407         const u32 *r;
 408         u64 pci_addr;
 409
 410         if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
 411                 pr_info("  Not support M64 window\n");
 412                 return;
 413         }
 414
 415         if (!firmware_has_feature(FW_FEATURE_OPAL)) {
 416                 pr_info("  Firmware too old to support M64 window\n");
 417                 return;
 418         }
 419
 420         r = of_get_property(dn, "ibm,opal-m64-window", NULL);
 421         if (!r) {
 422                 pr_info("  No <ibm,opal-m64-window> on %s\n",
 423                         dn->full_name);
 424                 return;
 425         }
 426
 427         res = &hose->mem_resources[1];
 428         res->name = dn->full_name;
 429         res->start = of_translate_address(dn, r + 2);
 430         res->end = res->start + of_read_number(r + 4, 2) - 1;
 431         res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
 432         pci_addr = of_read_number(r, 2);
 433         hose->mem_offset[1] = res->start - pci_addr;
 434
 435         phb->ioda.m64_size = resource_size(res);
 436         phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
 437         phb->ioda.m64_base = pci_addr;
 438
 439         pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n",
 440                         res->start, res->end, pci_addr);
 441
 442         /* Use last M64 BAR to cover M64 window */
 443         phb->ioda.m64_bar_idx = 15;
 444         if (phb->type == PNV_PHB_IODA1)
 445                 phb->init_m64 = pnv_ioda1_init_m64;
 446         else
 447                 phb->init_m64 = pnv_ioda2_init_m64;
 448         phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe;
 449         phb->pick_m64_pe = pnv_ioda_pick_m64_pe;
 450 }
 451
 452 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
 453 {
 454         struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
 455         struct pnv_ioda_pe *slave;
 456         s64 rc;
 457
 458         /* Fetch master PE */
 459         if (pe->flags & PNV_IODA_PE_SLAVE) {
 460                 pe = pe->master;
 461                 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
 462                         return;
 463
 464                 pe_no = pe->pe_number;
 465         }
 466
 467         /* Freeze master PE */
 468         rc = opal_pci_eeh_freeze_set(phb->opal_id,
 469                                      pe_no,
 470                                      OPAL_EEH_ACTION_SET_FREEZE_ALL);
 471         if (rc != OPAL_SUCCESS) {
 472                 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 473                         __func__, rc, phb->hose->global_number, pe_no);
 474                 return;
 475         }
 476
 477         /* Freeze slave PEs */
 478         if (!(pe->flags & PNV_IODA_PE_MASTER))
 479                 return;
 480
 481         list_for_each_entry(slave, &pe->slaves, list) {
 482                 rc = opal_pci_eeh_freeze_set(phb->opal_id,
 483                                              slave->pe_number,
 484                                              OPAL_EEH_ACTION_SET_FREEZE_ALL);
 485                 if (rc != OPAL_SUCCESS)
 486                         pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 487                                 __func__, rc, phb->hose->global_number,
 488                                 slave->pe_number);
 489         }
 490 }
 491
 492 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
 493 {
 494         struct pnv_ioda_pe *pe, *slave;
 495         s64 rc;
 496
 497         /* Find master PE */
 498         pe = &phb->ioda.pe_array[pe_no];
 499         if (pe->flags & PNV_IODA_PE_SLAVE) {
 500                 pe = pe->master;
 501                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 502                 pe_no = pe->pe_number;
 503         }
 504
 505         /* Clear frozen state for master PE */
 506         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
 507         if (rc != OPAL_SUCCESS) {
 508                 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 509                         __func__, rc, opt, phb->hose->global_number, pe_no);
 510                 return -EIO;
 511         }
 512
 513         if (!(pe->flags & PNV_IODA_PE_MASTER))
 514                 return 0;
 515
 516         /* Clear frozen state for slave PEs */
 517         list_for_each_entry(slave, &pe->slaves, list) {
 518                 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
 519                                              slave->pe_number,
 520                                              opt);
 521                 if (rc != OPAL_SUCCESS) {
 522                         pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 523                                 __func__, rc, opt, phb->hose->global_number,
 524                                 slave->pe_number);
 525                         return -EIO;
 526                 }
 527         }
 528
 529         return 0;
 530 }
 531
 532 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
 533 {
 534         struct pnv_ioda_pe *slave, *pe;
 535         u8 fstate, state;
 536         __be16 pcierr;
 537         s64 rc;
 538
 539         /* Sanity check on PE number */
 540         if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
 541                 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
 542
 543         /*
 544          * Fetch the master PE and the PE instance might be
 545          * not initialized yet.
 546          */
 547         pe = &phb->ioda.pe_array[pe_no];
 548         if (pe->flags & PNV_IODA_PE_SLAVE) {
 549                 pe = pe->master;
 550                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 551                 pe_no = pe->pe_number;
 552         }
 553
 554         /* Check the master PE */
 555         rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 556                                         &state, &pcierr, NULL);
 557         if (rc != OPAL_SUCCESS) {
 558                 pr_warn("%s: Failure %lld getting "
 559                         "PHB#%x-PE#%x state\n",
 560                         __func__, rc,
 561                         phb->hose->global_number, pe_no);
 562                 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 563         }
 564
 565         /* Check the slave PE */
 566         if (!(pe->flags & PNV_IODA_PE_MASTER))
 567                 return state;
 568
 569         list_for_each_entry(slave, &pe->slaves, list) {
 570                 rc = opal_pci_eeh_freeze_status(phb->opal_id,
 571                                                 slave->pe_number,
 572                                                 &fstate,
 573                                                 &pcierr,
 574                                                 NULL);
 575                 if (rc != OPAL_SUCCESS) {
 576                         pr_warn("%s: Failure %lld getting "
 577                                 "PHB#%x-PE#%x state\n",
 578                                 __func__, rc,
 579                                 phb->hose->global_number, slave->pe_number);
 580                         return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 581                 }
 582
 583                 /*
 584                  * Override the result based on the ascending
 585                  * priority.
 586                  */
 587                 if (fstate > state)
 588                         state = fstate;
 589         }
 590
 591         return state;
 592 }
 593
 594 /* Currently those 2 are only used when MSIs are enabled, this will change
 595  * but in the meantime, we need to protect them to avoid warnings
 596  */
 597 #ifdef CONFIG_PCI_MSI
 598 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
 599 {
 600         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 601         struct pnv_phb *phb = hose->private_data;
 602         struct pci_dn *pdn = pci_get_pdn(dev);
 603
 604         if (!pdn)
 605                 return NULL;
 606         if (pdn->pe_number == IODA_INVALID_PE)
 607                 return NULL;
 608         return &phb->ioda.pe_array[pdn->pe_number];
 609 }
 610 #endif /* CONFIG_PCI_MSI */
 611
 612 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
 613                                   struct pnv_ioda_pe *parent,
 614                                   struct pnv_ioda_pe *child,
 615                                   bool is_add)
 616 {
 617         const char *desc = is_add ? "adding" : "removing";
 618         uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
 619                               OPAL_REMOVE_PE_FROM_DOMAIN;
 620         struct pnv_ioda_pe *slave;
 621         long rc;
 622
 623         /* Parent PE affects child PE */
 624         rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 625                                 child->pe_number, op);
 626         if (rc != OPAL_SUCCESS) {
 627                 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
 628                         rc, desc);
 629                 return -ENXIO;
 630         }
 631
 632         if (!(child->flags & PNV_IODA_PE_MASTER))
 633                 return 0;
 634
 635         /* Compound case: parent PE affects slave PEs */
 636         list_for_each_entry(slave, &child->slaves, list) {
 637                 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 638                                         slave->pe_number, op);
 639                 if (rc != OPAL_SUCCESS) {
 640                         pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
 641                                 rc, desc);
 642                         return -ENXIO;
 643                 }
 644         }
 645
 646         return 0;
 647 }
 648
 649 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
 650                               struct pnv_ioda_pe *pe,
 651                               bool is_add)
 652 {
 653         struct pnv_ioda_pe *slave;
 654         struct pci_dev *pdev = NULL;
 655         int ret;
 656
 657         /*
 658          * Clear PE frozen state. If it's master PE, we need
 659          * clear slave PE frozen state as well.
 660          */
 661         if (is_add) {
 662                 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 663                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 664                 if (pe->flags & PNV_IODA_PE_MASTER) {
 665                         list_for_each_entry(slave, &pe->slaves, list)
 666                                 opal_pci_eeh_freeze_clear(phb->opal_id,
 667                                                           slave->pe_number,
 668                                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 669                 }
 670         }
 671
 672         /*
 673          * Associate PE in PELT. We need add the PE into the
 674          * corresponding PELT-V as well. Otherwise, the error
 675          * originated from the PE might contribute to other
 676          * PEs.
 677          */
 678         ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
 679         if (ret)
 680                 return ret;
 681
 682         /* For compound PEs, any one affects all of them */
 683         if (pe->flags & PNV_IODA_PE_MASTER) {
 684                 list_for_each_entry(slave, &pe->slaves, list) {
 685                         ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
 686                         if (ret)
 687                                 return ret;
 688                 }
 689         }
 690
 691         if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
 692                 pdev = pe->pbus->self;
 693         else if (pe->flags & PNV_IODA_PE_DEV)
 694                 pdev = pe->pdev->bus->self;
 695 #ifdef CONFIG_PCI_IOV
 696         else if (pe->flags & PNV_IODA_PE_VF)
 697                 pdev = pe->parent_dev;
 698 #endif /* CONFIG_PCI_IOV */
 699         while (pdev) {
 700                 struct pci_dn *pdn = pci_get_pdn(pdev);
 701                 struct pnv_ioda_pe *parent;
 702
 703                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 704                         parent = &phb->ioda.pe_array[pdn->pe_number];
 705                         ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
 706                         if (ret)
 707                                 return ret;
 708                 }
 709
 710                 pdev = pdev->bus->self;
 711         }
 712
 713         return 0;
 714 }
 715
 716 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 717 {
 718         struct pci_dev *parent;
 719         uint8_t bcomp, dcomp, fcomp;
 720         int64_t rc;
 721         long rid_end, rid;
 722
 723         /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
 724         if (pe->pbus) {
 725                 int count;
 726
 727                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 728                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 729                 parent = pe->pbus->self;
 730                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 731                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 732                 else
 733                         count = 1;
 734
 735                 switch(count) {
 736                 case  1: bcomp = OpalPciBusAll;         break;
 737                 case  2: bcomp = OpalPciBus7Bits;       break;
 738                 case  4: bcomp = OpalPciBus6Bits;       break;
 739                 case  8: bcomp = OpalPciBus5Bits;       break;
 740                 case 16: bcomp = OpalPciBus4Bits;       break;
 741                 case 32: bcomp = OpalPciBus3Bits;       break;
 742                 default:
 743                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 744                                 count);
 745                         /* Do an exact match only */
 746                         bcomp = OpalPciBusAll;
 747                 }
 748                 rid_end = pe->rid + (count << 8);
 749         } else {
 750 #ifdef CONFIG_PCI_IOV
 751                 if (pe->flags & PNV_IODA_PE_VF)
 752                         parent = pe->parent_dev;
 753                 else
 754 #endif
 755                         parent = pe->pdev->bus->self;
 756                 bcomp = OpalPciBusAll;
 757                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 758                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 759                 rid_end = pe->rid + 1;
 760         }
 761
 762         /* Clear the reverse map */
 763         for (rid = pe->rid; rid < rid_end; rid++)
 764                 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
 765
 766         /* Release from all parents PELT-V */
 767         while (parent) {
 768                 struct pci_dn *pdn = pci_get_pdn(parent);
 769                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 770                         rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
 771                                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 772                         /* XXX What to do in case of error ? */
 773                 }
 774                 parent = parent->bus->self;
 775         }
 776
 777         opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 778                                   OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 779
 780         /* Disassociate PE in PELT */
 781         rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
 782                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 783         if (rc)
 784                 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
 785         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 786                              bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
 787         if (rc)
 788                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 789
 790         pe->pbus = NULL;
 791         pe->pdev = NULL;
 792 #ifdef CONFIG_PCI_IOV
 793         pe->parent_dev = NULL;
 794 #endif
 795
 796         return 0;
 797 }
 798
 799 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 800 {
 801         struct pci_dev *parent;
 802         uint8_t bcomp, dcomp, fcomp;
 803         long rc, rid_end, rid;
 804
 805         /* Bus validation ? */
 806         if (pe->pbus) {
 807                 int count;
 808
 809                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 810                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 811                 parent = pe->pbus->self;
 812                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 813                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 814                 else
 815                         count = 1;
 816
 817                 switch(count) {
 818                 case  1: bcomp = OpalPciBusAll;         break;
 819                 case  2: bcomp = OpalPciBus7Bits;       break;
 820                 case  4: bcomp = OpalPciBus6Bits;       break;
 821                 case  8: bcomp = OpalPciBus5Bits;       break;
 822                 case 16: bcomp = OpalPciBus4Bits;       break;
 823                 case 32: bcomp = OpalPciBus3Bits;       break;
 824                 default:
 825                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 826                                 count);
 827                         /* Do an exact match only */
 828                         bcomp = OpalPciBusAll;
 829                 }
 830                 rid_end = pe->rid + (count << 8);
 831         } else {
 832 #ifdef CONFIG_PCI_IOV
 833                 if (pe->flags & PNV_IODA_PE_VF)
 834                         parent = pe->parent_dev;
 835                 else
 836 #endif /* CONFIG_PCI_IOV */
 837                         parent = pe->pdev->bus->self;
 838                 bcomp = OpalPciBusAll;
 839                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 840                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 841                 rid_end = pe->rid + 1;
 842         }
 843
 844         /*
 845          * Associate PE in PELT. We need add the PE into the
 846          * corresponding PELT-V as well. Otherwise, the error
 847          * originated from the PE might contribute to other
 848          * PEs.
 849          */
 850         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 851                              bcomp, dcomp, fcomp, OPAL_MAP_PE);
 852         if (rc) {
 853                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 854                 return -ENXIO;
 855         }
 856
 857         /*
 858          * Configure PELTV. NPUs don't have a PELTV table so skip
 859          * configuration on them.
 860          */
 861         if (phb->type != PNV_PHB_NPU)
 862                 pnv_ioda_set_peltv(phb, pe, true);
 863
 864         /* Setup reverse map */
 865         for (rid = pe->rid; rid < rid_end; rid++)
 866                 phb->ioda.pe_rmap[rid] = pe->pe_number;
 867
 868         /* Setup one MVTs on IODA1 */
 869         if (phb->type != PNV_PHB_IODA1) {
 870                 pe->mve_number = 0;
 871                 goto out;
 872         }
 873
 874         pe->mve_number = pe->pe_number;
 875         rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
 876         if (rc != OPAL_SUCCESS) {
 877                 pe_err(pe, "OPAL error %ld setting up MVE %d\n",
 878                        rc, pe->mve_number);
 879                 pe->mve_number = -1;
 880         } else {
 881                 rc = opal_pci_set_mve_enable(phb->opal_id,
 882                                              pe->mve_number, OPAL_ENABLE_MVE);
 883                 if (rc) {
 884                         pe_err(pe, "OPAL error %ld enabling MVE %d\n",
 885                                rc, pe->mve_number);
 886                         pe->mve_number = -1;
 887                 }
 888         }
 889
 890 out:
 891         return 0;
 892 }
 893
 894 #ifdef CONFIG_PCI_IOV
 895 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
 896 {
 897         struct pci_dn *pdn = pci_get_pdn(dev);
 898         int i;
 899         struct resource *res, res2;
 900         resource_size_t size;
 901         u16 num_vfs;
 902
 903         if (!dev->is_physfn)
 904                 return -EINVAL;
 905
 906         /*
 907          * "offset" is in VFs.  The M64 windows are sized so that when they
 908          * are segmented, each segment is the same size as the IOV BAR.
 909          * Each segment is in a separate PE, and the high order bits of the
 910          * address are the PE number.  Therefore, each VF's BAR is in a
 911          * separate PE, and changing the IOV BAR start address changes the
 912          * range of PEs the VFs are in.
 913          */
 914         num_vfs = pdn->num_vfs;
 915         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
 916                 res = &dev->resource[i + PCI_IOV_RESOURCES];
 917                 if (!res->flags || !res->parent)
 918                         continue;
 919
 920                 /*
 921                  * The actual IOV BAR range is determined by the start address
 922                  * and the actual size for num_vfs VFs BAR.  This check is to
 923                  * make sure that after shifting, the range will not overlap
 924                  * with another device.
 925                  */
 926                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
 927                 res2.flags = res->flags;
 928                 res2.start = res->start + (size * offset);
 929                 res2.end = res2.start + (size * num_vfs) - 1;
 930
 931                 if (res2.end > res->end) {
 932                         dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
 933                                 i, &res2, res, num_vfs, offset);
 934                         return -EBUSY;
 935                 }
 936         }
 937
 938         /*
 939          * After doing so, there would be a "hole" in the /proc/iomem when
 940          * offset is a positive value. It looks like the device return some
 941          * mmio back to the system, which actually no one could use it.
 942          */
 943         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
 944                 res = &dev->resource[i + PCI_IOV_RESOURCES];
 945                 if (!res->flags || !res->parent)
 946                         continue;
 947
 948                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
 949                 res2 = *res;
 950                 res->start += size * offset;
 951
 952                 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
 953                          i, &res2, res, (offset > 0) ? "En" : "Dis",
 954                          num_vfs, offset);
 955                 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
 956         }
 957         return 0;
 958 }
 959 #endif /* CONFIG_PCI_IOV */
 960
 961 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
 962 {
 963         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 964         struct pnv_phb *phb = hose->private_data;
 965         struct pci_dn *pdn = pci_get_pdn(dev);
 966         struct pnv_ioda_pe *pe;
 967
 968         if (!pdn) {
 969                 pr_err("%s: Device tree node not associated properly\n",
 970                            pci_name(dev));
 971                 return NULL;
 972         }
 973         if (pdn->pe_number != IODA_INVALID_PE)
 974                 return NULL;
 975
 976         pe = pnv_ioda_alloc_pe(phb);
 977         if (!pe) {
 978                 pr_warning("%s: Not enough PE# available, disabling device\n",
 979                            pci_name(dev));
 980                 return NULL;
 981         }
 982
 983         /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
 984          * pointer in the PE data structure, both should be destroyed at the
 985          * same time. However, this needs to be looked at more closely again
 986          * once we actually start removing things (Hotplug, SR-IOV, ...)
 987          *
 988          * At some point we want to remove the PDN completely anyways
 989          */
 990         pci_dev_get(dev);
 991         pdn->pcidev = dev;
 992         pdn->pe_number = pe->pe_number;
 993         pe->flags = PNV_IODA_PE_DEV;
 994         pe->pdev = dev;
 995         pe->pbus = NULL;
 996         pe->mve_number = -1;
 997         pe->rid = dev->bus->number << 8 | pdn->devfn;
 998
 999         pe_info(pe, "Associated device to PE\n");
1000
1001         if (pnv_ioda_configure_pe(phb, pe)) {
1002                 /* XXX What do we do here ? */
1003                 pnv_ioda_free_pe(pe);
1004                 pdn->pe_number = IODA_INVALID_PE;
1005                 pe->pdev = NULL;
1006                 pci_dev_put(dev);
1007                 return NULL;
1008         }
1009
1010         /* Put PE to the list */
1011         list_add_tail(&pe->list, &phb->ioda.pe_list);
1012
1013         return pe;
1014 }
1015
1016 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1017 {
1018         struct pci_dev *dev;
1019
1020         list_for_each_entry(dev, &bus->devices, bus_list) {
1021                 struct pci_dn *pdn = pci_get_pdn(dev);
1022
1023                 if (pdn == NULL) {
1024                         pr_warn("%s: No device node associated with device !\n",
1025                                 pci_name(dev));
1026                         continue;
1027                 }
1028
1029                 /*
1030                  * In partial hotplug case, the PCI device might be still
1031                  * associated with the PE and needn't attach it to the PE
1032                  * again.
1033                  */
1034                 if (pdn->pe_number != IODA_INVALID_PE)
1035                         continue;
1036
1037                 pe->device_count++;
1038                 pdn->pcidev = dev;
1039                 pdn->pe_number = pe->pe_number;
1040                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1041                         pnv_ioda_setup_same_PE(dev->subordinate, pe);
1042         }
1043 }
1044
1045 /*
1046  * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1047  * single PCI bus. Another one that contains the primary PCI bus and its
1048  * subordinate PCI devices and buses. The second type of PE is normally
1049  * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1050  */
1051 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1052 {
1053         struct pci_controller *hose = pci_bus_to_host(bus);
1054         struct pnv_phb *phb = hose->private_data;
1055         struct pnv_ioda_pe *pe = NULL;
1056         unsigned int pe_num;
1057
1058         /*
1059          * In partial hotplug case, the PE instance might be still alive.
1060          * We should reuse it instead of allocating a new one.
1061          */
1062         pe_num = phb->ioda.pe_rmap[bus->number << 8];
1063         if (pe_num != IODA_INVALID_PE) {
1064                 pe = &phb->ioda.pe_array[pe_num];
1065                 pnv_ioda_setup_same_PE(bus, pe);
1066                 return NULL;
1067         }
1068
1069         /* PE number for root bus should have been reserved */
1070         if (pci_is_root_bus(bus) &&
1071             phb->ioda.root_pe_idx != IODA_INVALID_PE)
1072                 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1073
1074         /* Check if PE is determined by M64 */
1075         if (!pe && phb->pick_m64_pe)
1076                 pe = phb->pick_m64_pe(bus, all);
1077
1078         /* The PE number isn't pinned by M64 */
1079         if (!pe)
1080                 pe = pnv_ioda_alloc_pe(phb);
1081
1082         if (!pe) {
1083                 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1084                         __func__, pci_domain_nr(bus), bus->number);
1085                 return NULL;
1086         }
1087
1088         pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1089         pe->pbus = bus;
1090         pe->pdev = NULL;
1091         pe->mve_number = -1;
1092         pe->rid = bus->busn_res.start << 8;
1093
1094         if (all)
1095                 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
1096                         bus->busn_res.start, bus->busn_res.end, pe->pe_number);
1097         else
1098                 pe_info(pe, "Secondary bus %d associated with PE#%d\n",
1099                         bus->busn_res.start, pe->pe_number);
1100
1101         if (pnv_ioda_configure_pe(phb, pe)) {
1102                 /* XXX What do we do here ? */
1103                 pnv_ioda_free_pe(pe);
1104                 pe->pbus = NULL;
1105                 return NULL;
1106         }
1107
1108         /* Associate it with all child devices */
1109         pnv_ioda_setup_same_PE(bus, pe);
1110
1111         /* Put PE to the list */
1112         list_add_tail(&pe->list, &phb->ioda.pe_list);
1113
1114         return pe;
1115 }
1116
1117 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1118 {
1119         int pe_num, found_pe = false, rc;
1120         long rid;
1121         struct pnv_ioda_pe *pe;
1122         struct pci_dev *gpu_pdev;
1123         struct pci_dn *npu_pdn;
1124         struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1125         struct pnv_phb *phb = hose->private_data;
1126
1127         /*
1128          * Due to a hardware errata PE#0 on the NPU is reserved for
1129          * error handling. This means we only have three PEs remaining
1130          * which need to be assigned to four links, implying some
1131          * links must share PEs.
1132          *
1133          * To achieve this we assign PEs such that NPUs linking the
1134          * same GPU get assigned the same PE.
1135          */
1136         gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1137         for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1138                 pe = &phb->ioda.pe_array[pe_num];
1139                 if (!pe->pdev)
1140                         continue;
1141
1142                 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1143                         /*
1144                          * This device has the same peer GPU so should
1145                          * be assigned the same PE as the existing
1146                          * peer NPU.
1147                          */
1148                         dev_info(&npu_pdev->dev,
1149                                 "Associating to existing PE %d\n", pe_num);
1150                         pci_dev_get(npu_pdev);
1151                         npu_pdn = pci_get_pdn(npu_pdev);
1152                         rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1153                         npu_pdn->pcidev = npu_pdev;
1154                         npu_pdn->pe_number = pe_num;
1155                         phb->ioda.pe_rmap[rid] = pe->pe_number;
1156
1157                         /* Map the PE to this link */
1158                         rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1159                                         OpalPciBusAll,
1160                                         OPAL_COMPARE_RID_DEVICE_NUMBER,
1161                                         OPAL_COMPARE_RID_FUNCTION_NUMBER,
1162                                         OPAL_MAP_PE);
1163                         WARN_ON(rc != OPAL_SUCCESS);
1164                         found_pe = true;
1165                         break;
1166                 }
1167         }
1168
1169         if (!found_pe)
1170                 /*
1171                  * Could not find an existing PE so allocate a new
1172                  * one.
1173                  */
1174                 return pnv_ioda_setup_dev_PE(npu_pdev);
1175         else
1176                 return pe;
1177 }
1178
1179 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1180 {
1181         struct pci_dev *pdev;
1182
1183         list_for_each_entry(pdev, &bus->devices, bus_list)
1184                 pnv_ioda_setup_npu_PE(pdev);
1185 }
1186
1187 static void pnv_pci_ioda_setup_PEs(void)
1188 {
1189         struct pci_controller *hose, *tmp;
1190         struct pnv_phb *phb;
1191
1192         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1193                 phb = hose->private_data;
1194                 if (phb->type == PNV_PHB_NPU) {
1195                         /* PE#0 is needed for error reporting */
1196                         pnv_ioda_reserve_pe(phb, 0);
1197                         pnv_ioda_setup_npu_PEs(hose->bus);
1198                 }
1199         }
1200 }
1201
1202 #ifdef CONFIG_PCI_IOV
1203 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1204 {
1205         struct pci_bus        *bus;
1206         struct pci_controller *hose;
1207         struct pnv_phb        *phb;
1208         struct pci_dn         *pdn;
1209         int                    i, j;
1210         int                    m64_bars;
1211
1212         bus = pdev->bus;
1213         hose = pci_bus_to_host(bus);
1214         phb = hose->private_data;
1215         pdn = pci_get_pdn(pdev);
1216
1217         if (pdn->m64_single_mode)
1218                 m64_bars = num_vfs;
1219         else
1220                 m64_bars = 1;
1221
1222         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1223                 for (j = 0; j < m64_bars; j++) {
1224                         if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1225                                 continue;
1226                         opal_pci_phb_mmio_enable(phb->opal_id,
1227                                 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1228                         clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1229                         pdn->m64_map[j][i] = IODA_INVALID_M64;
1230                 }
1231
1232         kfree(pdn->m64_map);
1233         return 0;
1234 }
1235
1236 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1237 {
1238         struct pci_bus        *bus;
1239         struct pci_controller *hose;
1240         struct pnv_phb        *phb;
1241         struct pci_dn         *pdn;
1242         unsigned int           win;
1243         struct resource       *res;
1244         int                    i, j;
1245         int64_t                rc;
1246         int                    total_vfs;
1247         resource_size_t        size, start;
1248         int                    pe_num;
1249         int                    m64_bars;
1250
1251         bus = pdev->bus;
1252         hose = pci_bus_to_host(bus);
1253         phb = hose->private_data;
1254         pdn = pci_get_pdn(pdev);
1255         total_vfs = pci_sriov_get_totalvfs(pdev);
1256
1257         if (pdn->m64_single_mode)
1258                 m64_bars = num_vfs;
1259         else
1260                 m64_bars = 1;
1261
1262         pdn->m64_map = kmalloc(sizeof(*pdn->m64_map) * m64_bars, GFP_KERNEL);
1263         if (!pdn->m64_map)
1264                 return -ENOMEM;
1265         /* Initialize the m64_map to IODA_INVALID_M64 */
1266         for (i = 0; i < m64_bars ; i++)
1267                 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1268                         pdn->m64_map[i][j] = IODA_INVALID_M64;
1269
1270
1271         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1272                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1273                 if (!res->flags || !res->parent)
1274                         continue;
1275
1276                 for (j = 0; j < m64_bars; j++) {
1277                         do {
1278                                 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1279                                                 phb->ioda.m64_bar_idx + 1, 0);
1280
1281                                 if (win >= phb->ioda.m64_bar_idx + 1)
1282                                         goto m64_failed;
1283                         } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1284
1285                         pdn->m64_map[j][i] = win;
1286
1287                         if (pdn->m64_single_mode) {
1288                                 size = pci_iov_resource_size(pdev,
1289                                                         PCI_IOV_RESOURCES + i);
1290                                 start = res->start + size * j;
1291                         } else {
1292                                 size = resource_size(res);
1293                                 start = res->start;
1294                         }
1295
1296                         /* Map the M64 here */
1297                         if (pdn->m64_single_mode) {
1298                                 pe_num = pdn->pe_num_map[j];
1299                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1300                                                 pe_num, OPAL_M64_WINDOW_TYPE,
1301                                                 pdn->m64_map[j][i], 0);
1302                         }
1303
1304                         rc = opal_pci_set_phb_mem_window(phb->opal_id,
1305                                                  OPAL_M64_WINDOW_TYPE,
1306                                                  pdn->m64_map[j][i],
1307                                                  start,
1308                                                  0, /* unused */
1309                                                  size);
1310
1311
1312                         if (rc != OPAL_SUCCESS) {
1313                                 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1314                                         win, rc);
1315                                 goto m64_failed;
1316                         }
1317
1318                         if (pdn->m64_single_mode)
1319                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1320                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1321                         else
1322                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1323                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1324
1325                         if (rc != OPAL_SUCCESS) {
1326                                 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1327                                         win, rc);
1328                                 goto m64_failed;
1329                         }
1330                 }
1331         }
1332         return 0;
1333
1334 m64_failed:
1335         pnv_pci_vf_release_m64(pdev, num_vfs);
1336         return -EBUSY;
1337 }
1338
1339 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1340                 int num);
1341 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
1342
1343 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1344 {
1345         struct iommu_table    *tbl;
1346         int64_t               rc;
1347
1348         tbl = pe->table_group.tables[0];
1349         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1350         if (rc)
1351                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1352
1353         pnv_pci_ioda2_set_bypass(pe, false);
1354         if (pe->table_group.group) {
1355                 iommu_group_put(pe->table_group.group);
1356                 BUG_ON(pe->table_group.group);
1357         }
1358         pnv_pci_ioda2_table_free_pages(tbl);
1359         iommu_free_table(tbl, of_node_full_name(dev->dev.of_node));
1360 }
1361
1362 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1363 {
1364         struct pci_bus        *bus;
1365         struct pci_controller *hose;
1366         struct pnv_phb        *phb;
1367         struct pnv_ioda_pe    *pe, *pe_n;
1368         struct pci_dn         *pdn;
1369
1370         bus = pdev->bus;
1371         hose = pci_bus_to_host(bus);
1372         phb = hose->private_data;
1373         pdn = pci_get_pdn(pdev);
1374
1375         if (!pdev->is_physfn)
1376                 return;
1377
1378         list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1379                 if (pe->parent_dev != pdev)
1380                         continue;
1381
1382                 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1383
1384                 /* Remove from list */
1385                 mutex_lock(&phb->ioda.pe_list_mutex);
1386                 list_del(&pe->list);
1387                 mutex_unlock(&phb->ioda.pe_list_mutex);
1388
1389                 pnv_ioda_deconfigure_pe(phb, pe);
1390
1391                 pnv_ioda_free_pe(pe);
1392         }
1393 }
1394
1395 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1396 {
1397         struct pci_bus        *bus;
1398         struct pci_controller *hose;
1399         struct pnv_phb        *phb;
1400         struct pnv_ioda_pe    *pe;
1401         struct pci_dn         *pdn;
1402         struct pci_sriov      *iov;
1403         u16                    num_vfs, i;
1404
1405         bus = pdev->bus;
1406         hose = pci_bus_to_host(bus);
1407         phb = hose->private_data;
1408         pdn = pci_get_pdn(pdev);
1409         iov = pdev->sriov;
1410         num_vfs = pdn->num_vfs;
1411
1412         /* Release VF PEs */
1413         pnv_ioda_release_vf_PE(pdev);
1414
1415         if (phb->type == PNV_PHB_IODA2) {
1416                 if (!pdn->m64_single_mode)
1417                         pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1418
1419                 /* Release M64 windows */
1420                 pnv_pci_vf_release_m64(pdev, num_vfs);
1421
1422                 /* Release PE numbers */
1423                 if (pdn->m64_single_mode) {
1424                         for (i = 0; i < num_vfs; i++) {
1425                                 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1426                                         continue;
1427
1428                                 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1429                                 pnv_ioda_free_pe(pe);
1430                         }
1431                 } else
1432                         bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1433                 /* Releasing pe_num_map */
1434                 kfree(pdn->pe_num_map);
1435         }
1436 }
1437
1438 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1439                                        struct pnv_ioda_pe *pe);
1440 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1441 {
1442         struct pci_bus        *bus;
1443         struct pci_controller *hose;
1444         struct pnv_phb        *phb;
1445         struct pnv_ioda_pe    *pe;
1446         int                    pe_num;
1447         u16                    vf_index;
1448         struct pci_dn         *pdn;
1449
1450         bus = pdev->bus;
1451         hose = pci_bus_to_host(bus);
1452         phb = hose->private_data;
1453         pdn = pci_get_pdn(pdev);
1454
1455         if (!pdev->is_physfn)
1456                 return;
1457
1458         /* Reserve PE for each VF */
1459         for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1460                 if (pdn->m64_single_mode)
1461                         pe_num = pdn->pe_num_map[vf_index];
1462                 else
1463                         pe_num = *pdn->pe_num_map + vf_index;
1464
1465                 pe = &phb->ioda.pe_array[pe_num];
1466                 pe->pe_number = pe_num;
1467                 pe->phb = phb;
1468                 pe->flags = PNV_IODA_PE_VF;
1469                 pe->pbus = NULL;
1470                 pe->parent_dev = pdev;
1471                 pe->mve_number = -1;
1472                 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1473                            pci_iov_virtfn_devfn(pdev, vf_index);
1474
1475                 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n",
1476                         hose->global_number, pdev->bus->number,
1477                         PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1478                         PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1479
1480                 if (pnv_ioda_configure_pe(phb, pe)) {
1481                         /* XXX What do we do here ? */
1482                         pnv_ioda_free_pe(pe);
1483                         pe->pdev = NULL;
1484                         continue;
1485                 }
1486
1487                 /* Put PE to the list */
1488                 mutex_lock(&phb->ioda.pe_list_mutex);
1489                 list_add_tail(&pe->list, &phb->ioda.pe_list);
1490                 mutex_unlock(&phb->ioda.pe_list_mutex);
1491
1492                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1493         }
1494 }
1495
1496 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1497 {
1498         struct pci_bus        *bus;
1499         struct pci_controller *hose;
1500         struct pnv_phb        *phb;
1501         struct pnv_ioda_pe    *pe;
1502         struct pci_dn         *pdn;
1503         int                    ret;
1504         u16                    i;
1505
1506         bus = pdev->bus;
1507         hose = pci_bus_to_host(bus);
1508         phb = hose->private_data;
1509         pdn = pci_get_pdn(pdev);
1510
1511         if (phb->type == PNV_PHB_IODA2) {
1512                 if (!pdn->vfs_expanded) {
1513                         dev_info(&pdev->dev, "don't support this SRIOV device"
1514                                 " with non 64bit-prefetchable IOV BAR\n");
1515                         return -ENOSPC;
1516                 }
1517
1518                 /*
1519                  * When M64 BARs functions in Single PE mode, the number of VFs
1520                  * could be enabled must be less than the number of M64 BARs.
1521                  */
1522                 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1523                         dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1524                         return -EBUSY;
1525                 }
1526
1527                 /* Allocating pe_num_map */
1528                 if (pdn->m64_single_mode)
1529                         pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map) * num_vfs,
1530                                         GFP_KERNEL);
1531                 else
1532                         pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1533
1534                 if (!pdn->pe_num_map)
1535                         return -ENOMEM;
1536
1537                 if (pdn->m64_single_mode)
1538                         for (i = 0; i < num_vfs; i++)
1539                                 pdn->pe_num_map[i] = IODA_INVALID_PE;
1540
1541                 /* Calculate available PE for required VFs */
1542                 if (pdn->m64_single_mode) {
1543                         for (i = 0; i < num_vfs; i++) {
1544                                 pe = pnv_ioda_alloc_pe(phb);
1545                                 if (!pe) {
1546                                         ret = -EBUSY;
1547                                         goto m64_failed;
1548                                 }
1549
1550                                 pdn->pe_num_map[i] = pe->pe_number;
1551                         }
1552                 } else {
1553                         mutex_lock(&phb->ioda.pe_alloc_mutex);
1554                         *pdn->pe_num_map = bitmap_find_next_zero_area(
1555                                 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1556                                 0, num_vfs, 0);
1557                         if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1558                                 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1559                                 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1560                                 kfree(pdn->pe_num_map);
1561                                 return -EBUSY;
1562                         }
1563                         bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1564                         mutex_unlock(&phb->ioda.pe_alloc_mutex);
1565                 }
1566                 pdn->num_vfs = num_vfs;
1567
1568                 /* Assign M64 window accordingly */
1569                 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1570                 if (ret) {
1571                         dev_info(&pdev->dev, "Not enough M64 window resources\n");
1572                         goto m64_failed;
1573                 }
1574
1575                 /*
1576                  * When using one M64 BAR to map one IOV BAR, we need to shift
1577                  * the IOV BAR according to the PE# allocated to the VFs.
1578                  * Otherwise, the PE# for the VF will conflict with others.
1579                  */
1580                 if (!pdn->m64_single_mode) {
1581                         ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1582                         if (ret)
1583                                 goto m64_failed;
1584                 }
1585         }
1586
1587         /* Setup VF PEs */
1588         pnv_ioda_setup_vf_PE(pdev, num_vfs);
1589
1590         return 0;
1591
1592 m64_failed:
1593         if (pdn->m64_single_mode) {
1594                 for (i = 0; i < num_vfs; i++) {
1595                         if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1596                                 continue;
1597
1598                         pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1599                         pnv_ioda_free_pe(pe);
1600                 }
1601         } else
1602                 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1603
1604         /* Releasing pe_num_map */
1605         kfree(pdn->pe_num_map);
1606
1607         return ret;
1608 }
1609
1610 int pcibios_sriov_disable(struct pci_dev *pdev)
1611 {
1612         pnv_pci_sriov_disable(pdev);
1613
1614         /* Release PCI data */
1615         remove_dev_pci_data(pdev);
1616         return 0;
1617 }
1618
1619 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1620 {
1621         /* Allocate PCI data */
1622         add_dev_pci_data(pdev);
1623
1624         return pnv_pci_sriov_enable(pdev, num_vfs);
1625 }
1626 #endif /* CONFIG_PCI_IOV */
1627
1628 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1629 {
1630         struct pci_dn *pdn = pci_get_pdn(pdev);
1631         struct pnv_ioda_pe *pe;
1632
1633         /*
1634          * The function can be called while the PE#
1635          * hasn't been assigned. Do nothing for the
1636          * case.
1637          */
1638         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1639                 return;
1640
1641         pe = &phb->ioda.pe_array[pdn->pe_number];
1642         WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1643         set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1644         set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1645         /*
1646          * Note: iommu_add_device() will fail here as
1647          * for physical PE: the device is already added by now;
1648          * for virtual PE: sysfs entries are not ready yet and
1649          * tce_iommu_bus_notifier will add the device to a group later.
1650          */
1651 }
1652
1653 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1654 {
1655         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1656         struct pnv_phb *phb = hose->private_data;
1657         struct pci_dn *pdn = pci_get_pdn(pdev);
1658         struct pnv_ioda_pe *pe;
1659         uint64_t top;
1660         bool bypass = false;
1661
1662         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1663                 return -ENODEV;;
1664
1665         pe = &phb->ioda.pe_array[pdn->pe_number];
1666         if (pe->tce_bypass_enabled) {
1667                 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1668                 bypass = (dma_mask >= top);
1669         }
1670
1671         if (bypass) {
1672                 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1673                 set_dma_ops(&pdev->dev, &dma_direct_ops);
1674         } else {
1675                 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1676                 set_dma_ops(&pdev->dev, &dma_iommu_ops);
1677         }
1678         *pdev->dev.dma_mask = dma_mask;
1679
1680         /* Update peer npu devices */
1681         pnv_npu_try_dma_set_bypass(pdev, bypass);
1682
1683         return 0;
1684 }
1685
1686 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1687 {
1688         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1689         struct pnv_phb *phb = hose->private_data;
1690         struct pci_dn *pdn = pci_get_pdn(pdev);
1691         struct pnv_ioda_pe *pe;
1692         u64 end, mask;
1693
1694         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1695                 return 0;
1696
1697         pe = &phb->ioda.pe_array[pdn->pe_number];
1698         if (!pe->tce_bypass_enabled)
1699                 return __dma_get_required_mask(&pdev->dev);
1700
1701
1702         end = pe->tce_bypass_base + memblock_end_of_DRAM();
1703         mask = 1ULL << (fls64(end) - 1);
1704         mask += mask - 1;
1705
1706         return mask;
1707 }
1708
1709 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1710                                    struct pci_bus *bus)
1711 {
1712         struct pci_dev *dev;
1713
1714         list_for_each_entry(dev, &bus->devices, bus_list) {
1715                 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1716                 set_dma_offset(&dev->dev, pe->tce_bypass_base);
1717                 iommu_add_device(&dev->dev);
1718
1719                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1720                         pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1721         }
1722 }
1723
1724 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1725                                                      bool real_mode)
1726 {
1727         return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1728                 (phb->regs + 0x210);
1729 }
1730
1731 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
1732                 unsigned long index, unsigned long npages, bool rm)
1733 {
1734         struct iommu_table_group_link *tgl = list_first_entry_or_null(
1735                         &tbl->it_group_list, struct iommu_table_group_link,
1736                         next);
1737         struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1738                         struct pnv_ioda_pe, table_group);
1739         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1740         unsigned long start, end, inc;
1741
1742         start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1743         end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1744                         npages - 1);
1745
1746         /* p7ioc-style invalidation, 2 TCEs per write */
1747         start |= (1ull << 63);
1748         end |= (1ull << 63);
1749         inc = 16;
1750         end |= inc - 1; /* round up end to be different than start */
1751
1752         mb(); /* Ensure above stores are visible */
1753         while (start <= end) {
1754                 if (rm)
1755                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
1756                 else
1757                         __raw_writeq(cpu_to_be64(start), invalidate);
1758                 start += inc;
1759         }
1760
1761         /*
1762          * The iommu layer will do another mb() for us on build()
1763          * and we don't care on free()
1764          */
1765 }
1766
1767 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1768                 long npages, unsigned long uaddr,
1769                 enum dma_data_direction direction,
1770                 struct dma_attrs *attrs)
1771 {
1772         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1773                         attrs);
1774
1775         if (!ret)
1776                 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1777
1778         return ret;
1779 }
1780
1781 #ifdef CONFIG_IOMMU_API
1782 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1783                 unsigned long *hpa, enum dma_data_direction *direction)
1784 {
1785         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1786
1787         if (!ret)
1788                 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false);
1789
1790         return ret;
1791 }
1792 #endif
1793
1794 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1795                 long npages)
1796 {
1797         pnv_tce_free(tbl, index, npages);
1798
1799         pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1800 }
1801
1802 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1803         .set = pnv_ioda1_tce_build,
1804 #ifdef CONFIG_IOMMU_API
1805         .exchange = pnv_ioda1_tce_xchg,
1806 #endif
1807         .clear = pnv_ioda1_tce_free,
1808         .get = pnv_tce_get,
1809 };
1810
1811 #define PHB3_TCE_KILL_INVAL_ALL         PPC_BIT(0)
1812 #define PHB3_TCE_KILL_INVAL_PE          PPC_BIT(1)
1813 #define PHB3_TCE_KILL_INVAL_ONE         PPC_BIT(2)
1814
1815 void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
1816 {
1817         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
1818         const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
1819
1820         mb(); /* Ensure previous TCE table stores are visible */
1821         if (rm)
1822                 __raw_rm_writeq(cpu_to_be64(val), invalidate);
1823         else
1824                 __raw_writeq(cpu_to_be64(val), invalidate);
1825 }
1826
1827 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1828 {
1829         /* 01xb - invalidate TCEs that match the specified PE# */
1830         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
1831         unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
1832
1833         mb(); /* Ensure above stores are visible */
1834         __raw_writeq(cpu_to_be64(val), invalidate);
1835 }
1836
1837 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
1838                                         unsigned shift, unsigned long index,
1839                                         unsigned long npages)
1840 {
1841         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
1842         unsigned long start, end, inc;
1843
1844         /* We'll invalidate DMA address in PE scope */
1845         start = PHB3_TCE_KILL_INVAL_ONE;
1846         start |= (pe->pe_number & 0xFF);
1847         end = start;
1848
1849         /* Figure out the start, end and step */
1850         start |= (index << shift);
1851         end |= ((index + npages - 1) << shift);
1852         inc = (0x1ull << shift);
1853         mb();
1854
1855         while (start <= end) {
1856                 if (rm)
1857                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
1858                 else
1859                         __raw_writeq(cpu_to_be64(start), invalidate);
1860                 start += inc;
1861         }
1862 }
1863
1864 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
1865                 unsigned long index, unsigned long npages, bool rm)
1866 {
1867         struct iommu_table_group_link *tgl;
1868
1869         list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) {
1870                 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1871                                 struct pnv_ioda_pe, table_group);
1872                 if (pe->phb->type == PNV_PHB_NPU) {
1873                         /*
1874                          * The NVLink hardware does not support TCE kill
1875                          * per TCE entry so we have to invalidate
1876                          * the entire cache for it.
1877                          */
1878                         pnv_pci_phb3_tce_invalidate_entire(pe->phb, rm);
1879                         continue;
1880                 }
1881                 pnv_pci_phb3_tce_invalidate(pe, rm, tbl->it_page_shift,
1882                                             index, npages);
1883         }
1884 }
1885
1886 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
1887                 long npages, unsigned long uaddr,
1888                 enum dma_data_direction direction,
1889                 struct dma_attrs *attrs)
1890 {
1891         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1892                         attrs);
1893
1894         if (!ret)
1895                 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1896
1897         return ret;
1898 }
1899
1900 #ifdef CONFIG_IOMMU_API
1901 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
1902                 unsigned long *hpa, enum dma_data_direction *direction)
1903 {
1904         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1905
1906         if (!ret)
1907                 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
1908
1909         return ret;
1910 }
1911 #endif
1912
1913 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
1914                 long npages)
1915 {
1916         pnv_tce_free(tbl, index, npages);
1917
1918         pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1919 }
1920
1921 static void pnv_ioda2_table_free(struct iommu_table *tbl)
1922 {
1923         pnv_pci_ioda2_table_free_pages(tbl);
1924         iommu_free_table(tbl, "pnv");
1925 }
1926
1927 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
1928         .set = pnv_ioda2_tce_build,
1929 #ifdef CONFIG_IOMMU_API
1930         .exchange = pnv_ioda2_tce_xchg,
1931 #endif
1932         .clear = pnv_ioda2_tce_free,
1933         .get = pnv_tce_get,
1934         .free = pnv_ioda2_table_free,
1935 };
1936
1937 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
1938 {
1939         unsigned int *weight = (unsigned int *)data;
1940
1941         /* This is quite simplistic. The "base" weight of a device
1942          * is 10. 0 means no DMA is to be accounted for it.
1943          */
1944         if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
1945                 return 0;
1946
1947         if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
1948             dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
1949             dev->class == PCI_CLASS_SERIAL_USB_EHCI)
1950                 *weight += 3;
1951         else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
1952                 *weight += 15;
1953         else
1954                 *weight += 10;
1955
1956         return 0;
1957 }
1958
1959 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
1960 {
1961         unsigned int weight = 0;
1962
1963         /* SRIOV VF has same DMA32 weight as its PF */
1964 #ifdef CONFIG_PCI_IOV
1965         if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
1966                 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
1967                 return weight;
1968         }
1969 #endif
1970
1971         if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
1972                 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
1973         } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
1974                 struct pci_dev *pdev;
1975
1976                 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
1977                         pnv_pci_ioda_dev_dma_weight(pdev, &weight);
1978         } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
1979                 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
1980         }
1981
1982         return weight;
1983 }
1984
1985 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
1986                                        struct pnv_ioda_pe *pe)
1987 {
1988
1989         struct page *tce_mem = NULL;
1990         struct iommu_table *tbl;
1991         unsigned int weight, total_weight = 0;
1992         unsigned int tce32_segsz, base, segs, avail, i;
1993         int64_t rc;
1994         void *addr;
1995
1996         /* XXX FIXME: Handle 64-bit only DMA devices */
1997         /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
1998         /* XXX FIXME: Allocate multi-level tables on PHB3 */
1999         weight = pnv_pci_ioda_pe_dma_weight(pe);
2000         if (!weight)
2001                 return;
2002
2003         pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2004                      &total_weight);
2005         segs = (weight * phb->ioda.dma32_count) / total_weight;
2006         if (!segs)
2007                 segs = 1;
2008
2009         /*
2010          * Allocate contiguous DMA32 segments. We begin with the expected
2011          * number of segments. With one more attempt, the number of DMA32
2012          * segments to be allocated is decreased by one until one segment
2013          * is allocated successfully.
2014          */
2015         do {
2016                 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2017                         for (avail = 0, i = base; i < base + segs; i++) {
2018                                 if (phb->ioda.dma32_segmap[i] ==
2019                                     IODA_INVALID_PE)
2020                                         avail++;
2021                         }
2022
2023                         if (avail == segs)
2024                                 goto found;
2025                 }
2026         } while (--segs);
2027
2028         if (!segs) {
2029                 pe_warn(pe, "No available DMA32 segments\n");
2030                 return;
2031         }
2032
2033 found:
2034         tbl = pnv_pci_table_alloc(phb->hose->node);
2035         iommu_register_group(&pe->table_group, phb->hose->global_number,
2036                         pe->pe_number);
2037         pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2038
2039         /* Grab a 32-bit TCE table */
2040         pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2041                 weight, total_weight, base, segs);
2042         pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2043                 base * PNV_IODA1_DMA32_SEGSIZE,
2044                 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2045
2046         /* XXX Currently, we allocate one big contiguous table for the
2047          * TCEs. We only really need one chunk per 256M of TCE space
2048          * (ie per segment) but that's an optimization for later, it
2049          * requires some added smarts with our get/put_tce implementation
2050          *
2051          * Each TCE page is 4KB in size and each TCE entry occupies 8
2052          * bytes
2053          */
2054         tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2055         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2056                                    get_order(tce32_segsz * segs));
2057         if (!tce_mem) {
2058                 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2059                 goto fail;
2060         }
2061         addr = page_address(tce_mem);
2062         memset(addr, 0, tce32_segsz * segs);
2063
2064         /* Configure HW */
2065         for (i = 0; i < segs; i++) {
2066                 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2067                                               pe->pe_number,
2068                                               base + i, 1,
2069                                               __pa(addr) + tce32_segsz * i,
2070                                               tce32_segsz, IOMMU_PAGE_SIZE_4K);
2071                 if (rc) {
2072                         pe_err(pe, " Failed to configure 32-bit TCE table,"
2073                                " err %ld\n", rc);
2074                         goto fail;
2075                 }
2076         }
2077
2078         /* Setup DMA32 segment mapping */
2079         for (i = base; i < base + segs; i++)
2080                 phb->ioda.dma32_segmap[i] = pe->pe_number;
2081
2082         /* Setup linux iommu table */
2083         pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2084                                   base * PNV_IODA1_DMA32_SEGSIZE,
2085                                   IOMMU_PAGE_SHIFT_4K);
2086
2087         tbl->it_ops = &pnv_ioda1_iommu_ops;
2088         pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2089         pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2090         iommu_init_table(tbl, phb->hose->node);
2091
2092         if (pe->flags & PNV_IODA_PE_DEV) {
2093                 /*
2094                  * Setting table base here only for carrying iommu_group
2095                  * further down to let iommu_add_device() do the job.
2096                  * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2097                  */
2098                 set_iommu_table_base(&pe->pdev->dev, tbl);
2099                 iommu_add_device(&pe->pdev->dev);
2100         } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2101                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2102
2103         return;
2104  fail:
2105         /* XXX Failure: Try to fallback to 64-bit only ? */
2106         if (tce_mem)
2107                 __free_pages(tce_mem, get_order(tce32_segsz * segs));
2108         if (tbl) {
2109                 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2110                 iommu_free_table(tbl, "pnv");
2111         }
2112 }
2113
2114 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2115                 int num, struct iommu_table *tbl)
2116 {
2117         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2118                         table_group);
2119         struct pnv_phb *phb = pe->phb;
2120         int64_t rc;
2121         const unsigned long size = tbl->it_indirect_levels ?
2122                         tbl->it_level_size : tbl->it_size;
2123         const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2124         const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2125
2126         pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
2127                         start_addr, start_addr + win_size - 1,
2128                         IOMMU_PAGE_SIZE(tbl));
2129
2130         /*
2131          * Map TCE table through TVT. The TVE index is the PE number
2132          * shifted by 1 bit for 32-bits DMA space.
2133          */
2134         rc = opal_pci_map_pe_dma_window(phb->opal_id,
2135                         pe->pe_number,
2136                         (pe->pe_number << 1) + num,
2137                         tbl->it_indirect_levels + 1,
2138                         __pa(tbl->it_base),
2139                         size << 3,
2140                         IOMMU_PAGE_SIZE(tbl));
2141         if (rc) {
2142                 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2143                 return rc;
2144         }
2145
2146         pnv_pci_link_table_and_group(phb->hose->node, num,
2147                         tbl, &pe->table_group);
2148         pnv_pci_phb3_tce_invalidate_pe(pe);
2149
2150         return 0;
2151 }
2152
2153 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2154 {
2155         uint16_t window_id = (pe->pe_number << 1 ) + 1;
2156         int64_t rc;
2157
2158         pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2159         if (enable) {
2160                 phys_addr_t top = memblock_end_of_DRAM();
2161
2162                 top = roundup_pow_of_two(top);
2163                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2164                                                      pe->pe_number,
2165                                                      window_id,
2166                                                      pe->tce_bypass_base,
2167                                                      top);
2168         } else {
2169                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2170                                                      pe->pe_number,
2171                                                      window_id,
2172                                                      pe->tce_bypass_base,
2173                                                      0);
2174         }
2175         if (rc)
2176                 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2177         else
2178                 pe->tce_bypass_enabled = enable;
2179 }
2180
2181 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2182                 __u32 page_shift, __u64 window_size, __u32 levels,
2183                 struct iommu_table *tbl);
2184
2185 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2186                 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2187                 struct iommu_table **ptbl)
2188 {
2189         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2190                         table_group);
2191         int nid = pe->phb->hose->node;
2192         __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2193         long ret;
2194         struct iommu_table *tbl;
2195
2196         tbl = pnv_pci_table_alloc(nid);
2197         if (!tbl)
2198                 return -ENOMEM;
2199
2200         ret = pnv_pci_ioda2_table_alloc_pages(nid,
2201                         bus_offset, page_shift, window_size,
2202                         levels, tbl);
2203         if (ret) {
2204                 iommu_free_table(tbl, "pnv");
2205                 return ret;
2206         }
2207
2208         tbl->it_ops = &pnv_ioda2_iommu_ops;
2209
2210         *ptbl = tbl;
2211
2212         return 0;
2213 }
2214
2215 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2216 {
2217         struct iommu_table *tbl = NULL;
2218         long rc;
2219
2220         /*
2221          * crashkernel= specifies the kdump kernel's maximum memory at
2222          * some offset and there is no guaranteed the result is a power
2223          * of 2, which will cause errors later.
2224          */
2225         const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2226
2227         /*
2228          * In memory constrained environments, e.g. kdump kernel, the
2229          * DMA window can be larger than available memory, which will
2230          * cause errors later.
2231          */
2232         const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2233
2234         rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2235                         IOMMU_PAGE_SHIFT_4K,
2236                         window_size,
2237                         POWERNV_IOMMU_DEFAULT_LEVELS, &tbl);
2238         if (rc) {
2239                 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2240                                 rc);
2241                 return rc;
2242         }
2243
2244         iommu_init_table(tbl, pe->phb->hose->node);
2245
2246         rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2247         if (rc) {
2248                 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2249                                 rc);
2250                 pnv_ioda2_table_free(tbl);
2251                 return rc;
2252         }
2253
2254         if (!pnv_iommu_bypass_disabled)
2255                 pnv_pci_ioda2_set_bypass(pe, true);
2256
2257         /*
2258          * Setting table base here only for carrying iommu_group
2259          * further down to let iommu_add_device() do the job.
2260          * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2261          */
2262         if (pe->flags & PNV_IODA_PE_DEV)
2263                 set_iommu_table_base(&pe->pdev->dev, tbl);
2264
2265         return 0;
2266 }
2267
2268 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2269 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2270                 int num)
2271 {
2272         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2273                         table_group);
2274         struct pnv_phb *phb = pe->phb;
2275         long ret;
2276
2277         pe_info(pe, "Removing DMA window #%d\n", num);
2278
2279         ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2280                         (pe->pe_number << 1) + num,
2281                         0/* levels */, 0/* table address */,
2282                         0/* table size */, 0/* page size */);
2283         if (ret)
2284                 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2285         else
2286                 pnv_pci_phb3_tce_invalidate_pe(pe);
2287
2288         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2289
2290         return ret;
2291 }
2292 #endif
2293
2294 #ifdef CONFIG_IOMMU_API
2295 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2296                 __u64 window_size, __u32 levels)
2297 {
2298         unsigned long bytes = 0;
2299         const unsigned window_shift = ilog2(window_size);
2300         unsigned entries_shift = window_shift - page_shift;
2301         unsigned table_shift = entries_shift + 3;
2302         unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2303         unsigned long direct_table_size;
2304
2305         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2306                         (window_size > memory_hotplug_max()) ||
2307                         !is_power_of_2(window_size))
2308                 return 0;
2309
2310         /* Calculate a direct table size from window_size and levels */
2311         entries_shift = (entries_shift + levels - 1) / levels;
2312         table_shift = entries_shift + 3;
2313         table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2314         direct_table_size =  1UL << table_shift;
2315
2316         for ( ; levels; --levels) {
2317                 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2318
2319                 tce_table_size /= direct_table_size;
2320                 tce_table_size <<= 3;
2321                 tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size);
2322         }
2323
2324         return bytes;
2325 }
2326
2327 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2328 {
2329         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2330                                                 table_group);
2331         /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2332         struct iommu_table *tbl = pe->table_group.tables[0];
2333
2334         pnv_pci_ioda2_set_bypass(pe, false);
2335         pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2336         pnv_ioda2_table_free(tbl);
2337 }
2338
2339 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2340 {
2341         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2342                                                 table_group);
2343
2344         pnv_pci_ioda2_setup_default_config(pe);
2345 }
2346
2347 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2348         .get_table_size = pnv_pci_ioda2_get_table_size,
2349         .create_table = pnv_pci_ioda2_create_table,
2350         .set_window = pnv_pci_ioda2_set_window,
2351         .unset_window = pnv_pci_ioda2_unset_window,
2352         .take_ownership = pnv_ioda2_take_ownership,
2353         .release_ownership = pnv_ioda2_release_ownership,
2354 };
2355
2356 static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque)
2357 {
2358         struct pci_controller *hose;
2359         struct pnv_phb *phb;
2360         struct pnv_ioda_pe **ptmppe = opaque;
2361         struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
2362         struct pci_dn *pdn = pci_get_pdn(pdev);
2363
2364         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
2365                 return 0;
2366
2367         hose = pci_bus_to_host(pdev->bus);
2368         phb = hose->private_data;
2369         if (phb->type != PNV_PHB_NPU)
2370                 return 0;
2371
2372         *ptmppe = &phb->ioda.pe_array[pdn->pe_number];
2373
2374         return 1;
2375 }
2376
2377 /*
2378  * This returns PE of associated NPU.
2379  * This assumes that NPU is in the same IOMMU group with GPU and there is
2380  * no other PEs.
2381  */
2382 static struct pnv_ioda_pe *gpe_table_group_to_npe(
2383                 struct iommu_table_group *table_group)
2384 {
2385         struct pnv_ioda_pe *npe = NULL;
2386         int ret = iommu_group_for_each_dev(table_group->group, &npe,
2387                         gpe_table_group_to_npe_cb);
2388
2389         BUG_ON(!ret || !npe);
2390
2391         return npe;
2392 }
2393
2394 static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group,
2395                 int num, struct iommu_table *tbl)
2396 {
2397         long ret = pnv_pci_ioda2_set_window(table_group, num, tbl);
2398
2399         if (ret)
2400                 return ret;
2401
2402         ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl);
2403         if (ret)
2404                 pnv_pci_ioda2_unset_window(table_group, num);
2405
2406         return ret;
2407 }
2408
2409 static long pnv_pci_ioda2_npu_unset_window(
2410                 struct iommu_table_group *table_group,
2411                 int num)
2412 {
2413         long ret = pnv_pci_ioda2_unset_window(table_group, num);
2414
2415         if (ret)
2416                 return ret;
2417
2418         return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num);
2419 }
2420
2421 static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group)
2422 {
2423         /*
2424          * Detach NPU first as pnv_ioda2_take_ownership() will destroy
2425          * the iommu_table if 32bit DMA is enabled.
2426          */
2427         pnv_npu_take_ownership(gpe_table_group_to_npe(table_group));
2428         pnv_ioda2_take_ownership(table_group);
2429 }
2430
2431 static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = {
2432         .get_table_size = pnv_pci_ioda2_get_table_size,
2433         .create_table = pnv_pci_ioda2_create_table,
2434         .set_window = pnv_pci_ioda2_npu_set_window,
2435         .unset_window = pnv_pci_ioda2_npu_unset_window,
2436         .take_ownership = pnv_ioda2_npu_take_ownership,
2437         .release_ownership = pnv_ioda2_release_ownership,
2438 };
2439
2440 static void pnv_pci_ioda_setup_iommu_api(void)
2441 {
2442         struct pci_controller *hose, *tmp;
2443         struct pnv_phb *phb;
2444         struct pnv_ioda_pe *pe, *gpe;
2445
2446         /*
2447          * Now we have all PHBs discovered, time to add NPU devices to
2448          * the corresponding IOMMU groups.
2449          */
2450         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2451                 phb = hose->private_data;
2452
2453                 if (phb->type != PNV_PHB_NPU)
2454                         continue;
2455
2456                 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2457                         gpe = pnv_pci_npu_setup_iommu(pe);
2458                         if (gpe)
2459                                 gpe->table_group.ops = &pnv_pci_ioda2_npu_ops;
2460                 }
2461         }
2462 }
2463 #else /* !CONFIG_IOMMU_API */
2464 static void pnv_pci_ioda_setup_iommu_api(void) { };
2465 #endif
2466
2467 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
2468                 unsigned levels, unsigned long limit,
2469                 unsigned long *current_offset, unsigned long *total_allocated)
2470 {
2471         struct page *tce_mem = NULL;
2472         __be64 *addr, *tmp;
2473         unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
2474         unsigned long allocated = 1UL << (order + PAGE_SHIFT);
2475         unsigned entries = 1UL << (shift - 3);
2476         long i;
2477
2478         tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
2479         if (!tce_mem) {
2480                 pr_err("Failed to allocate a TCE memory, order=%d\n", order);
2481                 return NULL;
2482         }
2483         addr = page_address(tce_mem);
2484         memset(addr, 0, allocated);
2485         *total_allocated += allocated;
2486
2487         --levels;
2488         if (!levels) {
2489                 *current_offset += allocated;
2490                 return addr;
2491         }
2492
2493         for (i = 0; i < entries; ++i) {
2494                 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
2495                                 levels, limit, current_offset, total_allocated);
2496                 if (!tmp)
2497                         break;
2498
2499                 addr[i] = cpu_to_be64(__pa(tmp) |
2500                                 TCE_PCI_READ | TCE_PCI_WRITE);
2501
2502                 if (*current_offset >= limit)
2503                         break;
2504         }
2505
2506         return addr;
2507 }
2508
2509 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2510                 unsigned long size, unsigned level);
2511
2512 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2513                 __u32 page_shift, __u64 window_size, __u32 levels,
2514                 struct iommu_table *tbl)
2515 {
2516         void *addr;
2517         unsigned long offset = 0, level_shift, total_allocated = 0;
2518         const unsigned window_shift = ilog2(window_size);
2519         unsigned entries_shift = window_shift - page_shift;
2520         unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
2521         const unsigned long tce_table_size = 1UL << table_shift;
2522
2523         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
2524                 return -EINVAL;
2525
2526         if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size))
2527                 return -EINVAL;
2528
2529         /* Adjust direct table size from window_size and levels */
2530         entries_shift = (entries_shift + levels - 1) / levels;
2531         level_shift = entries_shift + 3;
2532         level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
2533
2534         /* Allocate TCE table */
2535         addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
2536                         levels, tce_table_size, &offset, &total_allocated);
2537
2538         /* addr==NULL means that the first level allocation failed */
2539         if (!addr)
2540                 return -ENOMEM;
2541
2542         /*
2543          * First level was allocated but some lower level failed as
2544          * we did not allocate as much as we wanted,
2545          * release partially allocated table.
2546          */
2547         if (offset < tce_table_size) {
2548                 pnv_pci_ioda2_table_do_free_pages(addr,
2549                                 1ULL << (level_shift - 3), levels - 1);
2550                 return -ENOMEM;
2551         }
2552
2553         /* Setup linux iommu table */
2554         pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
2555                         page_shift);
2556         tbl->it_level_size = 1ULL << (level_shift - 3);
2557         tbl->it_indirect_levels = levels - 1;
2558         tbl->it_allocated_size = total_allocated;
2559
2560         pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2561                         window_size, tce_table_size, bus_offset);
2562
2563         return 0;
2564 }
2565
2566 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2567                 unsigned long size, unsigned level)
2568 {
2569         const unsigned long addr_ul = (unsigned long) addr &
2570                         ~(TCE_PCI_READ | TCE_PCI_WRITE);
2571
2572         if (level) {
2573                 long i;
2574                 u64 *tmp = (u64 *) addr_ul;
2575
2576                 for (i = 0; i < size; ++i) {
2577                         unsigned long hpa = be64_to_cpu(tmp[i]);
2578
2579                         if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
2580                                 continue;
2581
2582                         pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
2583                                         level - 1);
2584                 }
2585         }
2586
2587         free_pages(addr_ul, get_order(size << 3));
2588 }
2589
2590 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
2591 {
2592         const unsigned long size = tbl->it_indirect_levels ?
2593                         tbl->it_level_size : tbl->it_size;
2594
2595         if (!tbl->it_size)
2596                 return;
2597
2598         pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
2599                         tbl->it_indirect_levels);
2600 }
2601
2602 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2603                                        struct pnv_ioda_pe *pe)
2604 {
2605         int64_t rc;
2606
2607         if (!pnv_pci_ioda_pe_dma_weight(pe))
2608                 return;
2609
2610         /* TVE #1 is selected by PCI address bit 59 */
2611         pe->tce_bypass_base = 1ull << 59;
2612
2613         iommu_register_group(&pe->table_group, phb->hose->global_number,
2614                         pe->pe_number);
2615
2616         /* The PE will reserve all possible 32-bits space */
2617         pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2618                 phb->ioda.m32_pci_base);
2619
2620         /* Setup linux iommu table */
2621         pe->table_group.tce32_start = 0;
2622         pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2623         pe->table_group.max_dynamic_windows_supported =
2624                         IOMMU_TABLE_GROUP_MAX_TABLES;
2625         pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2626         pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
2627 #ifdef CONFIG_IOMMU_API
2628         pe->table_group.ops = &pnv_pci_ioda2_ops;
2629 #endif
2630
2631         rc = pnv_pci_ioda2_setup_default_config(pe);
2632         if (rc)
2633                 return;
2634
2635         if (pe->flags & PNV_IODA_PE_DEV)
2636                 iommu_add_device(&pe->pdev->dev);
2637         else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2638                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2639 }
2640
2641 #ifdef CONFIG_PCI_MSI
2642 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2643 {
2644         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2645         struct irq_chip *chip = irq_data_get_irq_chip(d);
2646         struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2647                                            ioda.irq_chip);
2648         int64_t rc;
2649
2650         rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);
2651         WARN_ON_ONCE(rc);
2652
2653         icp_native_eoi(d);
2654 }
2655
2656
2657 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2658 {
2659         struct irq_data *idata;
2660         struct irq_chip *ichip;
2661
2662         /* The MSI EOI OPAL call is only needed on PHB3 */
2663         if (phb->model != PNV_PHB_MODEL_PHB3)
2664                 return;
2665
2666         if (!phb->ioda.irq_chip_init) {
2667                 /*
2668                  * First time we setup an MSI IRQ, we need to setup the
2669                  * corresponding IRQ chip to route correctly.
2670                  */
2671                 idata = irq_get_irq_data(virq);
2672                 ichip = irq_data_get_irq_chip(idata);
2673                 phb->ioda.irq_chip_init = 1;
2674                 phb->ioda.irq_chip = *ichip;
2675                 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2676         }
2677         irq_set_chip(virq, &phb->ioda.irq_chip);
2678 }
2679
2680 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2681                                   unsigned int hwirq, unsigned int virq,
2682                                   unsigned int is_64, struct msi_msg *msg)
2683 {
2684         struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2685         unsigned int xive_num = hwirq - phb->msi_base;
2686         __be32 data;
2687         int rc;
2688
2689         /* No PE assigned ? bail out ... no MSI for you ! */
2690         if (pe == NULL)
2691                 return -ENXIO;
2692
2693         /* Check if we have an MVE */
2694         if (pe->mve_number < 0)
2695                 return -ENXIO;
2696
2697         /* Force 32-bit MSI on some broken devices */
2698         if (dev->no_64bit_msi)
2699                 is_64 = 0;
2700
2701         /* Assign XIVE to PE */
2702         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2703         if (rc) {
2704                 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2705                         pci_name(dev), rc, xive_num);
2706                 return -EIO;
2707         }
2708
2709         if (is_64) {
2710                 __be64 addr64;
2711
2712                 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2713                                      &addr64, &data);
2714                 if (rc) {
2715                         pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2716                                 pci_name(dev), rc);
2717                         return -EIO;
2718                 }
2719                 msg->address_hi = be64_to_cpu(addr64) >> 32;
2720                 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2721         } else {
2722                 __be32 addr32;
2723
2724                 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2725                                      &addr32, &data);
2726                 if (rc) {
2727                         pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2728                                 pci_name(dev), rc);
2729                         return -EIO;
2730                 }
2731                 msg->address_hi = 0;
2732                 msg->address_lo = be32_to_cpu(addr32);
2733         }
2734         msg->data = be32_to_cpu(data);
2735
2736         pnv_set_msi_irq_chip(phb, virq);
2737
2738         pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2739                  " address=%x_%08x data=%x PE# %d\n",
2740                  pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2741                  msg->address_hi, msg->address_lo, data, pe->pe_number);
2742
2743         return 0;
2744 }
2745
2746 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2747 {
2748         unsigned int count;
2749         const __be32 *prop = of_get_property(phb->hose->dn,
2750                                              "ibm,opal-msi-ranges", NULL);
2751         if (!prop) {
2752                 /* BML Fallback */
2753                 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2754         }
2755         if (!prop)
2756                 return;
2757
2758         phb->msi_base = be32_to_cpup(prop);
2759         count = be32_to_cpup(prop + 1);
2760         if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2761                 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2762                        phb->hose->global_number);
2763                 return;
2764         }
2765
2766         phb->msi_setup = pnv_pci_ioda_msi_setup;
2767         phb->msi32_support = 1;
2768         pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2769                 count, phb->msi_base);
2770 }
2771 #else
2772 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
2773 #endif /* CONFIG_PCI_MSI */
2774
2775 #ifdef CONFIG_PCI_IOV
2776 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2777 {
2778         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2779         struct pnv_phb *phb = hose->private_data;
2780         const resource_size_t gate = phb->ioda.m64_segsize >> 2;
2781         struct resource *res;
2782         int i;
2783         resource_size_t size, total_vf_bar_sz;
2784         struct pci_dn *pdn;
2785         int mul, total_vfs;
2786
2787         if (!pdev->is_physfn || pdev->is_added)
2788                 return;
2789
2790         pdn = pci_get_pdn(pdev);
2791         pdn->vfs_expanded = 0;
2792         pdn->m64_single_mode = false;
2793
2794         total_vfs = pci_sriov_get_totalvfs(pdev);
2795         mul = phb->ioda.total_pe_num;
2796         total_vf_bar_sz = 0;
2797
2798         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2799                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2800                 if (!res->flags || res->parent)
2801                         continue;
2802                 if (!pnv_pci_is_mem_pref_64(res->flags)) {
2803                         dev_warn(&pdev->dev, "Don't support SR-IOV with"
2804                                         " non M64 VF BAR%d: %pR. \n",
2805                                  i, res);
2806                         goto truncate_iov;
2807                 }
2808
2809                 total_vf_bar_sz += pci_iov_resource_size(pdev,
2810                                 i + PCI_IOV_RESOURCES);
2811
2812                 /*
2813                  * If bigger than quarter of M64 segment size, just round up
2814                  * power of two.
2815                  *
2816                  * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
2817                  * with other devices, IOV BAR size is expanded to be
2818                  * (total_pe * VF_BAR_size).  When VF_BAR_size is half of M64
2819                  * segment size , the expanded size would equal to half of the
2820                  * whole M64 space size, which will exhaust the M64 Space and
2821                  * limit the system flexibility.  This is a design decision to
2822                  * set the boundary to quarter of the M64 segment size.
2823                  */
2824                 if (total_vf_bar_sz > gate) {
2825                         mul = roundup_pow_of_two(total_vfs);
2826                         dev_info(&pdev->dev,
2827                                 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
2828                                 total_vf_bar_sz, gate, mul);
2829                         pdn->m64_single_mode = true;
2830                         break;
2831                 }
2832         }
2833
2834         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2835                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2836                 if (!res->flags || res->parent)
2837                         continue;
2838
2839                 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2840                 /*
2841                  * On PHB3, the minimum size alignment of M64 BAR in single
2842                  * mode is 32MB.
2843                  */
2844                 if (pdn->m64_single_mode && (size < SZ_32M))
2845                         goto truncate_iov;
2846                 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2847                 res->end = res->start + size * mul - 1;
2848                 dev_dbg(&pdev->dev, "                       %pR\n", res);
2849                 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2850                          i, res, mul);
2851         }
2852         pdn->vfs_expanded = mul;
2853
2854         return;
2855
2856 truncate_iov:
2857         /* To save MMIO space, IOV BAR is truncated. */
2858         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2859                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2860                 res->flags = 0;
2861                 res->end = res->start - 1;
2862         }
2863 }
2864 #endif /* CONFIG_PCI_IOV */
2865
2866 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
2867                                   struct resource *res)
2868 {
2869         struct pnv_phb *phb = pe->phb;
2870         struct pci_bus_region region;
2871         int index;
2872         int64_t rc;
2873
2874         if (!res || !res->flags || res->start > res->end)
2875                 return;
2876
2877         if (res->flags & IORESOURCE_IO) {
2878                 region.start = res->start - phb->ioda.io_pci_base;
2879                 region.end   = res->end - phb->ioda.io_pci_base;
2880                 index = region.start / phb->ioda.io_segsize;
2881
2882                 while (index < phb->ioda.total_pe_num &&
2883                        region.start <= region.end) {
2884                         phb->ioda.io_segmap[index] = pe->pe_number;
2885                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2886                                 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
2887                         if (rc != OPAL_SUCCESS) {
2888                                 pr_err("%s: Error %lld mapping IO segment#%d to PE#%d\n",
2889                                        __func__, rc, index, pe->pe_number);
2890                                 break;
2891                         }
2892
2893                         region.start += phb->ioda.io_segsize;
2894                         index++;
2895                 }
2896         } else if ((res->flags & IORESOURCE_MEM) &&
2897                    !pnv_pci_is_mem_pref_64(res->flags)) {
2898                 region.start = res->start -
2899                                phb->hose->mem_offset[0] -
2900                                phb->ioda.m32_pci_base;
2901                 region.end   = res->end -
2902                                phb->hose->mem_offset[0] -
2903                                phb->ioda.m32_pci_base;
2904                 index = region.start / phb->ioda.m32_segsize;
2905
2906                 while (index < phb->ioda.total_pe_num &&
2907                        region.start <= region.end) {
2908                         phb->ioda.m32_segmap[index] = pe->pe_number;
2909                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2910                                 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
2911                         if (rc != OPAL_SUCCESS) {
2912                                 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%d",
2913                                        __func__, rc, index, pe->pe_number);
2914                                 break;
2915                         }
2916
2917                         region.start += phb->ioda.m32_segsize;
2918                         index++;
2919                 }
2920         }
2921 }
2922
2923 /*
2924  * This function is supposed to be called on basis of PE from top
2925  * to bottom style. So the the I/O or MMIO segment assigned to
2926  * parent PE could be overrided by its child PEs if necessary.
2927  */
2928 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
2929 {
2930         struct pci_dev *pdev;
2931         int i;
2932
2933         /*
2934          * NOTE: We only care PCI bus based PE for now. For PCI
2935          * device based PE, for example SRIOV sensitive VF should
2936          * be figured out later.
2937          */
2938         BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
2939
2940         list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
2941                 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
2942                         pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
2943
2944                 /*
2945                  * If the PE contains all subordinate PCI buses, the
2946                  * windows of the child bridges should be mapped to
2947                  * the PE as well.
2948                  */
2949                 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
2950                         continue;
2951                 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
2952                         pnv_ioda_setup_pe_res(pe,
2953                                 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
2954         }
2955 }
2956
2957 static void pnv_pci_ioda_create_dbgfs(void)
2958 {
2959 #ifdef CONFIG_DEBUG_FS
2960         struct pci_controller *hose, *tmp;
2961         struct pnv_phb *phb;
2962         char name[16];
2963
2964         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2965                 phb = hose->private_data;
2966
2967                 /* Notify initialization of PHB done */
2968                 phb->initialized = 1;
2969
2970                 sprintf(name, "PCI%04x", hose->global_number);
2971                 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
2972                 if (!phb->dbgfs)
2973                         pr_warning("%s: Error on creating debugfs on PHB#%x\n",
2974                                 __func__, hose->global_number);
2975         }
2976 #endif /* CONFIG_DEBUG_FS */
2977 }
2978
2979 static void pnv_pci_ioda_fixup(void)
2980 {
2981         pnv_pci_ioda_setup_PEs();
2982         pnv_pci_ioda_setup_iommu_api();
2983         pnv_pci_ioda_create_dbgfs();
2984
2985 #ifdef CONFIG_EEH
2986         eeh_init();
2987         eeh_addr_cache_build();
2988 #endif
2989 }
2990
2991 /*
2992  * Returns the alignment for I/O or memory windows for P2P
2993  * bridges. That actually depends on how PEs are segmented.
2994  * For now, we return I/O or M32 segment size for PE sensitive
2995  * P2P bridges. Otherwise, the default values (4KiB for I/O,
2996  * 1MiB for memory) will be returned.
2997  *
2998  * The current PCI bus might be put into one PE, which was
2999  * create against the parent PCI bridge. For that case, we
3000  * needn't enlarge the alignment so that we can save some
3001  * resources.
3002  */
3003 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3004                                                 unsigned long type)
3005 {
3006         struct pci_dev *bridge;
3007         struct pci_controller *hose = pci_bus_to_host(bus);
3008         struct pnv_phb *phb = hose->private_data;
3009         int num_pci_bridges = 0;
3010
3011         bridge = bus->self;
3012         while (bridge) {
3013                 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3014                         num_pci_bridges++;
3015                         if (num_pci_bridges >= 2)
3016                                 return 1;
3017                 }
3018
3019                 bridge = bridge->bus->self;
3020         }
3021
3022         /* We fail back to M32 if M64 isn't supported */
3023         if (phb->ioda.m64_segsize &&
3024             pnv_pci_is_mem_pref_64(type))
3025                 return phb->ioda.m64_segsize;
3026         if (type & IORESOURCE_MEM)
3027                 return phb->ioda.m32_segsize;
3028
3029         return phb->ioda.io_segsize;
3030 }
3031
3032 /*
3033  * We are updating root port or the upstream port of the
3034  * bridge behind the root port with PHB's windows in order
3035  * to accommodate the changes on required resources during
3036  * PCI (slot) hotplug, which is connected to either root
3037  * port or the downstream ports of PCIe switch behind the
3038  * root port.
3039  */
3040 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
3041                                            unsigned long type)
3042 {
3043         struct pci_controller *hose = pci_bus_to_host(bus);
3044         struct pnv_phb *phb = hose->private_data;
3045         struct pci_dev *bridge = bus->self;
3046         struct resource *r, *w;
3047         bool msi_region = false;
3048         int i;
3049
3050         /* Check if we need apply fixup to the bridge's windows */
3051         if (!pci_is_root_bus(bridge->bus) &&
3052             !pci_is_root_bus(bridge->bus->self->bus))
3053                 return;
3054
3055         /* Fixup the resources */
3056         for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
3057                 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
3058                 if (!r->flags || !r->parent)
3059                         continue;
3060
3061                 w = NULL;
3062                 if (r->flags & type & IORESOURCE_IO)
3063                         w = &hose->io_resource;
3064                 else if (pnv_pci_is_mem_pref_64(r->flags) &&
3065                          (type & IORESOURCE_PREFETCH) &&
3066                          phb->ioda.m64_segsize)
3067                         w = &hose->mem_resources[1];
3068                 else if (r->flags & type & IORESOURCE_MEM) {
3069                         w = &hose->mem_resources[0];
3070                         msi_region = true;
3071                 }
3072
3073                 r->start = w->start;
3074                 r->end = w->end;
3075
3076                 /* The 64KB 32-bits MSI region shouldn't be included in
3077                  * the 32-bits bridge window. Otherwise, we can see strange
3078                  * issues. One of them is EEH error observed on Garrison.
3079                  *
3080                  * Exclude top 1MB region which is the minimal alignment of
3081                  * 32-bits bridge window.
3082                  */
3083                 if (msi_region) {
3084                         r->end += 0x10000;
3085                         r->end -= 0x100000;
3086                 }
3087         }
3088 }
3089
3090 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type)
3091 {
3092         struct pci_controller *hose = pci_bus_to_host(bus);
3093         struct pnv_phb *phb = hose->private_data;
3094         struct pci_dev *bridge = bus->self;
3095         struct pnv_ioda_pe *pe;
3096         bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
3097
3098         /* Extend bridge's windows if necessary */
3099         pnv_pci_fixup_bridge_resources(bus, type);
3100
3101         /* The PE for root bus should be realized before any one else */
3102         if (!phb->ioda.root_pe_populated) {
3103                 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
3104                 if (pe) {
3105                         phb->ioda.root_pe_idx = pe->pe_number;
3106                         phb->ioda.root_pe_populated = true;
3107                 }
3108         }
3109
3110         /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3111         if (list_empty(&bus->devices))
3112                 return;
3113
3114         /* Reserve PEs according to used M64 resources */
3115         if (phb->reserve_m64_pe)
3116                 phb->reserve_m64_pe(bus, NULL, all);
3117
3118         /*
3119          * Assign PE. We might run here because of partial hotplug.
3120          * For the case, we just pick up the existing PE and should
3121          * not allocate resources again.
3122          */
3123         pe = pnv_ioda_setup_bus_PE(bus, all);
3124         if (!pe)
3125                 return;
3126
3127         pnv_ioda_setup_pe_seg(pe);
3128         switch (phb->type) {
3129         case PNV_PHB_IODA1:
3130                 pnv_pci_ioda1_setup_dma_pe(phb, pe);
3131                 break;
3132         case PNV_PHB_IODA2:
3133                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
3134                 break;
3135         default:
3136                 pr_warn("%s: No DMA for PHB#%d (type %d)\n",
3137                         __func__, phb->hose->global_number, phb->type);
3138         }
3139 }
3140
3141 #ifdef CONFIG_PCI_IOV
3142 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3143                                                       int resno)
3144 {
3145         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3146         struct pnv_phb *phb = hose->private_data;
3147         struct pci_dn *pdn = pci_get_pdn(pdev);
3148         resource_size_t align;
3149
3150         /*
3151          * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3152          * SR-IOV. While from hardware perspective, the range mapped by M64
3153          * BAR should be size aligned.
3154          *
3155          * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3156          * powernv-specific hardware restriction is gone. But if just use the
3157          * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3158          * in one segment of M64 #15, which introduces the PE conflict between
3159          * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3160          * m64_segsize.
3161          *
3162          * This function returns the total IOV BAR size if M64 BAR is in
3163          * Shared PE mode or just VF BAR size if not.
3164          * If the M64 BAR is in Single PE mode, return the VF BAR size or
3165          * M64 segment size if IOV BAR size is less.
3166          */
3167         align = pci_iov_resource_size(pdev, resno);
3168         if (!pdn->vfs_expanded)
3169                 return align;
3170         if (pdn->m64_single_mode)
3171                 return max(align, (resource_size_t)phb->ioda.m64_segsize);
3172
3173         return pdn->vfs_expanded * align;
3174 }
3175 #endif /* CONFIG_PCI_IOV */
3176
3177 /* Prevent enabling devices for which we couldn't properly
3178  * assign a PE
3179  */
3180 bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3181 {
3182         struct pci_controller *hose = pci_bus_to_host(dev->bus);
3183         struct pnv_phb *phb = hose->private_data;
3184         struct pci_dn *pdn;
3185
3186         /* The function is probably called while the PEs have
3187          * not be created yet. For example, resource reassignment
3188          * during PCI probe period. We just skip the check if
3189          * PEs isn't ready.
3190          */
3191         if (!phb->initialized)
3192                 return true;
3193
3194         pdn = pci_get_pdn(dev);
3195         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3196                 return false;
3197
3198         return true;
3199 }
3200
3201 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
3202                                        int num)
3203 {
3204         struct pnv_ioda_pe *pe = container_of(table_group,
3205                                               struct pnv_ioda_pe, table_group);
3206         struct pnv_phb *phb = pe->phb;
3207         unsigned int idx;
3208         long rc;
3209
3210         pe_info(pe, "Removing DMA window #%d\n", num);
3211         for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
3212                 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
3213                         continue;
3214
3215                 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
3216                                                 idx, 0, 0ul, 0ul, 0ul);
3217                 if (rc != OPAL_SUCCESS) {
3218                         pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
3219                                 rc, idx);
3220                         return rc;
3221                 }
3222
3223                 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
3224         }
3225
3226         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
3227         return OPAL_SUCCESS;
3228 }
3229
3230 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
3231 {
3232         unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3233         struct iommu_table *tbl = pe->table_group.tables[0];
3234         int64_t rc;
3235
3236         if (!weight)
3237                 return;
3238
3239         rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
3240         if (rc != OPAL_SUCCESS)
3241                 return;
3242
3243         pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
3244         if (pe->table_group.group) {
3245                 iommu_group_put(pe->table_group.group);
3246                 WARN_ON(pe->table_group.group);
3247         }
3248
3249         free_pages(tbl->it_base, get_order(tbl->it_size << 3));
3250         iommu_free_table(tbl, "pnv");
3251 }
3252
3253 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
3254 {
3255         struct iommu_table *tbl = pe->table_group.tables[0];
3256         unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3257 #ifdef CONFIG_IOMMU_API
3258         int64_t rc;
3259 #endif
3260
3261         if (!weight)
3262                 return;
3263
3264 #ifdef CONFIG_IOMMU_API
3265         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
3266         if (rc)
3267                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
3268 #endif
3269
3270         pnv_pci_ioda2_set_bypass(pe, false);
3271         if (pe->table_group.group) {
3272                 iommu_group_put(pe->table_group.group);
3273                 WARN_ON(pe->table_group.group);
3274         }
3275
3276         pnv_pci_ioda2_table_free_pages(tbl);
3277         iommu_free_table(tbl, "pnv");
3278 }
3279
3280 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
3281                                  unsigned short win,
3282                                  unsigned int *map)
3283 {
3284         struct pnv_phb *phb = pe->phb;
3285         int idx;
3286         int64_t rc;
3287
3288         for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
3289                 if (map[idx] != pe->pe_number)
3290                         continue;
3291
3292                 if (win == OPAL_M64_WINDOW_TYPE)
3293                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3294                                         phb->ioda.reserved_pe_idx, win,
3295                                         idx / PNV_IODA1_M64_SEGS,
3296                                         idx % PNV_IODA1_M64_SEGS);
3297                 else
3298                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3299                                         phb->ioda.reserved_pe_idx, win, 0, idx);
3300
3301                 if (rc != OPAL_SUCCESS)
3302                         pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n",
3303                                 rc, win, idx);
3304
3305                 map[idx] = IODA_INVALID_PE;
3306         }
3307 }
3308
3309 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
3310 {
3311         struct pnv_phb *phb = pe->phb;
3312
3313         if (phb->type == PNV_PHB_IODA1) {
3314                 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
3315                                      phb->ioda.io_segmap);
3316                 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3317                                      phb->ioda.m32_segmap);
3318                 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
3319                                      phb->ioda.m64_segmap);
3320         } else if (phb->type == PNV_PHB_IODA2) {
3321                 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3322                                      phb->ioda.m32_segmap);
3323         }
3324 }
3325
3326 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
3327 {
3328         struct pnv_phb *phb = pe->phb;
3329         struct pnv_ioda_pe *slave, *tmp;
3330
3331         /* Release slave PEs in compound PE */
3332         if (pe->flags & PNV_IODA_PE_MASTER) {
3333                 list_for_each_entry_safe(slave, tmp, &pe->slaves, list)
3334                         pnv_ioda_release_pe(slave);
3335         }
3336
3337         list_del(&pe->list);
3338         switch (phb->type) {
3339         case PNV_PHB_IODA1:
3340                 pnv_pci_ioda1_release_pe_dma(pe);
3341                 break;
3342         case PNV_PHB_IODA2:
3343                 pnv_pci_ioda2_release_pe_dma(pe);
3344                 break;
3345         default:
3346                 WARN_ON(1);
3347         }
3348
3349         pnv_ioda_release_pe_seg(pe);
3350         pnv_ioda_deconfigure_pe(pe->phb, pe);
3351         pnv_ioda_free_pe(pe);
3352 }
3353
3354 static void pnv_pci_release_device(struct pci_dev *pdev)
3355 {
3356         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3357         struct pnv_phb *phb = hose->private_data;
3358         struct pci_dn *pdn = pci_get_pdn(pdev);
3359         struct pnv_ioda_pe *pe;
3360
3361         if (pdev->is_virtfn)
3362                 return;
3363
3364         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3365                 return;
3366
3367         pe = &phb->ioda.pe_array[pdn->pe_number];
3368         WARN_ON(--pe->device_count < 0);
3369         if (pe->device_count == 0)
3370                 pnv_ioda_release_pe(pe);
3371 }
3372
3373 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3374 {
3375         struct pnv_phb *phb = hose->private_data;
3376
3377         opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3378                        OPAL_ASSERT_RESET);
3379 }
3380
3381 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3382         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3383         .dma_bus_setup          = pnv_pci_dma_bus_setup,
3384 #ifdef CONFIG_PCI_MSI
3385         .setup_msi_irqs         = pnv_setup_msi_irqs,
3386         .teardown_msi_irqs      = pnv_teardown_msi_irqs,
3387 #endif
3388         .enable_device_hook     = pnv_pci_enable_device_hook,
3389         .release_device         = pnv_pci_release_device,
3390         .window_alignment       = pnv_pci_window_alignment,
3391         .setup_bridge           = pnv_pci_setup_bridge,
3392         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3393         .dma_set_mask           = pnv_pci_ioda_dma_set_mask,
3394         .dma_get_required_mask  = pnv_pci_ioda_dma_get_required_mask,
3395         .shutdown               = pnv_pci_ioda_shutdown,
3396 };
3397
3398 static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask)
3399 {
3400         dev_err_once(&npdev->dev,
3401                         "%s operation unsupported for NVLink devices\n",
3402                         __func__);
3403         return -EPERM;
3404 }
3405
3406 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3407         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3408 #ifdef CONFIG_PCI_MSI
3409         .setup_msi_irqs         = pnv_setup_msi_irqs,
3410         .teardown_msi_irqs      = pnv_teardown_msi_irqs,
3411 #endif
3412         .enable_device_hook     = pnv_pci_enable_device_hook,
3413         .window_alignment       = pnv_pci_window_alignment,
3414         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3415         .dma_set_mask           = pnv_npu_dma_set_mask,
3416         .shutdown               = pnv_pci_ioda_shutdown,
3417 };
3418
3419 #ifdef CONFIG_CXL_BASE
3420 const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = {
3421         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3422         .dma_bus_setup          = pnv_pci_dma_bus_setup,
3423 #ifdef CONFIG_PCI_MSI
3424         .setup_msi_irqs         = pnv_cxl_cx4_setup_msi_irqs,
3425         .teardown_msi_irqs      = pnv_cxl_cx4_teardown_msi_irqs,
3426 #endif
3427         .enable_device_hook     = pnv_cxl_enable_device_hook,
3428         .disable_device         = pnv_cxl_disable_device,
3429         .release_device         = pnv_pci_release_device,
3430         .window_alignment       = pnv_pci_window_alignment,
3431         .setup_bridge           = pnv_pci_setup_bridge,
3432         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3433         .dma_set_mask           = pnv_pci_ioda_dma_set_mask,
3434         .dma_get_required_mask  = pnv_pci_ioda_dma_get_required_mask,
3435         .shutdown               = pnv_pci_ioda_shutdown,
3436 };
3437 #endif
3438
3439 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3440                                          u64 hub_id, int ioda_type)
3441 {
3442         struct pci_controller *hose;
3443         struct pnv_phb *phb;
3444         unsigned long size, m64map_off, m32map_off, pemap_off;
3445         unsigned long iomap_off = 0, dma32map_off = 0;
3446         struct resource r;
3447         const __be64 *prop64;
3448         const __be32 *prop32;
3449         int len;
3450         unsigned int segno;
3451         u64 phb_id;
3452         void *aux;
3453         long rc;
3454
3455         pr_info("Initializing %s PHB (%s)\n",
3456                 pnv_phb_names[ioda_type], of_node_full_name(np));
3457
3458         prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3459         if (!prop64) {
3460                 pr_err("  Missing \"ibm,opal-phbid\" property !\n");
3461                 return;
3462         }
3463         phb_id = be64_to_cpup(prop64);
3464         pr_debug("  PHB-ID  : 0x%016llx\n", phb_id);
3465
3466         phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
3467
3468         /* Allocate PCI controller */
3469         phb->hose = hose = pcibios_alloc_controller(np);
3470         if (!phb->hose) {
3471                 pr_err("  Can't allocate PCI controller for %s\n",
3472                        np->full_name);
3473                 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3474                 return;
3475         }
3476
3477         spin_lock_init(&phb->lock);
3478         prop32 = of_get_property(np, "bus-range", &len);
3479         if (prop32 && len == 8) {
3480                 hose->first_busno = be32_to_cpu(prop32[0]);
3481                 hose->last_busno = be32_to_cpu(prop32[1]);
3482         } else {
3483                 pr_warn("  Broken <bus-range> on %s\n", np->full_name);
3484                 hose->first_busno = 0;
3485                 hose->last_busno = 0xff;
3486         }
3487         hose->private_data = phb;
3488         phb->hub_id = hub_id;
3489         phb->opal_id = phb_id;
3490         phb->type = ioda_type;
3491         mutex_init(&phb->ioda.pe_alloc_mutex);
3492
3493         /* Detect specific models for error handling */
3494         if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3495                 phb->model = PNV_PHB_MODEL_P7IOC;
3496         else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3497                 phb->model = PNV_PHB_MODEL_PHB3;
3498         else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3499                 phb->model = PNV_PHB_MODEL_NPU;
3500         else
3501                 phb->model = PNV_PHB_MODEL_UNKNOWN;
3502
3503         /* Parse 32-bit and IO ranges (if any) */
3504         pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3505
3506         /* Get registers */
3507         if (!of_address_to_resource(np, 0, &r)) {
3508                 phb->regs_phys = r.start;
3509                 phb->regs = ioremap(r.start, resource_size(&r));
3510                 if (phb->regs == NULL)
3511                         pr_err("  Failed to map registers !\n");
3512         }
3513
3514         /* Initialize more IODA stuff */
3515         phb->ioda.total_pe_num = 1;
3516         prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3517         if (prop32)
3518                 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3519         prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3520         if (prop32)
3521                 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3522
3523         /* Invalidate RID to PE# mapping */
3524         for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3525                 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3526
3527         /* Parse 64-bit MMIO range */
3528         pnv_ioda_parse_m64_window(phb);
3529
3530         phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3531         /* FW Has already off top 64k of M32 space (MSI space) */
3532         phb->ioda.m32_size += 0x10000;
3533
3534         phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3535         phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3536         phb->ioda.io_size = hose->pci_io_size;
3537         phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3538         phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3539
3540         /* Calculate how many 32-bit TCE segments we have */
3541         phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3542                                 PNV_IODA1_DMA32_SEGSIZE;
3543
3544         /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3545         size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3546                         sizeof(unsigned long));
3547         m64map_off = size;
3548         size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3549         m32map_off = size;
3550         size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3551         if (phb->type == PNV_PHB_IODA1) {
3552                 iomap_off = size;
3553                 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3554                 dma32map_off = size;
3555                 size += phb->ioda.dma32_count *
3556                         sizeof(phb->ioda.dma32_segmap[0]);
3557         }
3558         pemap_off = size;
3559         size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3560         aux = memblock_virt_alloc(size, 0);
3561         phb->ioda.pe_alloc = aux;
3562         phb->ioda.m64_segmap = aux + m64map_off;
3563         phb->ioda.m32_segmap = aux + m32map_off;
3564         for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3565                 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3566                 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3567         }
3568         if (phb->type == PNV_PHB_IODA1) {
3569                 phb->ioda.io_segmap = aux + iomap_off;
3570                 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3571                         phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3572
3573                 phb->ioda.dma32_segmap = aux + dma32map_off;
3574                 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3575                         phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3576         }
3577         phb->ioda.pe_array = aux + pemap_off;
3578
3579         /*
3580          * Choose PE number for root bus, which shouldn't have
3581          * M64 resources consumed by its child devices. To pick
3582          * the PE number adjacent to the reserved one if possible.
3583          */
3584         pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3585         if (phb->ioda.reserved_pe_idx == 0) {
3586                 phb->ioda.root_pe_idx = 1;
3587                 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3588         } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3589                 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3590                 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3591         } else {
3592                 phb->ioda.root_pe_idx = IODA_INVALID_PE;
3593         }
3594
3595         INIT_LIST_HEAD(&phb->ioda.pe_list);
3596         mutex_init(&phb->ioda.pe_list_mutex);
3597
3598         /* Calculate how many 32-bit TCE segments we have */
3599         phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3600                                 PNV_IODA1_DMA32_SEGSIZE;
3601
3602 #if 0 /* We should really do that ... */
3603         rc = opal_pci_set_phb_mem_window(opal->phb_id,
3604                                          window_type,
3605                                          window_num,
3606                                          starting_real_address,
3607                                          starting_pci_address,
3608                                          segment_size);
3609 #endif
3610
3611         pr_info("  %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3612                 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3613                 phb->ioda.m32_size, phb->ioda.m32_segsize);
3614         if (phb->ioda.m64_size)
3615                 pr_info("                 M64: 0x%lx [segment=0x%lx]\n",
3616                         phb->ioda.m64_size, phb->ioda.m64_segsize);
3617         if (phb->ioda.io_size)
3618                 pr_info("                  IO: 0x%x [segment=0x%x]\n",
3619                         phb->ioda.io_size, phb->ioda.io_segsize);
3620
3621
3622         phb->hose->ops = &pnv_pci_ops;
3623         phb->get_pe_state = pnv_ioda_get_pe_state;
3624         phb->freeze_pe = pnv_ioda_freeze_pe;
3625         phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3626
3627         /* Setup MSI support */
3628         pnv_pci_init_ioda_msis(phb);
3629
3630         /*
3631          * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3632          * to let the PCI core do resource assignment. It's supposed
3633          * that the PCI core will do correct I/O and MMIO alignment
3634          * for the P2P bridge bars so that each PCI bus (excluding
3635          * the child P2P bridges) can form individual PE.
3636          */
3637         ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3638
3639         if (phb->type == PNV_PHB_NPU) {
3640                 hose->controller_ops = pnv_npu_ioda_controller_ops;
3641         } else {
3642                 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3643                 hose->controller_ops = pnv_pci_ioda_controller_ops;
3644         }
3645
3646 #ifdef CONFIG_PCI_IOV
3647         ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
3648         ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3649 #endif
3650
3651         pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3652
3653         /* Reset IODA tables to a clean state */
3654         rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3655         if (rc)
3656                 pr_warning("  OPAL Error %ld performing IODA table reset !\n", rc);
3657
3658         /* If we're running in kdump kerenl, the previous kerenl never
3659          * shutdown PCI devices correctly. We already got IODA table
3660          * cleaned out. So we have to issue PHB reset to stop all PCI
3661          * transactions from previous kerenl.
3662          */
3663         if (is_kdump_kernel()) {
3664                 pr_info("  Issue PHB reset ...\n");
3665                 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3666                 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3667         }
3668
3669         /* Remove M64 resource if we can't configure it successfully */
3670         if (!phb->init_m64 || phb->init_m64(phb))
3671                 hose->mem_resources[1].flags = 0;
3672 }
3673
3674 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3675 {
3676         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3677 }
3678
3679 void __init pnv_pci_init_npu_phb(struct device_node *np)
3680 {
3681         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU);
3682 }
3683
3684 void __init pnv_pci_init_ioda_hub(struct device_node *np)
3685 {
3686         struct device_node *phbn;
3687         const __be64 *prop64;
3688         u64 hub_id;
3689
3690         pr_info("Probing IODA IO-Hub %s\n", np->full_name);
3691
3692         prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3693         if (!prop64) {
3694                 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3695                 return;
3696         }
3697         hub_id = be64_to_cpup(prop64);
3698         pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3699
3700         /* Count child PHBs */
3701         for_each_child_of_node(np, phbn) {
3702                 /* Look for IODA1 PHBs */
3703                 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
3704                         pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
3705         }
3706 }