arch/powerpc/platforms/powernv/pci-p5ioc2.c

   1 /*
   2  * Support PCI/PCIe on PowerNV platforms
   3  *
   4  * Currently supports only P5IOC2
   5  *
   6  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version
  11  * 2 of the License, or (at your option) any later version.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/delay.h>
  17 #include <linux/string.h>
  18 #include <linux/init.h>
  19 #include <linux/bootmem.h>
  20 #include <linux/irq.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/sections.h>
  24 #include <asm/io.h>
  25 #include <asm/prom.h>
  26 #include <asm/pci-bridge.h>
  27 #include <asm/machdep.h>
  28 #include <asm/ppc-pci.h>
  29 #include <asm/opal.h>
  30 #include <asm/iommu.h>
  31 #include <asm/tce.h>
  32 #include <asm/abs_addr.h>
  33
  34 #include "powernv.h"
  35 #include "pci.h"
  36
  37 /* For now, use a fixed amount of TCE memory for each p5ioc2
  38  * hub, 16M will do
  39  */
  40 #define P5IOC2_TCE_MEMORY       0x01000000
  41
  42 static void __devinit pnv_pci_p5ioc2_dma_dev_setup(struct pnv_phb *phb,
  43                                                    struct pci_dev *pdev)
  44 {
  45         if (phb->p5ioc2.iommu_table.it_map == NULL)
  46                 iommu_init_table(&phb->p5ioc2.iommu_table, phb->hose->node);
  47
  48         set_iommu_table_base(&pdev->dev, &phb->p5ioc2.iommu_table);
  49 }
  50
  51 static void __init pnv_pci_init_p5ioc2_phb(struct device_node *np,
  52                                            void *tce_mem, u64 tce_size)
  53 {
  54         struct pnv_phb *phb;
  55         const u64 *prop64;
  56         u64 phb_id;
  57         int64_t rc;
  58         static int primary = 1;
  59
  60         pr_info(" Initializing p5ioc2 PHB %s\n", np->full_name);
  61
  62         prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
  63         if (!prop64) {
  64                 pr_err("  Missing \"ibm,opal-phbid\" property !\n");
  65                 return;
  66         }
  67         phb_id = be64_to_cpup(prop64);
  68         pr_devel("  PHB-ID  : 0x%016llx\n", phb_id);
  69         pr_devel("  TCE AT  : 0x%016lx\n", __pa(tce_mem));
  70         pr_devel("  TCE SZ  : 0x%016llx\n", tce_size);
  71
  72         rc = opal_pci_set_phb_tce_memory(phb_id, __pa(tce_mem), tce_size);
  73         if (rc != OPAL_SUCCESS) {
  74                 pr_err("  Failed to set TCE memory, OPAL error %lld\n", rc);
  75                 return;
  76         }
  77
  78         phb = alloc_bootmem(sizeof(struct pnv_phb));
  79         if (phb) {
  80                 memset(phb, 0, sizeof(struct pnv_phb));
  81                 phb->hose = pcibios_alloc_controller(np);
  82         }
  83         if (!phb || !phb->hose) {
  84                 pr_err("  Failed to allocate PCI controller\n");
  85                 return;
  86         }
  87
  88         spin_lock_init(&phb->lock);
  89         phb->hose->first_busno = 0;
  90         phb->hose->last_busno = 0xff;
  91         phb->hose->private_data = phb;
  92         phb->opal_id = phb_id;
  93         phb->type = PNV_PHB_P5IOC2;
  94
  95         phb->regs = of_iomap(np, 0);
  96
  97         if (phb->regs == NULL)
  98                 pr_err("  Failed to map registers !\n");
  99         else {
 100                 pr_devel("  P_BUID     = 0x%08x\n", in_be32(phb->regs + 0x100));
 101                 pr_devel("  P_IOSZ     = 0x%08x\n", in_be32(phb->regs + 0x1b0));
 102                 pr_devel("  P_IO_ST    = 0x%08x\n", in_be32(phb->regs + 0x1e0));
 103                 pr_devel("  P_MEM1_H   = 0x%08x\n", in_be32(phb->regs + 0x1a0));
 104                 pr_devel("  P_MEM1_L   = 0x%08x\n", in_be32(phb->regs + 0x190));
 105                 pr_devel("  P_MSZ1_L   = 0x%08x\n", in_be32(phb->regs + 0x1c0));
 106                 pr_devel("  P_MEM_ST   = 0x%08x\n", in_be32(phb->regs + 0x1d0));
 107                 pr_devel("  P_MEM2_H   = 0x%08x\n", in_be32(phb->regs + 0x2c0));
 108                 pr_devel("  P_MEM2_L   = 0x%08x\n", in_be32(phb->regs + 0x2b0));
 109                 pr_devel("  P_MSZ2_H   = 0x%08x\n", in_be32(phb->regs + 0x2d0));
 110                 pr_devel("  P_MSZ2_L   = 0x%08x\n", in_be32(phb->regs + 0x2e0));
 111         }
 112
 113         /* Interpret the "ranges" property */
 114         /* This also maps the I/O region and sets isa_io/mem_base */
 115         pci_process_bridge_OF_ranges(phb->hose, np, primary);
 116         primary = 0;
 117
 118         phb->hose->ops = &pnv_pci_ops;
 119
 120         /* Setup TCEs */
 121         phb->dma_dev_setup = pnv_pci_p5ioc2_dma_dev_setup;
 122         pnv_pci_setup_iommu_table(&phb->p5ioc2.iommu_table,
 123                                   tce_mem, tce_size, 0);
 124 }
 125
 126 void __init pnv_pci_init_p5ioc2_hub(struct device_node *np)
 127 {
 128         struct device_node *phbn;
 129         const u64 *prop64;
 130         u64 hub_id;
 131         void *tce_mem;
 132         uint64_t tce_per_phb;
 133         int64_t rc;
 134         int phb_count = 0;
 135
 136         pr_info("Probing p5ioc2 IO-Hub %s\n", np->full_name);
 137
 138         prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
 139         if (!prop64) {
 140                 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
 141                 return;
 142         }
 143         hub_id = be64_to_cpup(prop64);
 144         pr_info(" HUB-ID : 0x%016llx\n", hub_id);
 145
 146         /* Currently allocate 16M of TCE memory for every Hub
 147          *
 148          * XXX TODO: Make it chip local if possible
 149          */
 150         tce_mem = __alloc_bootmem(P5IOC2_TCE_MEMORY, P5IOC2_TCE_MEMORY,
 151                                   __pa(MAX_DMA_ADDRESS));
 152         if (!tce_mem) {
 153                 pr_err(" Failed to allocate TCE Memory !\n");
 154                 return;
 155         }
 156         pr_debug(" TCE    : 0x%016lx..0x%016lx\n",
 157                 __pa(tce_mem), __pa(tce_mem) + P5IOC2_TCE_MEMORY - 1);
 158         rc = opal_pci_set_hub_tce_memory(hub_id, __pa(tce_mem),
 159                                         P5IOC2_TCE_MEMORY);
 160         if (rc != OPAL_SUCCESS) {
 161                 pr_err(" Failed to allocate TCE memory, OPAL error %lld\n", rc);
 162                 return;
 163         }
 164
 165         /* Count child PHBs */
 166         for_each_child_of_node(np, phbn) {
 167                 if (of_device_is_compatible(phbn, "ibm,p5ioc2-pcix") ||
 168                     of_device_is_compatible(phbn, "ibm,p5ioc2-pciex"))
 169                         phb_count++;
 170         }
 171
 172         /* Calculate how much TCE space we can give per PHB */
 173         tce_per_phb = __rounddown_pow_of_two(P5IOC2_TCE_MEMORY / phb_count);
 174         pr_info(" Allocating %lld MB of TCE memory per PHB\n",
 175                 tce_per_phb >> 20);
 176
 177         /* Initialize PHBs */
 178         for_each_child_of_node(np, phbn) {
 179                 if (of_device_is_compatible(phbn, "ibm,p5ioc2-pcix") ||
 180                     of_device_is_compatible(phbn, "ibm,p5ioc2-pciex")) {
 181                         pnv_pci_init_p5ioc2_phb(phbn, tce_mem, tce_per_phb);
 182                         tce_mem += tce_per_phb;
 183                 }
 184         }
 185 }