2 * Support PCI/PCIe on PowerNV platforms
4 * Currently supports only P5IOC2
6 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/delay.h>
17 #include <linux/string.h>
18 #include <linux/init.h>
19 #include <linux/irq.h>
21 #include <linux/msi.h>
22 #include <linux/iommu.h>
24 #include <asm/sections.h>
27 #include <asm/pci-bridge.h>
28 #include <asm/machdep.h>
29 #include <asm/msi_bitmap.h>
30 #include <asm/ppc-pci.h>
32 #include <asm/iommu.h>
34 #include <asm/firmware.h>
35 #include <asm/eeh_event.h>
42 #define PCI_RESET_DELAY_US 3000000
44 #define cfg_dbg(fmt...) do { } while(0)
45 //#define cfg_dbg(fmt...) printk(fmt)
48 int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
50 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
51 struct pnv_phb *phb = hose->private_data;
52 struct msi_desc *entry;
58 if (WARN_ON(!phb) || !phb->msi_bmp.bitmap)
61 if (pdev->no_64bit_msi && !phb->msi32_support)
64 for_each_pci_msi_entry(entry, pdev) {
65 if (!entry->msi_attrib.is_64 && !phb->msi32_support) {
66 pr_warn("%s: Supports only 64-bit MSIs\n",
70 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1);
72 pr_warn("%s: Failed to find a free MSI\n",
76 virq = irq_create_mapping(NULL, phb->msi_base + hwirq);
78 pr_warn("%s: Failed to map MSI to linux irq\n",
80 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
83 rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq,
84 virq, entry->msi_attrib.is_64, &msg);
86 pr_warn("%s: Failed to setup MSI\n", pci_name(pdev));
87 irq_dispose_mapping(virq);
88 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
91 irq_set_msi_desc(virq, entry);
92 pci_write_msi_msg(virq, &msg);
97 void pnv_teardown_msi_irqs(struct pci_dev *pdev)
99 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
100 struct pnv_phb *phb = hose->private_data;
101 struct msi_desc *entry;
106 for_each_pci_msi_entry(entry, pdev) {
107 if (entry->irq == NO_IRQ)
109 irq_set_msi_desc(entry->irq, NULL);
110 msi_bitmap_free_hwirqs(&phb->msi_bmp,
111 virq_to_hw(entry->irq) - phb->msi_base, 1);
112 irq_dispose_mapping(entry->irq);
115 #endif /* CONFIG_PCI_MSI */
117 static void pnv_pci_dump_p7ioc_diag_data(struct pci_controller *hose,
118 struct OpalIoPhbErrorCommon *common)
120 struct OpalIoP7IOCPhbErrorData *data;
123 data = (struct OpalIoP7IOCPhbErrorData *)common;
124 pr_info("P7IOC PHB#%d Diag-data (Version: %d)\n",
125 hose->global_number, be32_to_cpu(common->version));
128 pr_info("brdgCtl: %08x\n",
129 be32_to_cpu(data->brdgCtl));
130 if (data->portStatusReg || data->rootCmplxStatus ||
131 data->busAgentStatus)
132 pr_info("UtlSts: %08x %08x %08x\n",
133 be32_to_cpu(data->portStatusReg),
134 be32_to_cpu(data->rootCmplxStatus),
135 be32_to_cpu(data->busAgentStatus));
136 if (data->deviceStatus || data->slotStatus ||
137 data->linkStatus || data->devCmdStatus ||
139 pr_info("RootSts: %08x %08x %08x %08x %08x\n",
140 be32_to_cpu(data->deviceStatus),
141 be32_to_cpu(data->slotStatus),
142 be32_to_cpu(data->linkStatus),
143 be32_to_cpu(data->devCmdStatus),
144 be32_to_cpu(data->devSecStatus));
145 if (data->rootErrorStatus || data->uncorrErrorStatus ||
146 data->corrErrorStatus)
147 pr_info("RootErrSts: %08x %08x %08x\n",
148 be32_to_cpu(data->rootErrorStatus),
149 be32_to_cpu(data->uncorrErrorStatus),
150 be32_to_cpu(data->corrErrorStatus));
151 if (data->tlpHdr1 || data->tlpHdr2 ||
152 data->tlpHdr3 || data->tlpHdr4)
153 pr_info("RootErrLog: %08x %08x %08x %08x\n",
154 be32_to_cpu(data->tlpHdr1),
155 be32_to_cpu(data->tlpHdr2),
156 be32_to_cpu(data->tlpHdr3),
157 be32_to_cpu(data->tlpHdr4));
158 if (data->sourceId || data->errorClass ||
160 pr_info("RootErrLog1: %08x %016llx %016llx\n",
161 be32_to_cpu(data->sourceId),
162 be64_to_cpu(data->errorClass),
163 be64_to_cpu(data->correlator));
164 if (data->p7iocPlssr || data->p7iocCsr)
165 pr_info("PhbSts: %016llx %016llx\n",
166 be64_to_cpu(data->p7iocPlssr),
167 be64_to_cpu(data->p7iocCsr));
169 pr_info("Lem: %016llx %016llx %016llx\n",
170 be64_to_cpu(data->lemFir),
171 be64_to_cpu(data->lemErrorMask),
172 be64_to_cpu(data->lemWOF));
173 if (data->phbErrorStatus)
174 pr_info("PhbErr: %016llx %016llx %016llx %016llx\n",
175 be64_to_cpu(data->phbErrorStatus),
176 be64_to_cpu(data->phbFirstErrorStatus),
177 be64_to_cpu(data->phbErrorLog0),
178 be64_to_cpu(data->phbErrorLog1));
179 if (data->mmioErrorStatus)
180 pr_info("OutErr: %016llx %016llx %016llx %016llx\n",
181 be64_to_cpu(data->mmioErrorStatus),
182 be64_to_cpu(data->mmioFirstErrorStatus),
183 be64_to_cpu(data->mmioErrorLog0),
184 be64_to_cpu(data->mmioErrorLog1));
185 if (data->dma0ErrorStatus)
186 pr_info("InAErr: %016llx %016llx %016llx %016llx\n",
187 be64_to_cpu(data->dma0ErrorStatus),
188 be64_to_cpu(data->dma0FirstErrorStatus),
189 be64_to_cpu(data->dma0ErrorLog0),
190 be64_to_cpu(data->dma0ErrorLog1));
191 if (data->dma1ErrorStatus)
192 pr_info("InBErr: %016llx %016llx %016llx %016llx\n",
193 be64_to_cpu(data->dma1ErrorStatus),
194 be64_to_cpu(data->dma1FirstErrorStatus),
195 be64_to_cpu(data->dma1ErrorLog0),
196 be64_to_cpu(data->dma1ErrorLog1));
198 for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) {
199 if ((data->pestA[i] >> 63) == 0 &&
200 (data->pestB[i] >> 63) == 0)
203 pr_info("PE[%3d] A/B: %016llx %016llx\n",
204 i, be64_to_cpu(data->pestA[i]),
205 be64_to_cpu(data->pestB[i]));
209 static void pnv_pci_dump_phb3_diag_data(struct pci_controller *hose,
210 struct OpalIoPhbErrorCommon *common)
212 struct OpalIoPhb3ErrorData *data;
215 data = (struct OpalIoPhb3ErrorData*)common;
216 pr_info("PHB3 PHB#%d Diag-data (Version: %d)\n",
217 hose->global_number, be32_to_cpu(common->version));
219 pr_info("brdgCtl: %08x\n",
220 be32_to_cpu(data->brdgCtl));
221 if (data->portStatusReg || data->rootCmplxStatus ||
222 data->busAgentStatus)
223 pr_info("UtlSts: %08x %08x %08x\n",
224 be32_to_cpu(data->portStatusReg),
225 be32_to_cpu(data->rootCmplxStatus),
226 be32_to_cpu(data->busAgentStatus));
227 if (data->deviceStatus || data->slotStatus ||
228 data->linkStatus || data->devCmdStatus ||
230 pr_info("RootSts: %08x %08x %08x %08x %08x\n",
231 be32_to_cpu(data->deviceStatus),
232 be32_to_cpu(data->slotStatus),
233 be32_to_cpu(data->linkStatus),
234 be32_to_cpu(data->devCmdStatus),
235 be32_to_cpu(data->devSecStatus));
236 if (data->rootErrorStatus || data->uncorrErrorStatus ||
237 data->corrErrorStatus)
238 pr_info("RootErrSts: %08x %08x %08x\n",
239 be32_to_cpu(data->rootErrorStatus),
240 be32_to_cpu(data->uncorrErrorStatus),
241 be32_to_cpu(data->corrErrorStatus));
242 if (data->tlpHdr1 || data->tlpHdr2 ||
243 data->tlpHdr3 || data->tlpHdr4)
244 pr_info("RootErrLog: %08x %08x %08x %08x\n",
245 be32_to_cpu(data->tlpHdr1),
246 be32_to_cpu(data->tlpHdr2),
247 be32_to_cpu(data->tlpHdr3),
248 be32_to_cpu(data->tlpHdr4));
249 if (data->sourceId || data->errorClass ||
251 pr_info("RootErrLog1: %08x %016llx %016llx\n",
252 be32_to_cpu(data->sourceId),
253 be64_to_cpu(data->errorClass),
254 be64_to_cpu(data->correlator));
256 pr_info("nFir: %016llx %016llx %016llx\n",
257 be64_to_cpu(data->nFir),
258 be64_to_cpu(data->nFirMask),
259 be64_to_cpu(data->nFirWOF));
260 if (data->phbPlssr || data->phbCsr)
261 pr_info("PhbSts: %016llx %016llx\n",
262 be64_to_cpu(data->phbPlssr),
263 be64_to_cpu(data->phbCsr));
265 pr_info("Lem: %016llx %016llx %016llx\n",
266 be64_to_cpu(data->lemFir),
267 be64_to_cpu(data->lemErrorMask),
268 be64_to_cpu(data->lemWOF));
269 if (data->phbErrorStatus)
270 pr_info("PhbErr: %016llx %016llx %016llx %016llx\n",
271 be64_to_cpu(data->phbErrorStatus),
272 be64_to_cpu(data->phbFirstErrorStatus),
273 be64_to_cpu(data->phbErrorLog0),
274 be64_to_cpu(data->phbErrorLog1));
275 if (data->mmioErrorStatus)
276 pr_info("OutErr: %016llx %016llx %016llx %016llx\n",
277 be64_to_cpu(data->mmioErrorStatus),
278 be64_to_cpu(data->mmioFirstErrorStatus),
279 be64_to_cpu(data->mmioErrorLog0),
280 be64_to_cpu(data->mmioErrorLog1));
281 if (data->dma0ErrorStatus)
282 pr_info("InAErr: %016llx %016llx %016llx %016llx\n",
283 be64_to_cpu(data->dma0ErrorStatus),
284 be64_to_cpu(data->dma0FirstErrorStatus),
285 be64_to_cpu(data->dma0ErrorLog0),
286 be64_to_cpu(data->dma0ErrorLog1));
287 if (data->dma1ErrorStatus)
288 pr_info("InBErr: %016llx %016llx %016llx %016llx\n",
289 be64_to_cpu(data->dma1ErrorStatus),
290 be64_to_cpu(data->dma1FirstErrorStatus),
291 be64_to_cpu(data->dma1ErrorLog0),
292 be64_to_cpu(data->dma1ErrorLog1));
294 for (i = 0; i < OPAL_PHB3_NUM_PEST_REGS; i++) {
295 if ((be64_to_cpu(data->pestA[i]) >> 63) == 0 &&
296 (be64_to_cpu(data->pestB[i]) >> 63) == 0)
299 pr_info("PE[%3d] A/B: %016llx %016llx\n",
300 i, be64_to_cpu(data->pestA[i]),
301 be64_to_cpu(data->pestB[i]));
305 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
306 unsigned char *log_buff)
308 struct OpalIoPhbErrorCommon *common;
310 if (!hose || !log_buff)
313 common = (struct OpalIoPhbErrorCommon *)log_buff;
314 switch (be32_to_cpu(common->ioType)) {
315 case OPAL_PHB_ERROR_DATA_TYPE_P7IOC:
316 pnv_pci_dump_p7ioc_diag_data(hose, common);
318 case OPAL_PHB_ERROR_DATA_TYPE_PHB3:
319 pnv_pci_dump_phb3_diag_data(hose, common);
322 pr_warn("%s: Unrecognized ioType %d\n",
323 __func__, be32_to_cpu(common->ioType));
327 static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no)
329 unsigned long flags, rc;
330 int has_diag, ret = 0;
332 spin_lock_irqsave(&phb->lock, flags);
334 /* Fetch PHB diag-data */
335 rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
336 PNV_PCI_DIAG_BUF_SIZE);
337 has_diag = (rc == OPAL_SUCCESS);
339 /* If PHB supports compound PE, to handle it */
340 if (phb->unfreeze_pe) {
341 ret = phb->unfreeze_pe(phb,
343 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
345 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
347 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
349 pr_warn("%s: Failure %ld clearing frozen "
351 __func__, rc, phb->hose->global_number,
358 * For now, let's only display the diag buffer when we fail to clear
359 * the EEH status. We'll do more sensible things later when we have
360 * proper EEH support. We need to make sure we don't pollute ourselves
361 * with the normal errors generated when probing empty slots
364 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag.blob);
366 spin_unlock_irqrestore(&phb->lock, flags);
369 static void pnv_pci_config_check_eeh(struct pci_dn *pdn)
371 struct pnv_phb *phb = pdn->phb->private_data;
378 * Get the PE#. During the PCI probe stage, we might not
379 * setup that yet. So all ER errors should be mapped to
382 pe_no = pdn->pe_number;
383 if (pe_no == IODA_INVALID_PE) {
384 if (phb->type == PNV_PHB_P5IOC2)
387 pe_no = phb->ioda.reserved_pe;
391 * Fetch frozen state. If the PHB support compound PE,
392 * we need handle that case.
394 if (phb->get_pe_state) {
395 fstate = phb->get_pe_state(phb, pe_no);
397 rc = opal_pci_eeh_freeze_status(phb->opal_id,
403 pr_warn("%s: Failure %lld getting PHB#%x-PE#%x state\n",
404 __func__, rc, phb->hose->global_number, pe_no);
409 cfg_dbg(" -> EEH check, bdfn=%04x PE#%d fstate=%x\n",
410 (pdn->busno << 8) | (pdn->devfn), pe_no, fstate);
412 /* Clear the frozen state if applicable */
413 if (fstate == OPAL_EEH_STOPPED_MMIO_FREEZE ||
414 fstate == OPAL_EEH_STOPPED_DMA_FREEZE ||
415 fstate == OPAL_EEH_STOPPED_MMIO_DMA_FREEZE) {
417 * If PHB supports compound PE, freeze it for
421 phb->freeze_pe(phb, pe_no);
423 pnv_pci_handle_eeh_config(phb, pe_no);
427 int pnv_pci_cfg_read(struct pci_dn *pdn,
428 int where, int size, u32 *val)
430 struct pnv_phb *phb = pdn->phb->private_data;
431 u32 bdfn = (pdn->busno << 8) | pdn->devfn;
437 rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8);
438 *val = (rc == OPAL_SUCCESS) ? v8 : 0xff;
443 rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where,
445 *val = (rc == OPAL_SUCCESS) ? be16_to_cpu(v16) : 0xffff;
450 rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32);
451 *val = (rc == OPAL_SUCCESS) ? be32_to_cpu(v32) : 0xffffffff;
455 return PCIBIOS_FUNC_NOT_SUPPORTED;
458 cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
459 __func__, pdn->busno, pdn->devfn, where, size, *val);
460 return PCIBIOS_SUCCESSFUL;
463 int pnv_pci_cfg_write(struct pci_dn *pdn,
464 int where, int size, u32 val)
466 struct pnv_phb *phb = pdn->phb->private_data;
467 u32 bdfn = (pdn->busno << 8) | pdn->devfn;
469 cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
470 pdn->busno, pdn->devfn, where, size, val);
473 opal_pci_config_write_byte(phb->opal_id, bdfn, where, val);
476 opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val);
479 opal_pci_config_write_word(phb->opal_id, bdfn, where, val);
482 return PCIBIOS_FUNC_NOT_SUPPORTED;
485 return PCIBIOS_SUCCESSFUL;
489 static bool pnv_pci_cfg_check(struct pci_dn *pdn)
491 struct eeh_dev *edev = NULL;
492 struct pnv_phb *phb = pdn->phb->private_data;
494 /* EEH not enabled ? */
495 if (!(phb->flags & PNV_PHB_FLAG_EEH))
498 /* PE reset or device removed ? */
502 (edev->pe->state & EEH_PE_CFG_BLOCKED))
505 if (edev->mode & EEH_DEV_REMOVED)
512 static inline pnv_pci_cfg_check(struct pci_dn *pdn)
516 #endif /* CONFIG_EEH */
518 static int pnv_pci_read_config(struct pci_bus *bus,
520 int where, int size, u32 *val)
527 pdn = pci_get_pdn_by_devfn(bus, devfn);
529 return PCIBIOS_DEVICE_NOT_FOUND;
531 if (!pnv_pci_cfg_check(pdn))
532 return PCIBIOS_DEVICE_NOT_FOUND;
534 ret = pnv_pci_cfg_read(pdn, where, size, val);
535 phb = pdn->phb->private_data;
536 if (phb->flags & PNV_PHB_FLAG_EEH && pdn->edev) {
537 if (*val == EEH_IO_ERROR_VALUE(size) &&
538 eeh_dev_check_failure(pdn->edev))
539 return PCIBIOS_DEVICE_NOT_FOUND;
541 pnv_pci_config_check_eeh(pdn);
547 static int pnv_pci_write_config(struct pci_bus *bus,
549 int where, int size, u32 val)
555 pdn = pci_get_pdn_by_devfn(bus, devfn);
557 return PCIBIOS_DEVICE_NOT_FOUND;
559 if (!pnv_pci_cfg_check(pdn))
560 return PCIBIOS_DEVICE_NOT_FOUND;
562 ret = pnv_pci_cfg_write(pdn, where, size, val);
563 phb = pdn->phb->private_data;
564 if (!(phb->flags & PNV_PHB_FLAG_EEH))
565 pnv_pci_config_check_eeh(pdn);
570 struct pci_ops pnv_pci_ops = {
571 .read = pnv_pci_read_config,
572 .write = pnv_pci_write_config,
575 static __be64 *pnv_tce(struct iommu_table *tbl, long idx)
577 __be64 *tmp = ((__be64 *)tbl->it_base);
578 int level = tbl->it_indirect_levels;
579 const long shift = ilog2(tbl->it_level_size);
580 unsigned long mask = (tbl->it_level_size - 1) << (level * shift);
583 int n = (idx & mask) >> (level * shift);
584 unsigned long tce = be64_to_cpu(tmp[n]);
586 tmp = __va(tce & ~(TCE_PCI_READ | TCE_PCI_WRITE));
595 int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
596 unsigned long uaddr, enum dma_data_direction direction,
597 struct dma_attrs *attrs)
599 u64 proto_tce = iommu_direction_to_tce_perm(direction);
600 u64 rpn = __pa(uaddr) >> tbl->it_page_shift;
603 for (i = 0; i < npages; i++) {
604 unsigned long newtce = proto_tce |
605 ((rpn + i) << tbl->it_page_shift);
606 unsigned long idx = index - tbl->it_offset + i;
608 *(pnv_tce(tbl, idx)) = cpu_to_be64(newtce);
614 #ifdef CONFIG_IOMMU_API
615 int pnv_tce_xchg(struct iommu_table *tbl, long index,
616 unsigned long *hpa, enum dma_data_direction *direction)
618 u64 proto_tce = iommu_direction_to_tce_perm(*direction);
619 unsigned long newtce = *hpa | proto_tce, oldtce;
620 unsigned long idx = index - tbl->it_offset;
622 BUG_ON(*hpa & ~IOMMU_PAGE_MASK(tbl));
624 oldtce = xchg(pnv_tce(tbl, idx), cpu_to_be64(newtce));
625 *hpa = be64_to_cpu(oldtce) & ~(TCE_PCI_READ | TCE_PCI_WRITE);
626 *direction = iommu_tce_direction(oldtce);
632 void pnv_tce_free(struct iommu_table *tbl, long index, long npages)
636 for (i = 0; i < npages; i++) {
637 unsigned long idx = index - tbl->it_offset + i;
639 *(pnv_tce(tbl, idx)) = cpu_to_be64(0);
643 unsigned long pnv_tce_get(struct iommu_table *tbl, long index)
645 return *(pnv_tce(tbl, index - tbl->it_offset));
648 struct iommu_table *pnv_pci_table_alloc(int nid)
650 struct iommu_table *tbl;
652 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, nid);
653 INIT_LIST_HEAD_RCU(&tbl->it_group_list);
658 long pnv_pci_link_table_and_group(int node, int num,
659 struct iommu_table *tbl,
660 struct iommu_table_group *table_group)
662 struct iommu_table_group_link *tgl = NULL;
664 if (WARN_ON(!tbl || !table_group))
667 tgl = kzalloc_node(sizeof(struct iommu_table_group_link), GFP_KERNEL,
672 tgl->table_group = table_group;
673 list_add_rcu(&tgl->next, &tbl->it_group_list);
675 table_group->tables[num] = tbl;
680 static void pnv_iommu_table_group_link_free(struct rcu_head *head)
682 struct iommu_table_group_link *tgl = container_of(head,
683 struct iommu_table_group_link, rcu);
688 void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
689 struct iommu_table_group *table_group)
693 struct iommu_table_group_link *tgl;
695 if (!tbl || !table_group)
698 /* Remove link to a group from table's list of attached groups */
700 list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) {
701 if (tgl->table_group == table_group) {
702 list_del_rcu(&tgl->next);
703 call_rcu(&tgl->rcu, pnv_iommu_table_group_link_free);
711 /* Clean a pointer to iommu_table in iommu_table_group::tables[] */
713 for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i) {
714 if (table_group->tables[i] == tbl) {
715 table_group->tables[i] = NULL;
723 void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
724 void *tce_mem, u64 tce_size,
725 u64 dma_offset, unsigned page_shift)
727 tbl->it_blocksize = 16;
728 tbl->it_base = (unsigned long)tce_mem;
729 tbl->it_page_shift = page_shift;
730 tbl->it_offset = dma_offset >> tbl->it_page_shift;
732 tbl->it_size = tce_size >> 3;
734 tbl->it_type = TCE_PCI;
737 void pnv_pci_dma_dev_setup(struct pci_dev *pdev)
739 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
740 struct pnv_phb *phb = hose->private_data;
741 #ifdef CONFIG_PCI_IOV
742 struct pnv_ioda_pe *pe;
745 /* Fix the VF pdn PE number */
746 if (pdev->is_virtfn) {
747 pdn = pci_get_pdn(pdev);
748 WARN_ON(pdn->pe_number != IODA_INVALID_PE);
749 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
750 if (pe->rid == ((pdev->bus->number << 8) |
751 (pdev->devfn & 0xff))) {
752 pdn->pe_number = pe->pe_number;
758 #endif /* CONFIG_PCI_IOV */
760 if (phb && phb->dma_dev_setup)
761 phb->dma_dev_setup(phb, pdev);
764 void pnv_pci_shutdown(void)
766 struct pci_controller *hose;
768 list_for_each_entry(hose, &hose_list, list_node)
769 if (hose->controller_ops.shutdown)
770 hose->controller_ops.shutdown(hose);
773 /* Fixup wrong class code in p7ioc and p8 root complex */
774 static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
776 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
778 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk);
780 void __init pnv_pci_init(void)
782 struct device_node *np;
783 bool found_ioda = false;
785 pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN);
787 /* If we don't have OPAL, eg. in sim, just skip PCI probe */
788 if (!firmware_has_feature(FW_FEATURE_OPAL))
791 /* Look for IODA IO-Hubs. We don't support mixing IODA
792 * and p5ioc2 due to the need to change some global
795 for_each_compatible_node(np, NULL, "ibm,ioda-hub") {
796 pnv_pci_init_ioda_hub(np);
800 /* Look for p5ioc2 IO-Hubs */
802 for_each_compatible_node(np, NULL, "ibm,p5ioc2")
803 pnv_pci_init_p5ioc2_hub(np);
805 /* Look for ioda2 built-in PHB3's */
806 for_each_compatible_node(np, NULL, "ibm,ioda2-phb")
807 pnv_pci_init_ioda2_phb(np);
809 /* Setup the linkage between OF nodes and PHBs */
812 /* Configure IOMMU DMA hooks */
813 set_pci_dma_ops(&dma_iommu_ops);
816 machine_subsys_initcall_sync(powernv, tce_iommu_bus_notifier_init);