arch/powerpc/platforms/powernv/pci.c

   1 /*
   2  * Support PCI/PCIe on PowerNV platforms
   3  *
   4  * Currently supports only P5IOC2
   5  *
   6  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version
  11  * 2 of the License, or (at your option) any later version.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/delay.h>
  17 #include <linux/string.h>
  18 #include <linux/init.h>
  19 #include <linux/bootmem.h>
  20 #include <linux/irq.h>
  21 #include <linux/io.h>
  22 #include <linux/msi.h>
  23 #include <linux/iommu.h>
  24
  25 #include <asm/sections.h>
  26 #include <asm/io.h>
  27 #include <asm/prom.h>
  28 #include <asm/pci-bridge.h>
  29 #include <asm/machdep.h>
  30 #include <asm/msi_bitmap.h>
  31 #include <asm/ppc-pci.h>
  32 #include <asm/opal.h>
  33 #include <asm/iommu.h>
  34 #include <asm/tce.h>
  35 #include <asm/firmware.h>
  36 #include <asm/eeh_event.h>
  37 #include <asm/eeh.h>
  38
  39 #include "powernv.h"
  40 #include "pci.h"
  41
  42 /* Delay in usec */
  43 #define PCI_RESET_DELAY_US      3000000
  44
  45 #define cfg_dbg(fmt...) do { } while(0)
  46 //#define cfg_dbg(fmt...)       printk(fmt)
  47
  48 #ifdef CONFIG_PCI_MSI
  49 static int pnv_msi_check_device(struct pci_dev* pdev, int nvec, int type)
  50 {
  51         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
  52         struct pnv_phb *phb = hose->private_data;
  53         struct pci_dn *pdn = pci_get_pdn(pdev);
  54
  55         if (pdn && pdn->force_32bit_msi && !phb->msi32_support)
  56                 return -ENODEV;
  57
  58         return (phb && phb->msi_bmp.bitmap) ? 0 : -ENODEV;
  59 }
  60
  61 static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
  62 {
  63         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
  64         struct pnv_phb *phb = hose->private_data;
  65         struct msi_desc *entry;
  66         struct msi_msg msg;
  67         int hwirq;
  68         unsigned int virq;
  69         int rc;
  70
  71         if (WARN_ON(!phb))
  72                 return -ENODEV;
  73
  74         list_for_each_entry(entry, &pdev->msi_list, list) {
  75                 if (!entry->msi_attrib.is_64 && !phb->msi32_support) {
  76                         pr_warn("%s: Supports only 64-bit MSIs\n",
  77                                 pci_name(pdev));
  78                         return -ENXIO;
  79                 }
  80                 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1);
  81                 if (hwirq < 0) {
  82                         pr_warn("%s: Failed to find a free MSI\n",
  83                                 pci_name(pdev));
  84                         return -ENOSPC;
  85                 }
  86                 virq = irq_create_mapping(NULL, phb->msi_base + hwirq);
  87                 if (virq == NO_IRQ) {
  88                         pr_warn("%s: Failed to map MSI to linux irq\n",
  89                                 pci_name(pdev));
  90                         msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
  91                         return -ENOMEM;
  92                 }
  93                 rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq,
  94                                     virq, entry->msi_attrib.is_64, &msg);
  95                 if (rc) {
  96                         pr_warn("%s: Failed to setup MSI\n", pci_name(pdev));
  97                         irq_dispose_mapping(virq);
  98                         msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
  99                         return rc;
 100                 }
 101                 irq_set_msi_desc(virq, entry);
 102                 write_msi_msg(virq, &msg);
 103         }
 104         return 0;
 105 }
 106
 107 static void pnv_teardown_msi_irqs(struct pci_dev *pdev)
 108 {
 109         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
 110         struct pnv_phb *phb = hose->private_data;
 111         struct msi_desc *entry;
 112
 113         if (WARN_ON(!phb))
 114                 return;
 115
 116         list_for_each_entry(entry, &pdev->msi_list, list) {
 117                 if (entry->irq == NO_IRQ)
 118                         continue;
 119                 irq_set_msi_desc(entry->irq, NULL);
 120                 msi_bitmap_free_hwirqs(&phb->msi_bmp,
 121                         virq_to_hw(entry->irq) - phb->msi_base, 1);
 122                 irq_dispose_mapping(entry->irq);
 123         }
 124 }
 125 #endif /* CONFIG_PCI_MSI */
 126
 127 static void pnv_pci_dump_p7ioc_diag_data(struct pci_controller *hose,
 128                                          struct OpalIoPhbErrorCommon *common)
 129 {
 130         struct OpalIoP7IOCPhbErrorData *data;
 131         int i;
 132
 133         data = (struct OpalIoP7IOCPhbErrorData *)common;
 134         pr_info("P7IOC PHB#%d Diag-data (Version: %d)\n",
 135                 hose->global_number, common->version);
 136
 137         if (data->brdgCtl)
 138                 pr_info("brdgCtl:     %08x\n",
 139                         data->brdgCtl);
 140         if (data->portStatusReg || data->rootCmplxStatus ||
 141             data->busAgentStatus)
 142                 pr_info("UtlSts:      %08x %08x %08x\n",
 143                         data->portStatusReg, data->rootCmplxStatus,
 144                         data->busAgentStatus);
 145         if (data->deviceStatus || data->slotStatus   ||
 146             data->linkStatus   || data->devCmdStatus ||
 147             data->devSecStatus)
 148                 pr_info("RootSts:     %08x %08x %08x %08x %08x\n",
 149                         data->deviceStatus, data->slotStatus,
 150                         data->linkStatus, data->devCmdStatus,
 151                         data->devSecStatus);
 152         if (data->rootErrorStatus   || data->uncorrErrorStatus ||
 153             data->corrErrorStatus)
 154                 pr_info("RootErrSts:  %08x %08x %08x\n",
 155                         data->rootErrorStatus, data->uncorrErrorStatus,
 156                         data->corrErrorStatus);
 157         if (data->tlpHdr1 || data->tlpHdr2 ||
 158             data->tlpHdr3 || data->tlpHdr4)
 159                 pr_info("RootErrLog:  %08x %08x %08x %08x\n",
 160                         data->tlpHdr1, data->tlpHdr2,
 161                         data->tlpHdr3, data->tlpHdr4);
 162         if (data->sourceId || data->errorClass ||
 163             data->correlator)
 164                 pr_info("RootErrLog1: %08x %016llx %016llx\n",
 165                         data->sourceId, data->errorClass,
 166                         data->correlator);
 167         if (data->p7iocPlssr || data->p7iocCsr)
 168                 pr_info("PhbSts:      %016llx %016llx\n",
 169                         data->p7iocPlssr, data->p7iocCsr);
 170         if (data->lemFir)
 171                 pr_info("Lem:         %016llx %016llx %016llx\n",
 172                         data->lemFir, data->lemErrorMask,
 173                         data->lemWOF);
 174         if (data->phbErrorStatus)
 175                 pr_info("PhbErr:      %016llx %016llx %016llx %016llx\n",
 176                         data->phbErrorStatus, data->phbFirstErrorStatus,
 177                         data->phbErrorLog0, data->phbErrorLog1);
 178         if (data->mmioErrorStatus)
 179                 pr_info("OutErr:      %016llx %016llx %016llx %016llx\n",
 180                         data->mmioErrorStatus, data->mmioFirstErrorStatus,
 181                         data->mmioErrorLog0, data->mmioErrorLog1);
 182         if (data->dma0ErrorStatus)
 183                 pr_info("InAErr:      %016llx %016llx %016llx %016llx\n",
 184                         data->dma0ErrorStatus, data->dma0FirstErrorStatus,
 185                         data->dma0ErrorLog0, data->dma0ErrorLog1);
 186         if (data->dma1ErrorStatus)
 187                 pr_info("InBErr:      %016llx %016llx %016llx %016llx\n",
 188                         data->dma1ErrorStatus, data->dma1FirstErrorStatus,
 189                         data->dma1ErrorLog0, data->dma1ErrorLog1);
 190
 191         for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) {
 192                 if ((data->pestA[i] >> 63) == 0 &&
 193                     (data->pestB[i] >> 63) == 0)
 194                         continue;
 195
 196                 pr_info("PE[%3d] A/B: %016llx %016llx\n",
 197                         i, data->pestA[i], data->pestB[i]);
 198         }
 199 }
 200
 201 static void pnv_pci_dump_phb3_diag_data(struct pci_controller *hose,
 202                                         struct OpalIoPhbErrorCommon *common)
 203 {
 204         struct OpalIoPhb3ErrorData *data;
 205         int i;
 206
 207         data = (struct OpalIoPhb3ErrorData*)common;
 208         pr_info("PHB3 PHB#%d Diag-data (Version: %d)\n",
 209                 hose->global_number, common->version);
 210         if (data->brdgCtl)
 211                 pr_info("brdgCtl:     %08x\n",
 212                         data->brdgCtl);
 213         if (data->portStatusReg || data->rootCmplxStatus ||
 214             data->busAgentStatus)
 215                 pr_info("UtlSts:      %08x %08x %08x\n",
 216                         data->portStatusReg, data->rootCmplxStatus,
 217                         data->busAgentStatus);
 218         if (data->deviceStatus || data->slotStatus   ||
 219             data->linkStatus   || data->devCmdStatus ||
 220             data->devSecStatus)
 221                 pr_info("RootSts:     %08x %08x %08x %08x %08x\n",
 222                         data->deviceStatus, data->slotStatus,
 223                         data->linkStatus, data->devCmdStatus,
 224                         data->devSecStatus);
 225         if (data->rootErrorStatus || data->uncorrErrorStatus ||
 226             data->corrErrorStatus)
 227                 pr_info("RootErrSts:  %08x %08x %08x\n",
 228                         data->rootErrorStatus, data->uncorrErrorStatus,
 229                         data->corrErrorStatus);
 230         if (data->tlpHdr1 || data->tlpHdr2 ||
 231             data->tlpHdr3 || data->tlpHdr4)
 232                 pr_info("RootErrLog:  %08x %08x %08x %08x\n",
 233                         data->tlpHdr1, data->tlpHdr2,
 234                         data->tlpHdr3, data->tlpHdr4);
 235         if (data->sourceId || data->errorClass ||
 236             data->correlator)
 237                 pr_info("RootErrLog1: %08x %016llx %016llx\n",
 238                         data->sourceId, data->errorClass,
 239                         data->correlator);
 240         if (data->nFir)
 241                 pr_info("nFir:        %016llx %016llx %016llx\n",
 242                         data->nFir, data->nFirMask,
 243                         data->nFirWOF);
 244         if (data->phbPlssr || data->phbCsr)
 245                 pr_info("PhbSts:      %016llx %016llx\n",
 246                         data->phbPlssr, data->phbCsr);
 247         if (data->lemFir)
 248                 pr_info("Lem:         %016llx %016llx %016llx\n",
 249                         data->lemFir, data->lemErrorMask,
 250                         data->lemWOF);
 251         if (data->phbErrorStatus)
 252                 pr_info("PhbErr:      %016llx %016llx %016llx %016llx\n",
 253                         data->phbErrorStatus, data->phbFirstErrorStatus,
 254                         data->phbErrorLog0, data->phbErrorLog1);
 255         if (data->mmioErrorStatus)
 256                 pr_info("OutErr:      %016llx %016llx %016llx %016llx\n",
 257                         data->mmioErrorStatus, data->mmioFirstErrorStatus,
 258                         data->mmioErrorLog0, data->mmioErrorLog1);
 259         if (data->dma0ErrorStatus)
 260                 pr_info("InAErr:      %016llx %016llx %016llx %016llx\n",
 261                         data->dma0ErrorStatus, data->dma0FirstErrorStatus,
 262                         data->dma0ErrorLog0, data->dma0ErrorLog1);
 263         if (data->dma1ErrorStatus)
 264                 pr_info("InBErr:      %016llx %016llx %016llx %016llx\n",
 265                         data->dma1ErrorStatus, data->dma1FirstErrorStatus,
 266                         data->dma1ErrorLog0, data->dma1ErrorLog1);
 267
 268         for (i = 0; i < OPAL_PHB3_NUM_PEST_REGS; i++) {
 269                 if ((data->pestA[i] >> 63) == 0 &&
 270                     (data->pestB[i] >> 63) == 0)
 271                         continue;
 272
 273                 pr_info("PE[%3d] A/B: %016llx %016llx\n",
 274                         i, data->pestA[i], data->pestB[i]);
 275         }
 276 }
 277
 278 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
 279                                 unsigned char *log_buff)
 280 {
 281         struct OpalIoPhbErrorCommon *common;
 282
 283         if (!hose || !log_buff)
 284                 return;
 285
 286         common = (struct OpalIoPhbErrorCommon *)log_buff;
 287         switch (common->ioType) {
 288         case OPAL_PHB_ERROR_DATA_TYPE_P7IOC:
 289                 pnv_pci_dump_p7ioc_diag_data(hose, common);
 290                 break;
 291         case OPAL_PHB_ERROR_DATA_TYPE_PHB3:
 292                 pnv_pci_dump_phb3_diag_data(hose, common);
 293                 break;
 294         default:
 295                 pr_warn("%s: Unrecognized ioType %d\n",
 296                         __func__, common->ioType);
 297         }
 298 }
 299
 300 static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no)
 301 {
 302         unsigned long flags, rc;
 303         int has_diag;
 304
 305         spin_lock_irqsave(&phb->lock, flags);
 306
 307         rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
 308                                          PNV_PCI_DIAG_BUF_SIZE);
 309         has_diag = (rc == OPAL_SUCCESS);
 310
 311         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
 312                                        OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 313         if (rc) {
 314                 pr_warning("PCI %d: Failed to clear EEH freeze state"
 315                            " for PE#%d, err %ld\n",
 316                            phb->hose->global_number, pe_no, rc);
 317
 318                 /* For now, let's only display the diag buffer when we fail to clear
 319                  * the EEH status. We'll do more sensible things later when we have
 320                  * proper EEH support. We need to make sure we don't pollute ourselves
 321                  * with the normal errors generated when probing empty slots
 322                  */
 323                 if (has_diag)
 324                         pnv_pci_dump_phb_diag_data(phb->hose, phb->diag.blob);
 325                 else
 326                         pr_warning("PCI %d: No diag data available\n",
 327                                    phb->hose->global_number);
 328         }
 329
 330         spin_unlock_irqrestore(&phb->lock, flags);
 331 }
 332
 333 static void pnv_pci_config_check_eeh(struct pnv_phb *phb,
 334                                      struct device_node *dn)
 335 {
 336         s64     rc;
 337         u8      fstate;
 338         __be16  pcierr;
 339         u32     pe_no;
 340
 341         /*
 342          * Get the PE#. During the PCI probe stage, we might not
 343          * setup that yet. So all ER errors should be mapped to
 344          * reserved PE.
 345          */
 346         pe_no = PCI_DN(dn)->pe_number;
 347         if (pe_no == IODA_INVALID_PE) {
 348                 if (phb->type == PNV_PHB_P5IOC2)
 349                         pe_no = 0;
 350                 else
 351                         pe_no = phb->ioda.reserved_pe;
 352         }
 353
 354         /* Read freeze status */
 355         rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, &fstate, &pcierr,
 356                                         NULL);
 357         if (rc) {
 358                 pr_warning("%s: Can't read EEH status (PE#%d) for "
 359                            "%s, err %lld\n",
 360                            __func__, pe_no, dn->full_name, rc);
 361                 return;
 362         }
 363         cfg_dbg(" -> EEH check, bdfn=%04x PE#%d fstate=%x\n",
 364                 (PCI_DN(dn)->busno << 8) | (PCI_DN(dn)->devfn),
 365                 pe_no, fstate);
 366         if (fstate != 0)
 367                 pnv_pci_handle_eeh_config(phb, pe_no);
 368 }
 369
 370 int pnv_pci_cfg_read(struct device_node *dn,
 371                      int where, int size, u32 *val)
 372 {
 373         struct pci_dn *pdn = PCI_DN(dn);
 374         struct pnv_phb *phb = pdn->phb->private_data;
 375         u32 bdfn = (pdn->busno << 8) | pdn->devfn;
 376         s64 rc;
 377
 378         switch (size) {
 379         case 1: {
 380                 u8 v8;
 381                 rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8);
 382                 *val = (rc == OPAL_SUCCESS) ? v8 : 0xff;
 383                 break;
 384         }
 385         case 2: {
 386                 __be16 v16;
 387                 rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where,
 388                                                    &v16);
 389                 *val = (rc == OPAL_SUCCESS) ? be16_to_cpu(v16) : 0xffff;
 390                 break;
 391         }
 392         case 4: {
 393                 __be32 v32;
 394                 rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32);
 395                 *val = (rc == OPAL_SUCCESS) ? be32_to_cpu(v32) : 0xffffffff;
 396                 break;
 397         }
 398         default:
 399                 return PCIBIOS_FUNC_NOT_SUPPORTED;
 400         }
 401
 402         cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
 403                 __func__, pdn->busno, pdn->devfn, where, size, *val);
 404         return PCIBIOS_SUCCESSFUL;
 405 }
 406
 407 int pnv_pci_cfg_write(struct device_node *dn,
 408                       int where, int size, u32 val)
 409 {
 410         struct pci_dn *pdn = PCI_DN(dn);
 411         struct pnv_phb *phb = pdn->phb->private_data;
 412         u32 bdfn = (pdn->busno << 8) | pdn->devfn;
 413
 414         cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
 415                 pdn->busno, pdn->devfn, where, size, val);
 416         switch (size) {
 417         case 1:
 418                 opal_pci_config_write_byte(phb->opal_id, bdfn, where, val);
 419                 break;
 420         case 2:
 421                 opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val);
 422                 break;
 423         case 4:
 424                 opal_pci_config_write_word(phb->opal_id, bdfn, where, val);
 425                 break;
 426         default:
 427                 return PCIBIOS_FUNC_NOT_SUPPORTED;
 428         }
 429
 430         return PCIBIOS_SUCCESSFUL;
 431 }
 432
 433 #if CONFIG_EEH
 434 static bool pnv_pci_cfg_check(struct pci_controller *hose,
 435                               struct device_node *dn)
 436 {
 437         struct eeh_dev *edev = NULL;
 438         struct pnv_phb *phb = hose->private_data;
 439
 440         /* EEH not enabled ? */
 441         if (!(phb->flags & PNV_PHB_FLAG_EEH))
 442                 return true;
 443
 444         /* PE reset or device removed ? */
 445         edev = of_node_to_eeh_dev(dn);
 446         if (edev) {
 447                 if (edev->pe &&
 448                     (edev->pe->state & EEH_PE_RESET))
 449                         return false;
 450
 451                 if (edev->mode & EEH_DEV_REMOVED)
 452                         return false;
 453         }
 454
 455         return true;
 456 }
 457 #else
 458 static inline pnv_pci_cfg_check(struct pci_controller *hose,
 459                                 struct device_node *dn)
 460 {
 461         return true;
 462 }
 463 #endif /* CONFIG_EEH */
 464
 465 static int pnv_pci_read_config(struct pci_bus *bus,
 466                                unsigned int devfn,
 467                                int where, int size, u32 *val)
 468 {
 469         struct device_node *dn, *busdn = pci_bus_to_OF_node(bus);
 470         struct pci_dn *pdn;
 471         struct pnv_phb *phb;
 472         bool found = false;
 473         int ret;
 474
 475         *val = 0xFFFFFFFF;
 476         for (dn = busdn->child; dn; dn = dn->sibling) {
 477                 pdn = PCI_DN(dn);
 478                 if (pdn && pdn->devfn == devfn) {
 479                         phb = pdn->phb->private_data;
 480                         found = true;
 481                         break;
 482                 }
 483         }
 484
 485         if (!found || !pnv_pci_cfg_check(pdn->phb, dn))
 486                 return PCIBIOS_DEVICE_NOT_FOUND;
 487
 488         ret = pnv_pci_cfg_read(dn, where, size, val);
 489         if (phb->flags & PNV_PHB_FLAG_EEH) {
 490                 if (*val == EEH_IO_ERROR_VALUE(size) &&
 491                     eeh_dev_check_failure(of_node_to_eeh_dev(dn)))
 492                         return PCIBIOS_DEVICE_NOT_FOUND;
 493         } else {
 494                 pnv_pci_config_check_eeh(phb, dn);
 495         }
 496
 497         return ret;
 498 }
 499
 500 static int pnv_pci_write_config(struct pci_bus *bus,
 501                                 unsigned int devfn,
 502                                 int where, int size, u32 val)
 503 {
 504         struct device_node *dn, *busdn = pci_bus_to_OF_node(bus);
 505         struct pci_dn *pdn;
 506         struct pnv_phb *phb;
 507         bool found = false;
 508         int ret;
 509
 510         for (dn = busdn->child; dn; dn = dn->sibling) {
 511                 pdn = PCI_DN(dn);
 512                 if (pdn && pdn->devfn == devfn) {
 513                         phb = pdn->phb->private_data;
 514                         found = true;
 515                         break;
 516                 }
 517         }
 518
 519         if (!found || !pnv_pci_cfg_check(pdn->phb, dn))
 520                 return PCIBIOS_DEVICE_NOT_FOUND;
 521
 522         ret = pnv_pci_cfg_write(dn, where, size, val);
 523         if (!(phb->flags & PNV_PHB_FLAG_EEH))
 524                 pnv_pci_config_check_eeh(phb, dn);
 525
 526         return ret;
 527 }
 528
 529 struct pci_ops pnv_pci_ops = {
 530         .read  = pnv_pci_read_config,
 531         .write = pnv_pci_write_config,
 532 };
 533
 534 static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
 535                          unsigned long uaddr, enum dma_data_direction direction,
 536                          struct dma_attrs *attrs, bool rm)
 537 {
 538         u64 proto_tce;
 539         __be64 *tcep, *tces;
 540         u64 rpn;
 541
 542         proto_tce = TCE_PCI_READ; // Read allowed
 543
 544         if (direction != DMA_TO_DEVICE)
 545                 proto_tce |= TCE_PCI_WRITE;
 546
 547         tces = tcep = ((__be64 *)tbl->it_base) + index - tbl->it_offset;
 548         rpn = __pa(uaddr) >> TCE_SHIFT;
 549
 550         while (npages--)
 551                 *(tcep++) = cpu_to_be64(proto_tce | (rpn++ << TCE_RPN_SHIFT));
 552
 553         /* Some implementations won't cache invalid TCEs and thus may not
 554          * need that flush. We'll probably turn it_type into a bit mask
 555          * of flags if that becomes the case
 556          */
 557         if (tbl->it_type & TCE_PCI_SWINV_CREATE)
 558                 pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1, rm);
 559
 560         return 0;
 561 }
 562
 563 static int pnv_tce_build_vm(struct iommu_table *tbl, long index, long npages,
 564                             unsigned long uaddr,
 565                             enum dma_data_direction direction,
 566                             struct dma_attrs *attrs)
 567 {
 568         return pnv_tce_build(tbl, index, npages, uaddr, direction, attrs,
 569                         false);
 570 }
 571
 572 static void pnv_tce_free(struct iommu_table *tbl, long index, long npages,
 573                 bool rm)
 574 {
 575         __be64 *tcep, *tces;
 576
 577         tces = tcep = ((__be64 *)tbl->it_base) + index - tbl->it_offset;
 578
 579         while (npages--)
 580                 *(tcep++) = cpu_to_be64(0);
 581
 582         if (tbl->it_type & TCE_PCI_SWINV_FREE)
 583                 pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1, rm);
 584 }
 585
 586 static void pnv_tce_free_vm(struct iommu_table *tbl, long index, long npages)
 587 {
 588         pnv_tce_free(tbl, index, npages, false);
 589 }
 590
 591 static unsigned long pnv_tce_get(struct iommu_table *tbl, long index)
 592 {
 593         return ((u64 *)tbl->it_base)[index - tbl->it_offset];
 594 }
 595
 596 static int pnv_tce_build_rm(struct iommu_table *tbl, long index, long npages,
 597                             unsigned long uaddr,
 598                             enum dma_data_direction direction,
 599                             struct dma_attrs *attrs)
 600 {
 601         return pnv_tce_build(tbl, index, npages, uaddr, direction, attrs, true);
 602 }
 603
 604 static void pnv_tce_free_rm(struct iommu_table *tbl, long index, long npages)
 605 {
 606         pnv_tce_free(tbl, index, npages, true);
 607 }
 608
 609 void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
 610                                void *tce_mem, u64 tce_size,
 611                                u64 dma_offset)
 612 {
 613         tbl->it_blocksize = 16;
 614         tbl->it_base = (unsigned long)tce_mem;
 615         tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K;
 616         tbl->it_offset = dma_offset >> tbl->it_page_shift;
 617         tbl->it_index = 0;
 618         tbl->it_size = tce_size >> 3;
 619         tbl->it_busno = 0;
 620         tbl->it_type = TCE_PCI;
 621 }
 622
 623 static struct iommu_table *pnv_pci_setup_bml_iommu(struct pci_controller *hose)
 624 {
 625         struct iommu_table *tbl;
 626         const __be64 *basep, *swinvp;
 627         const __be32 *sizep;
 628
 629         basep = of_get_property(hose->dn, "linux,tce-base", NULL);
 630         sizep = of_get_property(hose->dn, "linux,tce-size", NULL);
 631         if (basep == NULL || sizep == NULL) {
 632                 pr_err("PCI: %s has missing tce entries !\n",
 633                        hose->dn->full_name);
 634                 return NULL;
 635         }
 636         tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node);
 637         if (WARN_ON(!tbl))
 638                 return NULL;
 639         pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)),
 640                                   be32_to_cpup(sizep), 0);
 641         iommu_init_table(tbl, hose->node);
 642         iommu_register_group(tbl, pci_domain_nr(hose->bus), 0);
 643
 644         /* Deal with SW invalidated TCEs when needed (BML way) */
 645         swinvp = of_get_property(hose->dn, "linux,tce-sw-invalidate-info",
 646                                  NULL);
 647         if (swinvp) {
 648                 tbl->it_busno = be64_to_cpu(swinvp[1]);
 649                 tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8);
 650                 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
 651         }
 652         return tbl;
 653 }
 654
 655 static void pnv_pci_dma_fallback_setup(struct pci_controller *hose,
 656                                        struct pci_dev *pdev)
 657 {
 658         struct device_node *np = pci_bus_to_OF_node(hose->bus);
 659         struct pci_dn *pdn;
 660
 661         if (np == NULL)
 662                 return;
 663         pdn = PCI_DN(np);
 664         if (!pdn->iommu_table)
 665                 pdn->iommu_table = pnv_pci_setup_bml_iommu(hose);
 666         if (!pdn->iommu_table)
 667                 return;
 668         set_iommu_table_base_and_group(&pdev->dev, pdn->iommu_table);
 669 }
 670
 671 static void pnv_pci_dma_dev_setup(struct pci_dev *pdev)
 672 {
 673         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
 674         struct pnv_phb *phb = hose->private_data;
 675
 676         /* If we have no phb structure, try to setup a fallback based on
 677          * the device-tree (RTAS PCI for example)
 678          */
 679         if (phb && phb->dma_dev_setup)
 680                 phb->dma_dev_setup(phb, pdev);
 681         else
 682                 pnv_pci_dma_fallback_setup(hose, pdev);
 683 }
 684
 685 int pnv_pci_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
 686 {
 687         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
 688         struct pnv_phb *phb = hose->private_data;
 689
 690         if (phb && phb->dma_set_mask)
 691                 return phb->dma_set_mask(phb, pdev, dma_mask);
 692         return __dma_set_mask(&pdev->dev, dma_mask);
 693 }
 694
 695 void pnv_pci_shutdown(void)
 696 {
 697         struct pci_controller *hose;
 698
 699         list_for_each_entry(hose, &hose_list, list_node) {
 700                 struct pnv_phb *phb = hose->private_data;
 701
 702                 if (phb && phb->shutdown)
 703                         phb->shutdown(phb);
 704         }
 705 }
 706
 707 /* Fixup wrong class code in p7ioc and p8 root complex */
 708 static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
 709 {
 710         dev->class = PCI_CLASS_BRIDGE_PCI << 8;
 711 }
 712 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk);
 713
 714 static int pnv_pci_probe_mode(struct pci_bus *bus)
 715 {
 716         struct pci_controller *hose = pci_bus_to_host(bus);
 717         const __be64 *tstamp;
 718         u64 now, target;
 719
 720
 721         /* We hijack this as a way to ensure we have waited long
 722          * enough since the reset was lifted on the PCI bus
 723          */
 724         if (bus != hose->bus)
 725                 return PCI_PROBE_NORMAL;
 726         tstamp = of_get_property(hose->dn, "reset-clear-timestamp", NULL);
 727         if (!tstamp || !*tstamp)
 728                 return PCI_PROBE_NORMAL;
 729
 730         now = mftb() / tb_ticks_per_usec;
 731         target = (be64_to_cpup(tstamp) / tb_ticks_per_usec)
 732                 + PCI_RESET_DELAY_US;
 733
 734         pr_devel("pci %04d: Reset target: 0x%llx now: 0x%llx\n",
 735                  hose->global_number, target, now);
 736
 737         if (now < target)
 738                 msleep((target - now + 999) / 1000);
 739
 740         return PCI_PROBE_NORMAL;
 741 }
 742
 743 void __init pnv_pci_init(void)
 744 {
 745         struct device_node *np;
 746
 747         pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN);
 748
 749         /* OPAL absent, try POPAL first then RTAS detection of PHBs */
 750         if (!firmware_has_feature(FW_FEATURE_OPAL)) {
 751 #ifdef CONFIG_PPC_POWERNV_RTAS
 752                 init_pci_config_tokens();
 753                 find_and_init_phbs();
 754 #endif /* CONFIG_PPC_POWERNV_RTAS */
 755         }
 756         /* OPAL is here, do our normal stuff */
 757         else {
 758                 int found_ioda = 0;
 759
 760                 /* Look for IODA IO-Hubs. We don't support mixing IODA
 761                  * and p5ioc2 due to the need to change some global
 762                  * probing flags
 763                  */
 764                 for_each_compatible_node(np, NULL, "ibm,ioda-hub") {
 765                         pnv_pci_init_ioda_hub(np);
 766                         found_ioda = 1;
 767                 }
 768
 769                 /* Look for p5ioc2 IO-Hubs */
 770                 if (!found_ioda)
 771                         for_each_compatible_node(np, NULL, "ibm,p5ioc2")
 772                                 pnv_pci_init_p5ioc2_hub(np);
 773
 774                 /* Look for ioda2 built-in PHB3's */
 775                 for_each_compatible_node(np, NULL, "ibm,ioda2-phb")
 776                         pnv_pci_init_ioda2_phb(np);
 777         }
 778
 779         /* Setup the linkage between OF nodes and PHBs */
 780         pci_devs_phb_init();
 781
 782         /* Configure IOMMU DMA hooks */
 783         ppc_md.pci_dma_dev_setup = pnv_pci_dma_dev_setup;
 784         ppc_md.tce_build = pnv_tce_build_vm;
 785         ppc_md.tce_free = pnv_tce_free_vm;
 786         ppc_md.tce_build_rm = pnv_tce_build_rm;
 787         ppc_md.tce_free_rm = pnv_tce_free_rm;
 788         ppc_md.tce_get = pnv_tce_get;
 789         ppc_md.pci_probe_mode = pnv_pci_probe_mode;
 790         set_pci_dma_ops(&dma_iommu_ops);
 791
 792         /* Configure MSIs */
 793 #ifdef CONFIG_PCI_MSI
 794         ppc_md.msi_check_device = pnv_msi_check_device;
 795         ppc_md.setup_msi_irqs = pnv_setup_msi_irqs;
 796         ppc_md.teardown_msi_irqs = pnv_teardown_msi_irqs;
 797 #endif
 798 }
 799
 800 static int tce_iommu_bus_notifier(struct notifier_block *nb,
 801                 unsigned long action, void *data)
 802 {
 803         struct device *dev = data;
 804
 805         switch (action) {
 806         case BUS_NOTIFY_ADD_DEVICE:
 807                 return iommu_add_device(dev);
 808         case BUS_NOTIFY_DEL_DEVICE:
 809                 if (dev->iommu_group)
 810                         iommu_del_device(dev);
 811                 return 0;
 812         default:
 813                 return 0;
 814         }
 815 }
 816
 817 static struct notifier_block tce_iommu_bus_nb = {
 818         .notifier_call = tce_iommu_bus_notifier,
 819 };
 820
 821 static int __init tce_iommu_bus_notifier_init(void)
 822 {
 823         bus_register_notifier(&pci_bus_type, &tce_iommu_bus_nb);
 824         return 0;
 825 }
 826
 827 subsys_initcall_sync(tce_iommu_bus_notifier_init);