1 #ifndef __POWERNV_PCI_H
2 #define __POWERNV_PCI_H
12 /* Precise PHB model for error management */
14 PNV_PHB_MODEL_UNKNOWN,
20 #define PNV_PCI_DIAG_BUF_SIZE 8192
21 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
22 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
23 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
24 #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
25 #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
26 #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */
28 /* Data associated with a PE, including IOMMU tracking etc.. */
34 /* A PE can be associated with a single device or an
35 * entire bus (& children). In the former case, pdev
36 * is populated, in the later case, pbus is.
39 struct pci_dev *parent_dev;
44 /* Effective RID (device RID for a device PE and base bus
45 * RID with devfn 0 for a bus PE)
50 unsigned int pe_number;
52 /* "Weight" assigned to the PE for the sake of DMA resource
55 unsigned int dma_weight;
57 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
60 struct iommu_table *tce32_table;
61 phys_addr_t tce_inval_reg_phys;
63 /* 64-bit TCE bypass region */
64 bool tce_bypass_enabled;
65 uint64_t tce_bypass_base;
67 /* MSIs. MVE index is identical for for 32 and 64 bit MSI
68 * and -1 if not supported. (It's actually identical to the
73 /* PEs in compound case */
74 struct pnv_ioda_pe *master;
75 struct list_head slaves;
77 /* Link in list of PE#s */
78 struct list_head dma_link;
79 struct list_head list;
82 #define PNV_PHB_FLAG_EEH (1 << 0)
85 struct pci_controller *hose;
86 enum pnv_phb_type type;
87 enum pnv_phb_model model;
95 #ifdef CONFIG_DEBUG_FS
100 #ifdef CONFIG_PCI_MSI
101 unsigned int msi_base;
102 unsigned int msi32_support;
103 struct msi_bitmap msi_bmp;
105 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
106 unsigned int hwirq, unsigned int virq,
107 unsigned int is_64, struct msi_msg *msg);
108 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
109 int (*dma_set_mask)(struct pnv_phb *phb, struct pci_dev *pdev,
111 u64 (*dma_get_required_mask)(struct pnv_phb *phb,
112 struct pci_dev *pdev);
113 void (*fixup_phb)(struct pci_controller *hose);
114 u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
115 void (*shutdown)(struct pnv_phb *phb);
116 int (*init_m64)(struct pnv_phb *phb);
117 void (*reserve_m64_pe)(struct pnv_phb *phb);
118 int (*pick_m64_pe)(struct pnv_phb *phb, struct pci_bus *bus, int all);
119 int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
120 void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
121 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
125 struct iommu_table iommu_table;
129 /* Global bridge info */
130 unsigned int total_pe;
131 unsigned int reserved_pe;
133 /* 32-bit MMIO window */
134 unsigned int m32_size;
135 unsigned int m32_segsize;
136 unsigned int m32_pci_base;
138 /* 64-bit MMIO window */
139 unsigned int m64_bar_idx;
140 unsigned long m64_size;
141 unsigned long m64_segsize;
142 unsigned long m64_base;
143 unsigned long m64_bar_alloc;
146 unsigned int io_size;
147 unsigned int io_segsize;
148 unsigned int io_pci_base;
150 /* PE allocation bitmap */
151 unsigned long *pe_alloc;
152 /* PE allocation mutex */
153 struct mutex pe_alloc_mutex;
155 /* M32 & IO segment maps */
156 unsigned int *m32_segmap;
157 unsigned int *io_segmap;
158 struct pnv_ioda_pe *pe_array;
162 struct irq_chip irq_chip;
164 /* Sorted list of used PE's based
165 * on the sequence of creation
167 struct list_head pe_list;
168 struct mutex pe_list_mutex;
170 /* Reverse map of PEs, will have to extend if
171 * we are to support more than 256 PEs, indexed
174 unsigned char pe_rmap[0x10000];
176 /* 32-bit TCE tables allocation */
177 unsigned long tce32_count;
179 /* Total "weight" for the sake of DMA resources
182 unsigned int dma_weight;
183 unsigned int dma_pe_count;
185 /* Sorted list of used PE's, sorted at
186 * boot for resource allocation purposes
188 struct list_head pe_dma_list;
192 /* PHB and hub status structure */
194 unsigned char blob[PNV_PCI_DIAG_BUF_SIZE];
195 struct OpalIoP7IOCPhbErrorData p7ioc;
196 struct OpalIoPhb3ErrorData phb3;
197 struct OpalIoP7IOCErrorData hub_diag;
202 extern struct pci_ops pnv_pci_ops;
204 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
205 unsigned char *log_buff);
206 int pnv_pci_cfg_read(struct pci_dn *pdn,
207 int where, int size, u32 *val);
208 int pnv_pci_cfg_write(struct pci_dn *pdn,
209 int where, int size, u32 val);
210 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
211 void *tce_mem, u64 tce_size,
212 u64 dma_offset, unsigned page_shift);
213 extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);
214 extern void pnv_pci_init_ioda_hub(struct device_node *np);
215 extern void pnv_pci_init_ioda2_phb(struct device_node *np);
216 extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
217 __be64 *startp, __be64 *endp, bool rm);
218 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
219 extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
221 extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
222 extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
223 extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
225 #endif /* __POWERNV_PCI_H */