1 #ifndef __POWERNV_PCI_H
2 #define __POWERNV_PCI_H
12 /* Precise PHB model for error management */
14 PNV_PHB_MODEL_UNKNOWN,
20 #define PNV_PCI_DIAG_BUF_SIZE 8192
21 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
22 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
23 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
24 #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
25 #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
27 /* Data associated with a PE, including IOMMU tracking etc.. */
33 /* A PE can be associated with a single device or an
34 * entire bus (& children). In the former case, pdev
35 * is populated, in the later case, pbus is.
40 /* Effective RID (device RID for a device PE and base bus
41 * RID with devfn 0 for a bus PE)
46 unsigned int pe_number;
48 /* "Weight" assigned to the PE for the sake of DMA resource
51 unsigned int dma_weight;
53 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
56 struct iommu_table tce32_table;
57 phys_addr_t tce_inval_reg_phys;
59 /* 64-bit TCE bypass region */
60 bool tce_bypass_enabled;
61 uint64_t tce_bypass_base;
63 /* MSIs. MVE index is identical for for 32 and 64 bit MSI
64 * and -1 if not supported. (It's actually identical to the
69 /* PEs in compound case */
70 struct pnv_ioda_pe *master;
71 struct list_head slaves;
73 /* Link in list of PE#s */
74 struct list_head dma_link;
75 struct list_head list;
78 /* IOC dependent EEH operations */
81 int (*reset)(struct eeh_pe *pe, int option);
83 #endif /* CONFIG_EEH */
85 #define PNV_PHB_FLAG_EEH (1 << 0)
88 struct pci_controller *hose;
89 enum pnv_phb_type type;
90 enum pnv_phb_model model;
99 struct pnv_eeh_ops *eeh_ops;
102 #ifdef CONFIG_DEBUG_FS
104 struct dentry *dbgfs;
107 #ifdef CONFIG_PCI_MSI
108 unsigned int msi_base;
109 unsigned int msi32_support;
110 struct msi_bitmap msi_bmp;
112 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
113 unsigned int hwirq, unsigned int virq,
114 unsigned int is_64, struct msi_msg *msg);
115 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
116 int (*dma_set_mask)(struct pnv_phb *phb, struct pci_dev *pdev,
118 u64 (*dma_get_required_mask)(struct pnv_phb *phb,
119 struct pci_dev *pdev);
120 void (*fixup_phb)(struct pci_controller *hose);
121 u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
122 void (*shutdown)(struct pnv_phb *phb);
123 int (*init_m64)(struct pnv_phb *phb);
124 void (*reserve_m64_pe)(struct pnv_phb *phb);
125 int (*pick_m64_pe)(struct pnv_phb *phb, struct pci_bus *bus, int all);
126 int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
127 void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
128 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
132 struct iommu_table iommu_table;
136 /* Global bridge info */
137 unsigned int total_pe;
138 unsigned int reserved_pe;
140 /* 32-bit MMIO window */
141 unsigned int m32_size;
142 unsigned int m32_segsize;
143 unsigned int m32_pci_base;
145 /* 64-bit MMIO window */
146 unsigned int m64_bar_idx;
147 unsigned long m64_size;
148 unsigned long m64_segsize;
149 unsigned long m64_base;
150 unsigned long m64_bar_alloc;
153 unsigned int io_size;
154 unsigned int io_segsize;
155 unsigned int io_pci_base;
157 /* PE allocation bitmap */
158 unsigned long *pe_alloc;
160 /* M32 & IO segment maps */
161 unsigned int *m32_segmap;
162 unsigned int *io_segmap;
163 struct pnv_ioda_pe *pe_array;
167 struct irq_chip irq_chip;
169 /* Sorted list of used PE's based
170 * on the sequence of creation
172 struct list_head pe_list;
174 /* Reverse map of PEs, will have to extend if
175 * we are to support more than 256 PEs, indexed
178 unsigned char pe_rmap[0x10000];
180 /* 32-bit TCE tables allocation */
181 unsigned long tce32_count;
183 /* Total "weight" for the sake of DMA resources
186 unsigned int dma_weight;
187 unsigned int dma_pe_count;
189 /* Sorted list of used PE's, sorted at
190 * boot for resource allocation purposes
192 struct list_head pe_dma_list;
196 /* PHB and hub status structure */
198 unsigned char blob[PNV_PCI_DIAG_BUF_SIZE];
199 struct OpalIoP7IOCPhbErrorData p7ioc;
200 struct OpalIoPhb3ErrorData phb3;
201 struct OpalIoP7IOCErrorData hub_diag;
206 extern struct pci_ops pnv_pci_ops;
208 extern struct pnv_eeh_ops ioda_eeh_ops;
211 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
212 unsigned char *log_buff);
213 int pnv_pci_cfg_read(struct device_node *dn,
214 int where, int size, u32 *val);
215 int pnv_pci_cfg_write(struct device_node *dn,
216 int where, int size, u32 val);
217 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
218 void *tce_mem, u64 tce_size,
219 u64 dma_offset, unsigned page_shift);
220 extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);
221 extern void pnv_pci_init_ioda_hub(struct device_node *np);
222 extern void pnv_pci_init_ioda2_phb(struct device_node *np);
223 extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
224 __be64 *startp, __be64 *endp, bool rm);
225 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
226 extern int ioda_eeh_phb_reset(struct pci_controller *hose, int option);
228 #endif /* __POWERNV_PCI_H */