1 #ifndef __POWERNV_PCI_H
2 #define __POWERNV_PCI_H
4 #include <linux/iommu.h>
6 #include <asm/msi_bitmap.h>
16 /* Precise PHB model for error management */
18 PNV_PHB_MODEL_UNKNOWN,
25 #define PNV_PCI_DIAG_BUF_SIZE 8192
26 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
27 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
28 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
29 #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
30 #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
31 #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */
33 /* Data associated with a PE, including IOMMU tracking etc.. */
40 /* A PE can be associated with a single device or an
41 * entire bus (& children). In the former case, pdev
42 * is populated, in the later case, pbus is.
45 struct pci_dev *parent_dev;
50 /* Effective RID (device RID for a device PE and base bus
51 * RID with devfn 0 for a bus PE)
56 unsigned int pe_number;
58 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
59 struct iommu_table_group table_group;
61 /* 64-bit TCE bypass region */
62 bool tce_bypass_enabled;
63 uint64_t tce_bypass_base;
65 /* MSIs. MVE index is identical for for 32 and 64 bit MSI
66 * and -1 if not supported. (It's actually identical to the
71 /* PEs in compound case */
72 struct pnv_ioda_pe *master;
73 struct list_head slaves;
75 /* Link in list of PE#s */
76 struct list_head list;
79 #define PNV_PHB_FLAG_EEH (1 << 0)
80 #define PNV_PHB_FLAG_CXL (1 << 1) /* Real PHB supporting the cxl kernel API */
83 struct pci_controller *hose;
84 enum pnv_phb_type type;
85 enum pnv_phb_model model;
94 #ifdef CONFIG_DEBUG_FS
100 unsigned int msi_base;
101 unsigned int msi32_support;
102 struct msi_bitmap msi_bmp;
104 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
105 unsigned int hwirq, unsigned int virq,
106 unsigned int is_64, struct msi_msg *msg);
107 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
108 void (*fixup_phb)(struct pci_controller *hose);
109 int (*init_m64)(struct pnv_phb *phb);
110 void (*reserve_m64_pe)(struct pci_bus *bus,
111 unsigned long *pe_bitmap, bool all);
112 struct pnv_ioda_pe *(*pick_m64_pe)(struct pci_bus *bus, bool all);
113 int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
114 void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
115 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
118 /* Global bridge info */
119 unsigned int total_pe_num;
120 unsigned int reserved_pe_idx;
121 unsigned int root_pe_idx;
122 bool root_pe_populated;
124 /* 32-bit MMIO window */
125 unsigned int m32_size;
126 unsigned int m32_segsize;
127 unsigned int m32_pci_base;
129 /* 64-bit MMIO window */
130 unsigned int m64_bar_idx;
131 unsigned long m64_size;
132 unsigned long m64_segsize;
133 unsigned long m64_base;
134 unsigned long m64_bar_alloc;
137 unsigned int io_size;
138 unsigned int io_segsize;
139 unsigned int io_pci_base;
142 struct mutex pe_alloc_mutex;
143 unsigned long *pe_alloc;
144 struct pnv_ioda_pe *pe_array;
146 /* M32 & IO segment maps */
147 unsigned int *m64_segmap;
148 unsigned int *m32_segmap;
149 unsigned int *io_segmap;
151 /* DMA32 segment maps - IODA1 only */
152 unsigned int dma32_count;
153 unsigned int *dma32_segmap;
157 struct irq_chip irq_chip;
159 /* Sorted list of used PE's based
160 * on the sequence of creation
162 struct list_head pe_list;
163 struct mutex pe_list_mutex;
165 /* Reverse map of PEs, indexed by {bus, devfn} */
166 unsigned int pe_rmap[0x10000];
169 /* PHB and hub status structure */
171 unsigned char blob[PNV_PCI_DIAG_BUF_SIZE];
172 struct OpalIoP7IOCPhbErrorData p7ioc;
173 struct OpalIoPhb3ErrorData phb3;
174 struct OpalIoP7IOCErrorData hub_diag;
177 #ifdef CONFIG_CXL_BASE
178 struct cxl_afu *cxl_afu;
182 extern struct pci_ops pnv_pci_ops;
183 extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
184 unsigned long uaddr, enum dma_data_direction direction,
185 unsigned long attrs);
186 extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
187 extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
188 unsigned long *hpa, enum dma_data_direction *direction);
189 extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);
191 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
192 unsigned char *log_buff);
193 int pnv_pci_cfg_read(struct pci_dn *pdn,
194 int where, int size, u32 *val);
195 int pnv_pci_cfg_write(struct pci_dn *pdn,
196 int where, int size, u32 val);
197 extern struct iommu_table *pnv_pci_table_alloc(int nid);
199 extern long pnv_pci_link_table_and_group(int node, int num,
200 struct iommu_table *tbl,
201 struct iommu_table_group *table_group);
202 extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
203 struct iommu_table_group *table_group);
204 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
205 void *tce_mem, u64 tce_size,
206 u64 dma_offset, unsigned page_shift);
207 extern void pnv_pci_init_ioda_hub(struct device_node *np);
208 extern void pnv_pci_init_ioda2_phb(struct device_node *np);
209 extern void pnv_pci_init_npu_phb(struct device_node *np);
210 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
211 extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
213 extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
214 extern void pnv_pci_dma_bus_setup(struct pci_bus *bus);
215 extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
216 extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
217 extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev);
218 extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq);
219 extern bool pnv_pci_enable_device_hook(struct pci_dev *dev);
221 extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
222 const char *fmt, ...);
223 #define pe_err(pe, fmt, ...) \
224 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
225 #define pe_warn(pe, fmt, ...) \
226 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
227 #define pe_info(pe, fmt, ...) \
228 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
230 /* Nvlink functions */
231 extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
232 extern void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
233 extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe);
234 extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
235 struct iommu_table *tbl);
236 extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num);
237 extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe);
238 extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe);
242 extern bool pnv_cxl_enable_device_hook(struct pci_dev *dev);
243 extern void pnv_cxl_disable_device(struct pci_dev *dev);
244 extern int pnv_cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
245 extern void pnv_cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev);
248 /* phb ops (cxl switches these when enabling the kernel api on the phb) */
249 extern const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops;
251 #endif /* __POWERNV_PCI_H */