1 #ifndef __POWERNV_PCI_H
2 #define __POWERNV_PCI_H
12 /* Precise PHB model for error management */
14 PNV_PHB_MODEL_UNKNOWN,
20 #define PNV_PCI_DIAG_BUF_SIZE 8192
21 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
22 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
23 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
24 #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
25 #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
27 /* Data associated with a PE, including IOMMU tracking etc.. */
33 /* A PE can be associated with a single device or an
34 * entire bus (& children). In the former case, pdev
35 * is populated, in the later case, pbus is.
40 /* Effective RID (device RID for a device PE and base bus
41 * RID with devfn 0 for a bus PE)
46 unsigned int pe_number;
48 /* "Weight" assigned to the PE for the sake of DMA resource
51 unsigned int dma_weight;
53 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
56 struct iommu_table tce32_table;
57 phys_addr_t tce_inval_reg_phys;
59 /* 64-bit TCE bypass region */
60 bool tce_bypass_enabled;
61 uint64_t tce_bypass_base;
63 /* MSIs. MVE index is identical for for 32 and 64 bit MSI
64 * and -1 if not supported. (It's actually identical to the
69 /* PEs in compound case */
70 struct pnv_ioda_pe *master;
71 struct list_head slaves;
73 /* Link in list of PE#s */
74 struct list_head dma_link;
75 struct list_head list;
78 #define PNV_PHB_FLAG_EEH (1 << 0)
81 struct pci_controller *hose;
82 enum pnv_phb_type type;
83 enum pnv_phb_model model;
91 #ifdef CONFIG_DEBUG_FS
97 unsigned int msi_base;
98 unsigned int msi32_support;
99 struct msi_bitmap msi_bmp;
101 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
102 unsigned int hwirq, unsigned int virq,
103 unsigned int is_64, struct msi_msg *msg);
104 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
105 int (*dma_set_mask)(struct pnv_phb *phb, struct pci_dev *pdev,
107 u64 (*dma_get_required_mask)(struct pnv_phb *phb,
108 struct pci_dev *pdev);
109 void (*fixup_phb)(struct pci_controller *hose);
110 u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
111 void (*shutdown)(struct pnv_phb *phb);
112 int (*init_m64)(struct pnv_phb *phb);
113 void (*reserve_m64_pe)(struct pnv_phb *phb);
114 int (*pick_m64_pe)(struct pnv_phb *phb, struct pci_bus *bus, int all);
115 int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
116 void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
117 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
121 struct iommu_table iommu_table;
125 /* Global bridge info */
126 unsigned int total_pe;
127 unsigned int reserved_pe;
129 /* 32-bit MMIO window */
130 unsigned int m32_size;
131 unsigned int m32_segsize;
132 unsigned int m32_pci_base;
134 /* 64-bit MMIO window */
135 unsigned int m64_bar_idx;
136 unsigned long m64_size;
137 unsigned long m64_segsize;
138 unsigned long m64_base;
139 unsigned long m64_bar_alloc;
142 unsigned int io_size;
143 unsigned int io_segsize;
144 unsigned int io_pci_base;
146 /* PE allocation bitmap */
147 unsigned long *pe_alloc;
149 /* M32 & IO segment maps */
150 unsigned int *m32_segmap;
151 unsigned int *io_segmap;
152 struct pnv_ioda_pe *pe_array;
156 struct irq_chip irq_chip;
158 /* Sorted list of used PE's based
159 * on the sequence of creation
161 struct list_head pe_list;
163 /* Reverse map of PEs, will have to extend if
164 * we are to support more than 256 PEs, indexed
167 unsigned char pe_rmap[0x10000];
169 /* 32-bit TCE tables allocation */
170 unsigned long tce32_count;
172 /* Total "weight" for the sake of DMA resources
175 unsigned int dma_weight;
176 unsigned int dma_pe_count;
178 /* Sorted list of used PE's, sorted at
179 * boot for resource allocation purposes
181 struct list_head pe_dma_list;
185 /* PHB and hub status structure */
187 unsigned char blob[PNV_PCI_DIAG_BUF_SIZE];
188 struct OpalIoP7IOCPhbErrorData p7ioc;
189 struct OpalIoPhb3ErrorData phb3;
190 struct OpalIoP7IOCErrorData hub_diag;
195 extern struct pci_ops pnv_pci_ops;
197 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
198 unsigned char *log_buff);
199 int pnv_pci_cfg_read(struct device_node *dn,
200 int where, int size, u32 *val);
201 int pnv_pci_cfg_write(struct device_node *dn,
202 int where, int size, u32 val);
203 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
204 void *tce_mem, u64 tce_size,
205 u64 dma_offset, unsigned page_shift);
206 extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);
207 extern void pnv_pci_init_ioda_hub(struct device_node *np);
208 extern void pnv_pci_init_ioda2_phb(struct device_node *np);
209 extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
210 __be64 *startp, __be64 *endp, bool rm);
211 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
212 extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
214 #endif /* __POWERNV_PCI_H */