3 * Copyright IBM Corporation 2001, 2005, 2006
4 * Copyright Dave Engebretsen & Todd Inglett 2001
5 * Copyright Linas Vepstas 2005, 2006
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/list.h>
27 #include <linux/pci.h>
28 #include <linux/proc_fs.h>
29 #include <linux/rbtree.h>
30 #include <linux/seq_file.h>
31 #include <linux/spinlock.h>
34 #include <asm/atomic.h>
36 #include <asm/eeh_event.h>
38 #include <asm/machdep.h>
39 #include <asm/ppc-pci.h>
44 * EEH, or "Extended Error Handling" is a PCI bridge technology for
45 * dealing with PCI bus errors that can't be dealt with within the
46 * usual PCI framework, except by check-stopping the CPU. Systems
47 * that are designed for high-availability/reliability cannot afford
48 * to crash due to a "mere" PCI error, thus the need for EEH.
49 * An EEH-capable bridge operates by converting a detected error
50 * into a "slot freeze", taking the PCI adapter off-line, making
51 * the slot behave, from the OS'es point of view, as if the slot
52 * were "empty": all reads return 0xff's and all writes are silently
53 * ignored. EEH slot isolation events can be triggered by parity
54 * errors on the address or data busses (e.g. during posted writes),
55 * which in turn might be caused by low voltage on the bus, dust,
56 * vibration, humidity, radioactivity or plain-old failed hardware.
58 * Note, however, that one of the leading causes of EEH slot
59 * freeze events are buggy device drivers, buggy device microcode,
60 * or buggy device hardware. This is because any attempt by the
61 * device to bus-master data to a memory address that is not
62 * assigned to the device will trigger a slot freeze. (The idea
63 * is to prevent devices-gone-wild from corrupting system memory).
64 * Buggy hardware/drivers will have a miserable time co-existing
67 * Ideally, a PCI device driver, when suspecting that an isolation
68 * event has occurred (e.g. by reading 0xff's), will then ask EEH
69 * whether this is the case, and then take appropriate steps to
70 * reset the PCI slot, the PCI device, and then resume operations.
71 * However, until that day, the checking is done here, with the
72 * eeh_check_failure() routine embedded in the MMIO macros. If
73 * the slot is found to be isolated, an "EEH Event" is synthesized
74 * and sent out for processing.
77 /* If a device driver keeps reading an MMIO register in an interrupt
78 * handler after a slot isolation event, it might be broken.
79 * This sets the threshold for how many read attempts we allow
80 * before printing an error message.
82 #define EEH_MAX_FAILS 2100000
84 /* Time to wait for a PCI slot to report status, in milliseconds */
85 #define PCI_BUS_RESET_WAIT_MSEC (60*1000)
88 static int ibm_set_eeh_option;
89 static int ibm_set_slot_reset;
90 static int ibm_read_slot_reset_state;
91 static int ibm_read_slot_reset_state2;
92 static int ibm_slot_error_detail;
93 static int ibm_get_config_addr_info;
94 static int ibm_get_config_addr_info2;
95 static int ibm_configure_bridge;
97 int eeh_subsystem_enabled;
98 EXPORT_SYMBOL(eeh_subsystem_enabled);
100 /* Lock to avoid races due to multiple reports of an error */
101 static DEFINE_RAW_SPINLOCK(confirm_error_lock);
103 /* Buffer for reporting slot-error-detail rtas calls. Its here
104 * in BSS, and not dynamically alloced, so that it ends up in
105 * RMO where RTAS can access it.
107 static unsigned char slot_errbuf[RTAS_ERROR_LOG_MAX];
108 static DEFINE_SPINLOCK(slot_errbuf_lock);
109 static int eeh_error_buf_size;
111 /* Buffer for reporting pci register dumps. Its here in BSS, and
112 * not dynamically alloced, so that it ends up in RMO where RTAS
115 #define EEH_PCI_REGS_LOG_LEN 4096
116 static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN];
118 /* System monitoring statistics */
119 static unsigned long no_device;
120 static unsigned long no_dn;
121 static unsigned long no_cfg_addr;
122 static unsigned long ignored_check;
123 static unsigned long total_mmio_ffs;
124 static unsigned long false_positives;
125 static unsigned long slot_resets;
127 #define IS_BRIDGE(class_code) (((class_code)<<16) == PCI_BASE_CLASS_BRIDGE)
129 /* --------------------------------------------------------------- */
130 /* Below lies the EEH event infrastructure */
132 static void rtas_slot_error_detail(struct pci_dn *pdn, int severity,
133 char *driver_log, size_t loglen)
139 /* Log the error with the rtas logger */
140 spin_lock_irqsave(&slot_errbuf_lock, flags);
141 memset(slot_errbuf, 0, eeh_error_buf_size);
143 /* Use PE configuration address, if present */
144 config_addr = pdn->eeh_config_addr;
145 if (pdn->eeh_pe_config_addr)
146 config_addr = pdn->eeh_pe_config_addr;
148 rc = rtas_call(ibm_slot_error_detail,
149 8, 1, NULL, config_addr,
150 BUID_HI(pdn->phb->buid),
151 BUID_LO(pdn->phb->buid),
152 virt_to_phys(driver_log), loglen,
153 virt_to_phys(slot_errbuf),
158 log_error(slot_errbuf, ERR_TYPE_RTAS_LOG, 0);
159 spin_unlock_irqrestore(&slot_errbuf_lock, flags);
163 * gather_pci_data - copy assorted PCI config space registers to buff
164 * @pdn: device to report data for
165 * @buf: point to buffer in which to log
166 * @len: amount of room in buffer
168 * This routine captures assorted PCI configuration space data,
169 * and puts them into a buffer for RTAS error logging.
171 static size_t gather_pci_data(struct pci_dn *pdn, char * buf, size_t len)
173 struct pci_dev *dev = pdn->pcidev;
178 n += scnprintf(buf+n, len-n, "%s\n", pdn->node->full_name);
179 printk(KERN_WARNING "EEH: of node=%s\n", pdn->node->full_name);
181 rtas_read_config(pdn, PCI_VENDOR_ID, 4, &cfg);
182 n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg);
183 printk(KERN_WARNING "EEH: PCI device/vendor: %08x\n", cfg);
185 rtas_read_config(pdn, PCI_COMMAND, 4, &cfg);
186 n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg);
187 printk(KERN_WARNING "EEH: PCI cmd/status register: %08x\n", cfg);
190 printk(KERN_WARNING "EEH: no PCI device for this of node\n");
194 /* Gather bridge-specific registers */
195 if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) {
196 rtas_read_config(pdn, PCI_SEC_STATUS, 2, &cfg);
197 n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg);
198 printk(KERN_WARNING "EEH: Bridge secondary status: %04x\n", cfg);
200 rtas_read_config(pdn, PCI_BRIDGE_CONTROL, 2, &cfg);
201 n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg);
202 printk(KERN_WARNING "EEH: Bridge control: %04x\n", cfg);
205 /* Dump out the PCI-X command and status regs */
206 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
208 rtas_read_config(pdn, cap, 4, &cfg);
209 n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg);
210 printk(KERN_WARNING "EEH: PCI-X cmd: %08x\n", cfg);
212 rtas_read_config(pdn, cap+4, 4, &cfg);
213 n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg);
214 printk(KERN_WARNING "EEH: PCI-X status: %08x\n", cfg);
217 /* If PCI-E capable, dump PCI-E cap 10, and the AER */
218 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
220 n += scnprintf(buf+n, len-n, "pci-e cap10:\n");
222 "EEH: PCI-E capabilities and status follow:\n");
224 for (i=0; i<=8; i++) {
225 rtas_read_config(pdn, cap+4*i, 4, &cfg);
226 n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
227 printk(KERN_WARNING "EEH: PCI-E %02x: %08x\n", i, cfg);
230 cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
232 n += scnprintf(buf+n, len-n, "pci-e AER:\n");
234 "EEH: PCI-E AER capability register set follows:\n");
236 for (i=0; i<14; i++) {
237 rtas_read_config(pdn, cap+4*i, 4, &cfg);
238 n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
239 printk(KERN_WARNING "EEH: PCI-E AER %02x: %08x\n", i, cfg);
244 /* Gather status on devices under the bridge */
245 if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) {
246 struct device_node *dn;
248 for_each_child_of_node(pdn->node, dn) {
251 n += gather_pci_data(pdn, buf+n, len-n);
258 void eeh_slot_error_detail(struct pci_dn *pdn, int severity)
263 rtas_pci_enable(pdn, EEH_THAW_MMIO);
264 loglen = gather_pci_data(pdn, pci_regs_buf, EEH_PCI_REGS_LOG_LEN);
266 rtas_slot_error_detail(pdn, severity, pci_regs_buf, loglen);
270 * read_slot_reset_state - Read the reset state of a device node's slot
271 * @dn: device node to read
272 * @rets: array to return results in
274 static int read_slot_reset_state(struct pci_dn *pdn, int rets[])
279 if (ibm_read_slot_reset_state2 != RTAS_UNKNOWN_SERVICE) {
280 token = ibm_read_slot_reset_state2;
283 token = ibm_read_slot_reset_state;
284 rets[2] = 0; /* fake PE Unavailable info */
288 /* Use PE configuration address, if present */
289 config_addr = pdn->eeh_config_addr;
290 if (pdn->eeh_pe_config_addr)
291 config_addr = pdn->eeh_pe_config_addr;
293 return rtas_call(token, 3, outputs, rets, config_addr,
294 BUID_HI(pdn->phb->buid), BUID_LO(pdn->phb->buid));
298 * eeh_wait_for_slot_status - returns error status of slot
299 * @pdn pci device node
300 * @max_wait_msecs maximum number to millisecs to wait
302 * Return negative value if a permanent error, else return
303 * Partition Endpoint (PE) status value.
305 * If @max_wait_msecs is positive, then this routine will
306 * sleep until a valid status can be obtained, or until
307 * the max allowed wait time is exceeded, in which case
311 eeh_wait_for_slot_status(struct pci_dn *pdn, int max_wait_msecs)
318 rc = read_slot_reset_state(pdn, rets);
320 if (rets[1] == 0) return -1; /* EEH is not supported */
322 if (rets[0] != 5) return rets[0]; /* return actual status */
324 if (rets[2] == 0) return -1; /* permanently unavailable */
326 if (max_wait_msecs <= 0) break;
331 "EEH: Firmware returned bad wait value=%d\n", mwait);
333 } else if (mwait > 300*1000) {
335 "EEH: Firmware is taking too long, time=%d\n", mwait);
338 max_wait_msecs -= mwait;
342 printk(KERN_WARNING "EEH: Timed out waiting for slot status\n");
347 * eeh_token_to_phys - convert EEH address token to phys address
348 * @token i/o token, should be address in the form 0xA....
350 static inline unsigned long eeh_token_to_phys(unsigned long token)
355 ptep = find_linux_pte(init_mm.pgd, token);
358 pa = pte_pfn(*ptep) << PAGE_SHIFT;
360 return pa | (token & (PAGE_SIZE-1));
364 * Return the "partitionable endpoint" (pe) under which this device lies
366 struct device_node * find_device_pe(struct device_node *dn)
368 while ((dn->parent) && PCI_DN(dn->parent) &&
369 (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) {
375 /** Mark all devices that are children of this device as failed.
376 * Mark the device driver too, so that it can see the failure
377 * immediately; this is critical, since some drivers poll
378 * status registers in interrupts ... If a driver is polling,
379 * and the slot is frozen, then the driver can deadlock in
380 * an interrupt context, which is bad.
383 static void __eeh_mark_slot(struct device_node *parent, int mode_flag)
385 struct device_node *dn;
387 for_each_child_of_node(parent, dn) {
389 /* Mark the pci device driver too */
390 struct pci_dev *dev = PCI_DN(dn)->pcidev;
392 PCI_DN(dn)->eeh_mode |= mode_flag;
394 if (dev && dev->driver)
395 dev->error_state = pci_channel_io_frozen;
397 __eeh_mark_slot(dn, mode_flag);
402 void eeh_mark_slot (struct device_node *dn, int mode_flag)
405 dn = find_device_pe (dn);
407 /* Back up one, since config addrs might be shared */
408 if (!pcibios_find_pci_bus(dn) && PCI_DN(dn->parent))
411 PCI_DN(dn)->eeh_mode |= mode_flag;
413 /* Mark the pci device too */
414 dev = PCI_DN(dn)->pcidev;
416 dev->error_state = pci_channel_io_frozen;
418 __eeh_mark_slot(dn, mode_flag);
421 static void __eeh_clear_slot(struct device_node *parent, int mode_flag)
423 struct device_node *dn;
425 for_each_child_of_node(parent, dn) {
427 PCI_DN(dn)->eeh_mode &= ~mode_flag;
428 PCI_DN(dn)->eeh_check_count = 0;
429 __eeh_clear_slot(dn, mode_flag);
434 void eeh_clear_slot (struct device_node *dn, int mode_flag)
437 raw_spin_lock_irqsave(&confirm_error_lock, flags);
439 dn = find_device_pe (dn);
441 /* Back up one, since config addrs might be shared */
442 if (!pcibios_find_pci_bus(dn) && PCI_DN(dn->parent))
445 PCI_DN(dn)->eeh_mode &= ~mode_flag;
446 PCI_DN(dn)->eeh_check_count = 0;
447 __eeh_clear_slot(dn, mode_flag);
448 raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
452 * eeh_dn_check_failure - check if all 1's data is due to EEH slot freeze
454 * @dev pci device, if known
456 * Check for an EEH failure for the given device node. Call this
457 * routine if the result of a read was all 0xff's and you want to
458 * find out if this is due to an EEH slot freeze. This routine
459 * will query firmware for the EEH status.
461 * Returns 0 if there has not been an EEH error; otherwise returns
462 * a non-zero value and queues up a slot isolation event notification.
464 * It is safe to call this routine in an interrupt context.
466 int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
473 const char *location;
477 if (!eeh_subsystem_enabled)
484 dn = find_device_pe(dn);
487 /* Access to IO BARs might get this far and still not want checking. */
488 if (!(pdn->eeh_mode & EEH_MODE_SUPPORTED) ||
489 pdn->eeh_mode & EEH_MODE_NOCHECK) {
491 pr_debug("EEH: Ignored check (%x) for %s %s\n",
492 pdn->eeh_mode, eeh_pci_name(dev), dn->full_name);
496 if (!pdn->eeh_config_addr && !pdn->eeh_pe_config_addr) {
501 /* If we already have a pending isolation event for this
502 * slot, we know it's bad already, we don't need to check.
503 * Do this checking under a lock; as multiple PCI devices
504 * in one slot might report errors simultaneously, and we
505 * only want one error recovery routine running.
507 raw_spin_lock_irqsave(&confirm_error_lock, flags);
509 if (pdn->eeh_mode & EEH_MODE_ISOLATED) {
510 pdn->eeh_check_count ++;
511 if (pdn->eeh_check_count % EEH_MAX_FAILS == 0) {
512 location = of_get_property(dn, "ibm,loc-code", NULL);
513 printk (KERN_ERR "EEH: %d reads ignored for recovering device at "
514 "location=%s driver=%s pci addr=%s\n",
515 pdn->eeh_check_count, location,
516 dev->driver->name, eeh_pci_name(dev));
517 printk (KERN_ERR "EEH: Might be infinite loop in %s driver\n",
525 * Now test for an EEH failure. This is VERY expensive.
526 * Note that the eeh_config_addr may be a parent device
527 * in the case of a device behind a bridge, or it may be
528 * function zero of a multi-function device.
529 * In any case they must share a common PHB.
531 ret = read_slot_reset_state(pdn, rets);
533 /* If the call to firmware failed, punt */
535 printk(KERN_WARNING "EEH: read_slot_reset_state() failed; rc=%d dn=%s\n",
538 pdn->eeh_false_positives ++;
543 /* Note that config-io to empty slots may fail;
544 * they are empty when they don't have children. */
545 if ((rets[0] == 5) && (rets[2] == 0) && (dn->child == NULL)) {
547 pdn->eeh_false_positives ++;
552 /* If EEH is not supported on this device, punt. */
554 printk(KERN_WARNING "EEH: event on unsupported device, rc=%d dn=%s\n",
557 pdn->eeh_false_positives ++;
562 /* If not the kind of error we know about, punt. */
563 if (rets[0] != 1 && rets[0] != 2 && rets[0] != 4 && rets[0] != 5) {
565 pdn->eeh_false_positives ++;
572 /* Avoid repeated reports of this failure, including problems
573 * with other functions on this device, and functions under
575 eeh_mark_slot (dn, EEH_MODE_ISOLATED);
576 raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
578 eeh_send_failure_event (dn, dev);
580 /* Most EEH events are due to device driver bugs. Having
581 * a stack trace will help the device-driver authors figure
582 * out what happened. So print that out. */
587 raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
591 EXPORT_SYMBOL_GPL(eeh_dn_check_failure);
594 * eeh_check_failure - check if all 1's data is due to EEH slot freeze
595 * @token i/o token, should be address in the form 0xA....
596 * @val value, should be all 1's (XXX why do we need this arg??)
598 * Check for an EEH failure at the given token address. Call this
599 * routine if the result of a read was all 0xff's and you want to
600 * find out if this is due to an EEH slot freeze event. This routine
601 * will query firmware for the EEH status.
603 * Note this routine is safe to call in an interrupt context.
605 unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val)
609 struct device_node *dn;
611 /* Finding the phys addr + pci device; this is pretty quick. */
612 addr = eeh_token_to_phys((unsigned long __force) token);
613 dev = pci_get_device_by_addr(addr);
619 dn = pci_device_to_OF_node(dev);
620 eeh_dn_check_failure (dn, dev);
626 EXPORT_SYMBOL(eeh_check_failure);
628 /* ------------------------------------------------------------- */
629 /* The code below deals with error recovery */
632 * rtas_pci_enable - enable MMIO or DMA transfers for this slot
633 * @pdn pci device node
637 rtas_pci_enable(struct pci_dn *pdn, int function)
642 /* Use PE configuration address, if present */
643 config_addr = pdn->eeh_config_addr;
644 if (pdn->eeh_pe_config_addr)
645 config_addr = pdn->eeh_pe_config_addr;
647 rc = rtas_call(ibm_set_eeh_option, 4, 1, NULL,
649 BUID_HI(pdn->phb->buid),
650 BUID_LO(pdn->phb->buid),
654 printk(KERN_WARNING "EEH: Unexpected state change %d, err=%d dn=%s\n",
655 function, rc, pdn->node->full_name);
657 rc = eeh_wait_for_slot_status (pdn, PCI_BUS_RESET_WAIT_MSEC);
658 if ((rc == 4) && (function == EEH_THAW_MMIO))
665 * rtas_pci_slot_reset - raises/lowers the pci #RST line
666 * @pdn pci device node
667 * @state: 1/0 to raise/lower the #RST
669 * Clear the EEH-frozen condition on a slot. This routine
670 * asserts the PCI #RST line if the 'state' argument is '1',
671 * and drops the #RST line if 'state is '0'. This routine is
672 * safe to call in an interrupt context.
677 rtas_pci_slot_reset(struct pci_dn *pdn, int state)
685 printk (KERN_WARNING "EEH: in slot reset, device node %s has no phb\n",
686 pdn->node->full_name);
690 /* Use PE configuration address, if present */
691 config_addr = pdn->eeh_config_addr;
692 if (pdn->eeh_pe_config_addr)
693 config_addr = pdn->eeh_pe_config_addr;
695 rc = rtas_call(ibm_set_slot_reset,4,1, NULL,
697 BUID_HI(pdn->phb->buid),
698 BUID_LO(pdn->phb->buid),
701 printk (KERN_WARNING "EEH: Unable to reset the failed slot,"
702 " (%d) #RST=%d dn=%s\n",
703 rc, state, pdn->node->full_name);
707 * pcibios_set_pcie_slot_reset - Set PCI-E reset state
708 * @dev: pci device struct
709 * @state: reset state to enter
714 int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
716 struct device_node *dn = pci_device_to_OF_node(dev);
717 struct pci_dn *pdn = PCI_DN(dn);
720 case pcie_deassert_reset:
721 rtas_pci_slot_reset(pdn, 0);
724 rtas_pci_slot_reset(pdn, 1);
726 case pcie_warm_reset:
727 rtas_pci_slot_reset(pdn, 3);
737 * rtas_set_slot_reset -- assert the pci #RST line for 1/4 second
738 * @pdn: pci device node to be reset.
740 * Return 0 if success, else a non-zero value.
743 static void __rtas_set_slot_reset(struct pci_dn *pdn)
745 struct pci_dev *dev = pdn->pcidev;
747 /* Determine type of EEH reset required by device,
748 * default hot reset or fundamental reset
750 if (dev && dev->needs_freset)
751 rtas_pci_slot_reset(pdn, 3);
753 rtas_pci_slot_reset(pdn, 1);
755 /* The PCI bus requires that the reset be held high for at least
756 * a 100 milliseconds. We wait a bit longer 'just in case'. */
758 #define PCI_BUS_RST_HOLD_TIME_MSEC 250
759 msleep (PCI_BUS_RST_HOLD_TIME_MSEC);
761 /* We might get hit with another EEH freeze as soon as the
762 * pci slot reset line is dropped. Make sure we don't miss
763 * these, and clear the flag now. */
764 eeh_clear_slot (pdn->node, EEH_MODE_ISOLATED);
766 rtas_pci_slot_reset (pdn, 0);
768 /* After a PCI slot has been reset, the PCI Express spec requires
769 * a 1.5 second idle time for the bus to stabilize, before starting
771 #define PCI_BUS_SETTLE_TIME_MSEC 1800
772 msleep (PCI_BUS_SETTLE_TIME_MSEC);
775 int rtas_set_slot_reset(struct pci_dn *pdn)
779 /* Take three shots at resetting the bus */
780 for (i=0; i<3; i++) {
781 __rtas_set_slot_reset(pdn);
783 rc = eeh_wait_for_slot_status(pdn, PCI_BUS_RESET_WAIT_MSEC);
788 printk(KERN_ERR "EEH: unrecoverable slot failure %s\n",
789 pdn->node->full_name);
792 printk(KERN_ERR "EEH: bus reset %d failed on slot %s, rc=%d\n",
793 i+1, pdn->node->full_name, rc);
799 /* ------------------------------------------------------- */
800 /** Save and restore of PCI BARs
802 * Although firmware will set up BARs during boot, it doesn't
803 * set up device BAR's after a device reset, although it will,
804 * if requested, set up bridge configuration. Thus, we need to
805 * configure the PCI devices ourselves.
809 * __restore_bars - Restore the Base Address Registers
810 * @pdn: pci device node
812 * Loads the PCI configuration space base address registers,
813 * the expansion ROM base address, the latency timer, and etc.
814 * from the saved values in the device node.
816 static inline void __restore_bars (struct pci_dn *pdn)
821 if (NULL==pdn->phb) return;
822 for (i=4; i<10; i++) {
823 rtas_write_config(pdn, i*4, 4, pdn->config_space[i]);
826 /* 12 == Expansion ROM Address */
827 rtas_write_config(pdn, 12*4, 4, pdn->config_space[12]);
829 #define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
830 #define SAVED_BYTE(OFF) (((u8 *)(pdn->config_space))[BYTE_SWAP(OFF)])
832 rtas_write_config (pdn, PCI_CACHE_LINE_SIZE, 1,
833 SAVED_BYTE(PCI_CACHE_LINE_SIZE));
835 rtas_write_config (pdn, PCI_LATENCY_TIMER, 1,
836 SAVED_BYTE(PCI_LATENCY_TIMER));
838 /* max latency, min grant, interrupt pin and line */
839 rtas_write_config(pdn, 15*4, 4, pdn->config_space[15]);
841 /* Restore PERR & SERR bits, some devices require it,
842 don't touch the other command bits */
843 rtas_read_config(pdn, PCI_COMMAND, 4, &cmd);
844 if (pdn->config_space[1] & PCI_COMMAND_PARITY)
845 cmd |= PCI_COMMAND_PARITY;
847 cmd &= ~PCI_COMMAND_PARITY;
848 if (pdn->config_space[1] & PCI_COMMAND_SERR)
849 cmd |= PCI_COMMAND_SERR;
851 cmd &= ~PCI_COMMAND_SERR;
852 rtas_write_config(pdn, PCI_COMMAND, 4, cmd);
856 * eeh_restore_bars - restore the PCI config space info
858 * This routine performs a recursive walk to the children
859 * of this device as well.
861 void eeh_restore_bars(struct pci_dn *pdn)
863 struct device_node *dn;
867 if ((pdn->eeh_mode & EEH_MODE_SUPPORTED) && !IS_BRIDGE(pdn->class_code))
868 __restore_bars (pdn);
870 for_each_child_of_node(pdn->node, dn)
871 eeh_restore_bars (PCI_DN(dn));
875 * eeh_save_bars - save device bars
877 * Save the values of the device bars. Unlike the restore
878 * routine, this routine is *not* recursive. This is because
879 * PCI devices are added individually; but, for the restore,
880 * an entire slot is reset at a time.
882 static void eeh_save_bars(struct pci_dn *pdn)
889 for (i = 0; i < 16; i++)
890 rtas_read_config(pdn, i * 4, 4, &pdn->config_space[i]);
894 rtas_configure_bridge(struct pci_dn *pdn)
899 /* Use PE configuration address, if present */
900 config_addr = pdn->eeh_config_addr;
901 if (pdn->eeh_pe_config_addr)
902 config_addr = pdn->eeh_pe_config_addr;
904 rc = rtas_call(ibm_configure_bridge,3,1, NULL,
906 BUID_HI(pdn->phb->buid),
907 BUID_LO(pdn->phb->buid));
909 printk (KERN_WARNING "EEH: Unable to configure device bridge (%d) for %s\n",
910 rc, pdn->node->full_name);
914 /* ------------------------------------------------------------- */
915 /* The code below deals with enabling EEH for devices during the
916 * early boot sequence. EEH must be enabled before any PCI probing
922 struct eeh_early_enable_info {
923 unsigned int buid_hi;
924 unsigned int buid_lo;
927 static int get_pe_addr (int config_addr,
928 struct eeh_early_enable_info *info)
930 unsigned int rets[3];
933 /* Use latest config-addr token on power6 */
934 if (ibm_get_config_addr_info2 != RTAS_UNKNOWN_SERVICE) {
935 /* Make sure we have a PE in hand */
936 ret = rtas_call (ibm_get_config_addr_info2, 4, 2, rets,
937 config_addr, info->buid_hi, info->buid_lo, 1);
938 if (ret || (rets[0]==0))
941 ret = rtas_call (ibm_get_config_addr_info2, 4, 2, rets,
942 config_addr, info->buid_hi, info->buid_lo, 0);
948 /* Use older config-addr token on power5 */
949 if (ibm_get_config_addr_info != RTAS_UNKNOWN_SERVICE) {
950 ret = rtas_call (ibm_get_config_addr_info, 4, 2, rets,
951 config_addr, info->buid_hi, info->buid_lo, 0);
959 /* Enable eeh for the given device node. */
960 static void *early_enable_eeh(struct device_node *dn, void *data)
962 unsigned int rets[3];
963 struct eeh_early_enable_info *info = data;
965 const u32 *class_code = of_get_property(dn, "class-code", NULL);
966 const u32 *vendor_id = of_get_property(dn, "vendor-id", NULL);
967 const u32 *device_id = of_get_property(dn, "device-id", NULL);
970 struct pci_dn *pdn = PCI_DN(dn);
974 pdn->eeh_check_count = 0;
975 pdn->eeh_freeze_count = 0;
976 pdn->eeh_false_positives = 0;
978 if (!of_device_is_available(dn))
981 /* Ignore bad nodes. */
982 if (!class_code || !vendor_id || !device_id)
985 /* There is nothing to check on PCI to ISA bridges */
986 if (dn->type && !strcmp(dn->type, "isa")) {
987 pdn->eeh_mode |= EEH_MODE_NOCHECK;
990 pdn->class_code = *class_code;
992 /* Ok... see if this device supports EEH. Some do, some don't,
993 * and the only way to find out is to check each and every one. */
994 regs = of_get_property(dn, "reg", NULL);
996 /* First register entry is addr (00BBSS00) */
997 /* Try to enable eeh */
998 ret = rtas_call(ibm_set_eeh_option, 4, 1, NULL,
999 regs[0], info->buid_hi, info->buid_lo,
1004 pdn->eeh_config_addr = regs[0];
1006 /* If the newer, better, ibm,get-config-addr-info is supported,
1007 * then use that instead. */
1008 pdn->eeh_pe_config_addr = get_pe_addr(pdn->eeh_config_addr, info);
1010 /* Some older systems (Power4) allow the
1011 * ibm,set-eeh-option call to succeed even on nodes
1012 * where EEH is not supported. Verify support
1014 ret = read_slot_reset_state(pdn, rets);
1015 if ((ret == 0) && (rets[1] == 1))
1020 eeh_subsystem_enabled = 1;
1021 pdn->eeh_mode |= EEH_MODE_SUPPORTED;
1023 pr_debug("EEH: %s: eeh enabled, config=%x pe_config=%x\n",
1024 dn->full_name, pdn->eeh_config_addr,
1025 pdn->eeh_pe_config_addr);
1028 /* This device doesn't support EEH, but it may have an
1029 * EEH parent, in which case we mark it as supported. */
1030 if (dn->parent && PCI_DN(dn->parent)
1031 && (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) {
1032 /* Parent supports EEH. */
1033 pdn->eeh_mode |= EEH_MODE_SUPPORTED;
1034 pdn->eeh_config_addr = PCI_DN(dn->parent)->eeh_config_addr;
1039 printk(KERN_WARNING "EEH: %s: unable to get reg property.\n",
1048 * Initialize EEH by trying to enable it for all of the adapters in the system.
1049 * As a side effect we can determine here if eeh is supported at all.
1050 * Note that we leave EEH on so failed config cycles won't cause a machine
1051 * check. If a user turns off EEH for a particular adapter they are really
1052 * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't
1053 * grant access to a slot if EEH isn't enabled, and so we always enable
1054 * EEH for all slots/all devices.
1056 * The eeh-force-off option disables EEH checking globally, for all slots.
1057 * Even if force-off is set, the EEH hardware is still enabled, so that
1058 * newer systems can boot.
1060 void __init eeh_init(void)
1062 struct device_node *phb, *np;
1063 struct eeh_early_enable_info info;
1065 raw_spin_lock_init(&confirm_error_lock);
1066 spin_lock_init(&slot_errbuf_lock);
1068 np = of_find_node_by_path("/rtas");
1072 ibm_set_eeh_option = rtas_token("ibm,set-eeh-option");
1073 ibm_set_slot_reset = rtas_token("ibm,set-slot-reset");
1074 ibm_read_slot_reset_state2 = rtas_token("ibm,read-slot-reset-state2");
1075 ibm_read_slot_reset_state = rtas_token("ibm,read-slot-reset-state");
1076 ibm_slot_error_detail = rtas_token("ibm,slot-error-detail");
1077 ibm_get_config_addr_info = rtas_token("ibm,get-config-addr-info");
1078 ibm_get_config_addr_info2 = rtas_token("ibm,get-config-addr-info2");
1079 ibm_configure_bridge = rtas_token ("ibm,configure-bridge");
1081 if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE)
1084 eeh_error_buf_size = rtas_token("rtas-error-log-max");
1085 if (eeh_error_buf_size == RTAS_UNKNOWN_SERVICE) {
1086 eeh_error_buf_size = 1024;
1088 if (eeh_error_buf_size > RTAS_ERROR_LOG_MAX) {
1089 printk(KERN_WARNING "EEH: rtas-error-log-max is bigger than allocated "
1090 "buffer ! (%d vs %d)", eeh_error_buf_size, RTAS_ERROR_LOG_MAX);
1091 eeh_error_buf_size = RTAS_ERROR_LOG_MAX;
1094 /* Enable EEH for all adapters. Note that eeh requires buid's */
1095 for (phb = of_find_node_by_name(NULL, "pci"); phb;
1096 phb = of_find_node_by_name(phb, "pci")) {
1099 buid = get_phb_buid(phb);
1100 if (buid == 0 || PCI_DN(phb) == NULL)
1103 info.buid_lo = BUID_LO(buid);
1104 info.buid_hi = BUID_HI(buid);
1105 traverse_pci_devices(phb, early_enable_eeh, &info);
1108 if (eeh_subsystem_enabled)
1109 printk(KERN_INFO "EEH: PCI Enhanced I/O Error Handling Enabled\n");
1111 printk(KERN_WARNING "EEH: No capable adapters found\n");
1115 * eeh_add_device_early - enable EEH for the indicated device_node
1116 * @dn: device node for which to set up EEH
1118 * This routine must be used to perform EEH initialization for PCI
1119 * devices that were added after system boot (e.g. hotplug, dlpar).
1120 * This routine must be called before any i/o is performed to the
1121 * adapter (inluding any config-space i/o).
1122 * Whether this actually enables EEH or not for this device depends
1123 * on the CEC architecture, type of the device, on earlier boot
1124 * command-line arguments & etc.
1126 static void eeh_add_device_early(struct device_node *dn)
1128 struct pci_controller *phb;
1129 struct eeh_early_enable_info info;
1131 if (!dn || !PCI_DN(dn))
1133 phb = PCI_DN(dn)->phb;
1135 /* USB Bus children of PCI devices will not have BUID's */
1136 if (NULL == phb || 0 == phb->buid)
1139 info.buid_hi = BUID_HI(phb->buid);
1140 info.buid_lo = BUID_LO(phb->buid);
1141 early_enable_eeh(dn, &info);
1144 void eeh_add_device_tree_early(struct device_node *dn)
1146 struct device_node *sib;
1148 for_each_child_of_node(dn, sib)
1149 eeh_add_device_tree_early(sib);
1150 eeh_add_device_early(dn);
1152 EXPORT_SYMBOL_GPL(eeh_add_device_tree_early);
1155 * eeh_add_device_late - perform EEH initialization for the indicated pci device
1156 * @dev: pci device for which to set up EEH
1158 * This routine must be used to complete EEH initialization for PCI
1159 * devices that were added after system boot (e.g. hotplug, dlpar).
1161 static void eeh_add_device_late(struct pci_dev *dev)
1163 struct device_node *dn;
1166 if (!dev || !eeh_subsystem_enabled)
1169 pr_debug("EEH: Adding device %s\n", pci_name(dev));
1171 dn = pci_device_to_OF_node(dev);
1173 if (pdn->pcidev == dev) {
1174 pr_debug("EEH: Already referenced !\n");
1177 WARN_ON(pdn->pcidev);
1182 pci_addr_cache_insert_device(dev);
1183 eeh_sysfs_add_device(dev);
1186 void eeh_add_device_tree_late(struct pci_bus *bus)
1188 struct pci_dev *dev;
1190 list_for_each_entry(dev, &bus->devices, bus_list) {
1191 eeh_add_device_late(dev);
1192 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1193 struct pci_bus *subbus = dev->subordinate;
1195 eeh_add_device_tree_late(subbus);
1199 EXPORT_SYMBOL_GPL(eeh_add_device_tree_late);
1202 * eeh_remove_device - undo EEH setup for the indicated pci device
1203 * @dev: pci device to be removed
1205 * This routine should be called when a device is removed from
1206 * a running system (e.g. by hotplug or dlpar). It unregisters
1207 * the PCI device from the EEH subsystem. I/O errors affecting
1208 * this device will no longer be detected after this call; thus,
1209 * i/o errors affecting this slot may leave this device unusable.
1211 static void eeh_remove_device(struct pci_dev *dev)
1213 struct device_node *dn;
1214 if (!dev || !eeh_subsystem_enabled)
1217 /* Unregister the device with the EEH/PCI address search system */
1218 pr_debug("EEH: Removing device %s\n", pci_name(dev));
1220 dn = pci_device_to_OF_node(dev);
1221 if (PCI_DN(dn)->pcidev == NULL) {
1222 pr_debug("EEH: Not referenced !\n");
1225 PCI_DN(dn)->pcidev = NULL;
1228 pci_addr_cache_remove_device(dev);
1229 eeh_sysfs_remove_device(dev);
1232 void eeh_remove_bus_device(struct pci_dev *dev)
1234 struct pci_bus *bus = dev->subordinate;
1235 struct pci_dev *child, *tmp;
1237 eeh_remove_device(dev);
1239 if (bus && dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1240 list_for_each_entry_safe(child, tmp, &bus->devices, bus_list)
1241 eeh_remove_bus_device(child);
1244 EXPORT_SYMBOL_GPL(eeh_remove_bus_device);
1246 static int proc_eeh_show(struct seq_file *m, void *v)
1248 if (0 == eeh_subsystem_enabled) {
1249 seq_printf(m, "EEH Subsystem is globally disabled\n");
1250 seq_printf(m, "eeh_total_mmio_ffs=%ld\n", total_mmio_ffs);
1252 seq_printf(m, "EEH Subsystem is enabled\n");
1255 "no device node=%ld\n"
1256 "no config address=%ld\n"
1257 "check not wanted=%ld\n"
1258 "eeh_total_mmio_ffs=%ld\n"
1259 "eeh_false_positives=%ld\n"
1260 "eeh_slot_resets=%ld\n",
1261 no_device, no_dn, no_cfg_addr,
1262 ignored_check, total_mmio_ffs,
1270 static int proc_eeh_open(struct inode *inode, struct file *file)
1272 return single_open(file, proc_eeh_show, NULL);
1275 static const struct file_operations proc_eeh_operations = {
1276 .open = proc_eeh_open,
1278 .llseek = seq_lseek,
1279 .release = single_release,
1282 static int __init eeh_init_proc(void)
1284 if (machine_is(pseries))
1285 proc_create("ppc64/eeh", 0, NULL, &proc_eeh_operations);
1288 __initcall(eeh_init_proc);