arch/powerpc/platforms/pseries/iommu.c

   1 /*
   2  * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
   3  *
   4  * Rewrite, cleanup:
   5  *
   6  * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
   7  * Copyright (C) 2006 Olof Johansson <olof@lixom.net>
   8  *
   9  * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
  10  *
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  25  */
  26
  27 #include <linux/init.h>
  28 #include <linux/types.h>
  29 #include <linux/slab.h>
  30 #include <linux/mm.h>
  31 #include <linux/memblock.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/string.h>
  34 #include <linux/pci.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/crash_dump.h>
  37 #include <linux/memory.h>
  38 #include <linux/of.h>
  39 #include <linux/iommu.h>
  40 #include <linux/rculist.h>
  41 #include <asm/io.h>
  42 #include <asm/prom.h>
  43 #include <asm/rtas.h>
  44 #include <asm/iommu.h>
  45 #include <asm/pci-bridge.h>
  46 #include <asm/machdep.h>
  47 #include <asm/firmware.h>
  48 #include <asm/tce.h>
  49 #include <asm/ppc-pci.h>
  50 #include <asm/udbg.h>
  51 #include <asm/mmzone.h>
  52 #include <asm/plpar_wrappers.h>
  53
  54 #include "pseries.h"
  55
  56 static struct iommu_table_group *iommu_pseries_alloc_group(int node)
  57 {
  58         struct iommu_table_group *table_group = NULL;
  59         struct iommu_table *tbl = NULL;
  60         struct iommu_table_group_link *tgl = NULL;
  61
  62         table_group = kzalloc_node(sizeof(struct iommu_table_group), GFP_KERNEL,
  63                            node);
  64         if (!table_group)
  65                 goto fail_exit;
  66
  67         tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, node);
  68         if (!tbl)
  69                 goto fail_exit;
  70
  71         tgl = kzalloc_node(sizeof(struct iommu_table_group_link), GFP_KERNEL,
  72                         node);
  73         if (!tgl)
  74                 goto fail_exit;
  75
  76         INIT_LIST_HEAD_RCU(&tbl->it_group_list);
  77         kref_init(&tbl->it_kref);
  78         tgl->table_group = table_group;
  79         list_add_rcu(&tgl->next, &tbl->it_group_list);
  80
  81         table_group->tables[0] = tbl;
  82
  83         return table_group;
  84
  85 fail_exit:
  86         kfree(tgl);
  87         kfree(table_group);
  88         kfree(tbl);
  89
  90         return NULL;
  91 }
  92
  93 static void iommu_pseries_free_group(struct iommu_table_group *table_group,
  94                 const char *node_name)
  95 {
  96         struct iommu_table *tbl;
  97 #ifdef CONFIG_IOMMU_API
  98         struct iommu_table_group_link *tgl;
  99 #endif
 100
 101         if (!table_group)
 102                 return;
 103
 104         tbl = table_group->tables[0];
 105 #ifdef CONFIG_IOMMU_API
 106         tgl = list_first_entry_or_null(&tbl->it_group_list,
 107                         struct iommu_table_group_link, next);
 108
 109         WARN_ON_ONCE(!tgl);
 110         if (tgl) {
 111                 list_del_rcu(&tgl->next);
 112                 kfree(tgl);
 113         }
 114         if (table_group->group) {
 115                 iommu_group_put(table_group->group);
 116                 BUG_ON(table_group->group);
 117         }
 118 #endif
 119         iommu_tce_table_put(tbl);
 120
 121         kfree(table_group);
 122 }
 123
 124 static int tce_build_pSeries(struct iommu_table *tbl, long index,
 125                               long npages, unsigned long uaddr,
 126                               enum dma_data_direction direction,
 127                               unsigned long attrs)
 128 {
 129         u64 proto_tce;
 130         __be64 *tcep, *tces;
 131         u64 rpn;
 132
 133         proto_tce = TCE_PCI_READ; // Read allowed
 134
 135         if (direction != DMA_TO_DEVICE)
 136                 proto_tce |= TCE_PCI_WRITE;
 137
 138         tces = tcep = ((__be64 *)tbl->it_base) + index;
 139
 140         while (npages--) {
 141                 /* can't move this out since we might cross MEMBLOCK boundary */
 142                 rpn = __pa(uaddr) >> TCE_SHIFT;
 143                 *tcep = cpu_to_be64(proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT);
 144
 145                 uaddr += TCE_PAGE_SIZE;
 146                 tcep++;
 147         }
 148         return 0;
 149 }
 150
 151
 152 static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
 153 {
 154         __be64 *tcep, *tces;
 155
 156         tces = tcep = ((__be64 *)tbl->it_base) + index;
 157
 158         while (npages--)
 159                 *(tcep++) = 0;
 160 }
 161
 162 static unsigned long tce_get_pseries(struct iommu_table *tbl, long index)
 163 {
 164         __be64 *tcep;
 165
 166         tcep = ((__be64 *)tbl->it_base) + index;
 167
 168         return be64_to_cpu(*tcep);
 169 }
 170
 171 static void tce_free_pSeriesLP(struct iommu_table*, long, long);
 172 static void tce_freemulti_pSeriesLP(struct iommu_table*, long, long);
 173
 174 static int tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
 175                                 long npages, unsigned long uaddr,
 176                                 enum dma_data_direction direction,
 177                                 unsigned long attrs)
 178 {
 179         u64 rc = 0;
 180         u64 proto_tce, tce;
 181         u64 rpn;
 182         int ret = 0;
 183         long tcenum_start = tcenum, npages_start = npages;
 184
 185         rpn = __pa(uaddr) >> TCE_SHIFT;
 186         proto_tce = TCE_PCI_READ;
 187         if (direction != DMA_TO_DEVICE)
 188                 proto_tce |= TCE_PCI_WRITE;
 189
 190         while (npages--) {
 191                 tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
 192                 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce);
 193
 194                 if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
 195                         ret = (int)rc;
 196                         tce_free_pSeriesLP(tbl, tcenum_start,
 197                                            (npages_start - (npages + 1)));
 198                         break;
 199                 }
 200
 201                 if (rc && printk_ratelimit()) {
 202                         printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
 203                         printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 204                         printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
 205                         printk("\ttce val = 0x%llx\n", tce );
 206                         dump_stack();
 207                 }
 208
 209                 tcenum++;
 210                 rpn++;
 211         }
 212         return ret;
 213 }
 214
 215 static DEFINE_PER_CPU(__be64 *, tce_page);
 216
 217 static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
 218                                      long npages, unsigned long uaddr,
 219                                      enum dma_data_direction direction,
 220                                      unsigned long attrs)
 221 {
 222         u64 rc = 0;
 223         u64 proto_tce;
 224         __be64 *tcep;
 225         u64 rpn;
 226         long l, limit;
 227         long tcenum_start = tcenum, npages_start = npages;
 228         int ret = 0;
 229         unsigned long flags;
 230
 231         if ((npages == 1) || !firmware_has_feature(FW_FEATURE_MULTITCE)) {
 232                 return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
 233                                            direction, attrs);
 234         }
 235
 236         local_irq_save(flags);  /* to protect tcep and the page behind it */
 237
 238         tcep = __this_cpu_read(tce_page);
 239
 240         /* This is safe to do since interrupts are off when we're called
 241          * from iommu_alloc{,_sg}()
 242          */
 243         if (!tcep) {
 244                 tcep = (__be64 *)__get_free_page(GFP_ATOMIC);
 245                 /* If allocation fails, fall back to the loop implementation */
 246                 if (!tcep) {
 247                         local_irq_restore(flags);
 248                         return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
 249                                             direction, attrs);
 250                 }
 251                 __this_cpu_write(tce_page, tcep);
 252         }
 253
 254         rpn = __pa(uaddr) >> TCE_SHIFT;
 255         proto_tce = TCE_PCI_READ;
 256         if (direction != DMA_TO_DEVICE)
 257                 proto_tce |= TCE_PCI_WRITE;
 258
 259         /* We can map max one pageful of TCEs at a time */
 260         do {
 261                 /*
 262                  * Set up the page with TCE data, looping through and setting
 263                  * the values.
 264                  */
 265                 limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE);
 266
 267                 for (l = 0; l < limit; l++) {
 268                         tcep[l] = cpu_to_be64(proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT);
 269                         rpn++;
 270                 }
 271
 272                 rc = plpar_tce_put_indirect((u64)tbl->it_index,
 273                                             (u64)tcenum << 12,
 274                                             (u64)__pa(tcep),
 275                                             limit);
 276
 277                 npages -= limit;
 278                 tcenum += limit;
 279         } while (npages > 0 && !rc);
 280
 281         local_irq_restore(flags);
 282
 283         if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
 284                 ret = (int)rc;
 285                 tce_freemulti_pSeriesLP(tbl, tcenum_start,
 286                                         (npages_start - (npages + limit)));
 287                 return ret;
 288         }
 289
 290         if (rc && printk_ratelimit()) {
 291                 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
 292                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 293                 printk("\tnpages  = 0x%llx\n", (u64)npages);
 294                 printk("\ttce[0] val = 0x%llx\n", tcep[0]);
 295                 dump_stack();
 296         }
 297         return ret;
 298 }
 299
 300 static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
 301 {
 302         u64 rc;
 303
 304         while (npages--) {
 305                 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0);
 306
 307                 if (rc && printk_ratelimit()) {
 308                         printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
 309                         printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 310                         printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
 311                         dump_stack();
 312                 }
 313
 314                 tcenum++;
 315         }
 316 }
 317
 318
 319 static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
 320 {
 321         u64 rc;
 322
 323         if (!firmware_has_feature(FW_FEATURE_MULTITCE))
 324                 return tce_free_pSeriesLP(tbl, tcenum, npages);
 325
 326         rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages);
 327
 328         if (rc && printk_ratelimit()) {
 329                 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n");
 330                 printk("\trc      = %lld\n", rc);
 331                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 332                 printk("\tnpages  = 0x%llx\n", (u64)npages);
 333                 dump_stack();
 334         }
 335 }
 336
 337 static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum)
 338 {
 339         u64 rc;
 340         unsigned long tce_ret;
 341
 342         rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret);
 343
 344         if (rc && printk_ratelimit()) {
 345                 printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%lld\n", rc);
 346                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 347                 printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
 348                 dump_stack();
 349         }
 350
 351         return tce_ret;
 352 }
 353
 354 /* this is compatible with cells for the device tree property */
 355 struct dynamic_dma_window_prop {
 356         __be32  liobn;          /* tce table number */
 357         __be64  dma_base;       /* address hi,lo */
 358         __be32  tce_shift;      /* ilog2(tce_page_size) */
 359         __be32  window_shift;   /* ilog2(tce_window_size) */
 360 };
 361
 362 struct direct_window {
 363         struct device_node *device;
 364         const struct dynamic_dma_window_prop *prop;
 365         struct list_head list;
 366 };
 367
 368 /* Dynamic DMA Window support */
 369 struct ddw_query_response {
 370         u32 windows_available;
 371         u32 largest_available_block;
 372         u32 page_size;
 373         u32 migration_capable;
 374 };
 375
 376 struct ddw_create_response {
 377         u32 liobn;
 378         u32 addr_hi;
 379         u32 addr_lo;
 380 };
 381
 382 static LIST_HEAD(direct_window_list);
 383 /* prevents races between memory on/offline and window creation */
 384 static DEFINE_SPINLOCK(direct_window_list_lock);
 385 /* protects initializing window twice for same device */
 386 static DEFINE_MUTEX(direct_window_init_mutex);
 387 #define DIRECT64_PROPNAME "linux,direct64-ddr-window-info"
 388
 389 static int tce_clearrange_multi_pSeriesLP(unsigned long start_pfn,
 390                                         unsigned long num_pfn, const void *arg)
 391 {
 392         const struct dynamic_dma_window_prop *maprange = arg;
 393         int rc;
 394         u64 tce_size, num_tce, dma_offset, next;
 395         u32 tce_shift;
 396         long limit;
 397
 398         tce_shift = be32_to_cpu(maprange->tce_shift);
 399         tce_size = 1ULL << tce_shift;
 400         next = start_pfn << PAGE_SHIFT;
 401         num_tce = num_pfn << PAGE_SHIFT;
 402
 403         /* round back to the beginning of the tce page size */
 404         num_tce += next & (tce_size - 1);
 405         next &= ~(tce_size - 1);
 406
 407         /* covert to number of tces */
 408         num_tce |= tce_size - 1;
 409         num_tce >>= tce_shift;
 410
 411         do {
 412                 /*
 413                  * Set up the page with TCE data, looping through and setting
 414                  * the values.
 415                  */
 416                 limit = min_t(long, num_tce, 512);
 417                 dma_offset = next + be64_to_cpu(maprange->dma_base);
 418
 419                 rc = plpar_tce_stuff((u64)be32_to_cpu(maprange->liobn),
 420                                              dma_offset,
 421                                              0, limit);
 422                 next += limit * tce_size;
 423                 num_tce -= limit;
 424         } while (num_tce > 0 && !rc);
 425
 426         return rc;
 427 }
 428
 429 static int tce_setrange_multi_pSeriesLP(unsigned long start_pfn,
 430                                         unsigned long num_pfn, const void *arg)
 431 {
 432         const struct dynamic_dma_window_prop *maprange = arg;
 433         u64 tce_size, num_tce, dma_offset, next, proto_tce, liobn;
 434         __be64 *tcep;
 435         u32 tce_shift;
 436         u64 rc = 0;
 437         long l, limit;
 438
 439         local_irq_disable();    /* to protect tcep and the page behind it */
 440         tcep = __this_cpu_read(tce_page);
 441
 442         if (!tcep) {
 443                 tcep = (__be64 *)__get_free_page(GFP_ATOMIC);
 444                 if (!tcep) {
 445                         local_irq_enable();
 446                         return -ENOMEM;
 447                 }
 448                 __this_cpu_write(tce_page, tcep);
 449         }
 450
 451         proto_tce = TCE_PCI_READ | TCE_PCI_WRITE;
 452
 453         liobn = (u64)be32_to_cpu(maprange->liobn);
 454         tce_shift = be32_to_cpu(maprange->tce_shift);
 455         tce_size = 1ULL << tce_shift;
 456         next = start_pfn << PAGE_SHIFT;
 457         num_tce = num_pfn << PAGE_SHIFT;
 458
 459         /* round back to the beginning of the tce page size */
 460         num_tce += next & (tce_size - 1);
 461         next &= ~(tce_size - 1);
 462
 463         /* covert to number of tces */
 464         num_tce |= tce_size - 1;
 465         num_tce >>= tce_shift;
 466
 467         /* We can map max one pageful of TCEs at a time */
 468         do {
 469                 /*
 470                  * Set up the page with TCE data, looping through and setting
 471                  * the values.
 472                  */
 473                 limit = min_t(long, num_tce, 4096/TCE_ENTRY_SIZE);
 474                 dma_offset = next + be64_to_cpu(maprange->dma_base);
 475
 476                 for (l = 0; l < limit; l++) {
 477                         tcep[l] = cpu_to_be64(proto_tce | next);
 478                         next += tce_size;
 479                 }
 480
 481                 rc = plpar_tce_put_indirect(liobn,
 482                                             dma_offset,
 483                                             (u64)__pa(tcep),
 484                                             limit);
 485
 486                 num_tce -= limit;
 487         } while (num_tce > 0 && !rc);
 488
 489         /* error cleanup: caller will clear whole range */
 490
 491         local_irq_enable();
 492         return rc;
 493 }
 494
 495 static int tce_setrange_multi_pSeriesLP_walk(unsigned long start_pfn,
 496                 unsigned long num_pfn, void *arg)
 497 {
 498         return tce_setrange_multi_pSeriesLP(start_pfn, num_pfn, arg);
 499 }
 500
 501 static void iommu_table_setparms(struct pci_controller *phb,
 502                                  struct device_node *dn,
 503                                  struct iommu_table *tbl)
 504 {
 505         struct device_node *node;
 506         const unsigned long *basep;
 507         const u32 *sizep;
 508
 509         node = phb->dn;
 510
 511         basep = of_get_property(node, "linux,tce-base", NULL);
 512         sizep = of_get_property(node, "linux,tce-size", NULL);
 513         if (basep == NULL || sizep == NULL) {
 514                 printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has "
 515                                 "missing tce entries !\n", dn->full_name);
 516                 return;
 517         }
 518
 519         tbl->it_base = (unsigned long)__va(*basep);
 520
 521         if (!is_kdump_kernel())
 522                 memset((void *)tbl->it_base, 0, *sizep);
 523
 524         tbl->it_busno = phb->bus->number;
 525         tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K;
 526
 527         /* Units of tce entries */
 528         tbl->it_offset = phb->dma_window_base_cur >> tbl->it_page_shift;
 529
 530         /* Test if we are going over 2GB of DMA space */
 531         if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) {
 532                 udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
 533                 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
 534         }
 535
 536         phb->dma_window_base_cur += phb->dma_window_size;
 537
 538         /* Set the tce table size - measured in entries */
 539         tbl->it_size = phb->dma_window_size >> tbl->it_page_shift;
 540
 541         tbl->it_index = 0;
 542         tbl->it_blocksize = 16;
 543         tbl->it_type = TCE_PCI;
 544 }
 545
 546 /*
 547  * iommu_table_setparms_lpar
 548  *
 549  * Function: On pSeries LPAR systems, return TCE table info, given a pci bus.
 550  */
 551 static void iommu_table_setparms_lpar(struct pci_controller *phb,
 552                                       struct device_node *dn,
 553                                       struct iommu_table *tbl,
 554                                       const __be32 *dma_window)
 555 {
 556         unsigned long offset, size;
 557
 558         of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size);
 559
 560         tbl->it_busno = phb->bus->number;
 561         tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K;
 562         tbl->it_base   = 0;
 563         tbl->it_blocksize  = 16;
 564         tbl->it_type = TCE_PCI;
 565         tbl->it_offset = offset >> tbl->it_page_shift;
 566         tbl->it_size = size >> tbl->it_page_shift;
 567 }
 568
 569 struct iommu_table_ops iommu_table_pseries_ops = {
 570         .set = tce_build_pSeries,
 571         .clear = tce_free_pSeries,
 572         .get = tce_get_pseries
 573 };
 574
 575 static void pci_dma_bus_setup_pSeries(struct pci_bus *bus)
 576 {
 577         struct device_node *dn;
 578         struct iommu_table *tbl;
 579         struct device_node *isa_dn, *isa_dn_orig;
 580         struct device_node *tmp;
 581         struct pci_dn *pci;
 582         int children;
 583
 584         dn = pci_bus_to_OF_node(bus);
 585
 586         pr_debug("pci_dma_bus_setup_pSeries: setting up bus %s\n", dn->full_name);
 587
 588         if (bus->self) {
 589                 /* This is not a root bus, any setup will be done for the
 590                  * device-side of the bridge in iommu_dev_setup_pSeries().
 591                  */
 592                 return;
 593         }
 594         pci = PCI_DN(dn);
 595
 596         /* Check if the ISA bus on the system is under
 597          * this PHB.
 598          */
 599         isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa");
 600
 601         while (isa_dn && isa_dn != dn)
 602                 isa_dn = isa_dn->parent;
 603
 604         of_node_put(isa_dn_orig);
 605
 606         /* Count number of direct PCI children of the PHB. */
 607         for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling)
 608                 children++;
 609
 610         pr_debug("Children: %d\n", children);
 611
 612         /* Calculate amount of DMA window per slot. Each window must be
 613          * a power of two (due to pci_alloc_consistent requirements).
 614          *
 615          * Keep 256MB aside for PHBs with ISA.
 616          */
 617
 618         if (!isa_dn) {
 619                 /* No ISA/IDE - just set window size and return */
 620                 pci->phb->dma_window_size = 0x80000000ul; /* To be divided */
 621
 622                 while (pci->phb->dma_window_size * children > 0x80000000ul)
 623                         pci->phb->dma_window_size >>= 1;
 624                 pr_debug("No ISA/IDE, window size is 0x%llx\n",
 625                          pci->phb->dma_window_size);
 626                 pci->phb->dma_window_base_cur = 0;
 627
 628                 return;
 629         }
 630
 631         /* If we have ISA, then we probably have an IDE
 632          * controller too. Allocate a 128MB table but
 633          * skip the first 128MB to avoid stepping on ISA
 634          * space.
 635          */
 636         pci->phb->dma_window_size = 0x8000000ul;
 637         pci->phb->dma_window_base_cur = 0x8000000ul;
 638
 639         pci->table_group = iommu_pseries_alloc_group(pci->phb->node);
 640         tbl = pci->table_group->tables[0];
 641
 642         iommu_table_setparms(pci->phb, dn, tbl);
 643         tbl->it_ops = &iommu_table_pseries_ops;
 644         iommu_init_table(tbl, pci->phb->node);
 645         iommu_register_group(pci->table_group, pci_domain_nr(bus), 0);
 646
 647         /* Divide the rest (1.75GB) among the children */
 648         pci->phb->dma_window_size = 0x80000000ul;
 649         while (pci->phb->dma_window_size * children > 0x70000000ul)
 650                 pci->phb->dma_window_size >>= 1;
 651
 652         pr_debug("ISA/IDE, window size is 0x%llx\n", pci->phb->dma_window_size);
 653 }
 654
 655 struct iommu_table_ops iommu_table_lpar_multi_ops = {
 656         .set = tce_buildmulti_pSeriesLP,
 657         .clear = tce_freemulti_pSeriesLP,
 658         .get = tce_get_pSeriesLP
 659 };
 660
 661 static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus)
 662 {
 663         struct iommu_table *tbl;
 664         struct device_node *dn, *pdn;
 665         struct pci_dn *ppci;
 666         const __be32 *dma_window = NULL;
 667
 668         dn = pci_bus_to_OF_node(bus);
 669
 670         pr_debug("pci_dma_bus_setup_pSeriesLP: setting up bus %s\n",
 671                  dn->full_name);
 672
 673         /* Find nearest ibm,dma-window, walking up the device tree */
 674         for (pdn = dn; pdn != NULL; pdn = pdn->parent) {
 675                 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
 676                 if (dma_window != NULL)
 677                         break;
 678         }
 679
 680         if (dma_window == NULL) {
 681                 pr_debug("  no ibm,dma-window property !\n");
 682                 return;
 683         }
 684
 685         ppci = PCI_DN(pdn);
 686
 687         pr_debug("  parent is %s, iommu_table: 0x%p\n",
 688                  pdn->full_name, ppci->table_group);
 689
 690         if (!ppci->table_group) {
 691                 ppci->table_group = iommu_pseries_alloc_group(ppci->phb->node);
 692                 tbl = ppci->table_group->tables[0];
 693                 iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window);
 694                 tbl->it_ops = &iommu_table_lpar_multi_ops;
 695                 iommu_init_table(tbl, ppci->phb->node);
 696                 iommu_register_group(ppci->table_group,
 697                                 pci_domain_nr(bus), 0);
 698                 pr_debug("  created table: %p\n", ppci->table_group);
 699         }
 700 }
 701
 702
 703 static void pci_dma_dev_setup_pSeries(struct pci_dev *dev)
 704 {
 705         struct device_node *dn;
 706         struct iommu_table *tbl;
 707
 708         pr_debug("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev));
 709
 710         dn = dev->dev.of_node;
 711
 712         /* If we're the direct child of a root bus, then we need to allocate
 713          * an iommu table ourselves. The bus setup code should have setup
 714          * the window sizes already.
 715          */
 716         if (!dev->bus->self) {
 717                 struct pci_controller *phb = PCI_DN(dn)->phb;
 718
 719                 pr_debug(" --> first child, no bridge. Allocating iommu table.\n");
 720                 PCI_DN(dn)->table_group = iommu_pseries_alloc_group(phb->node);
 721                 tbl = PCI_DN(dn)->table_group->tables[0];
 722                 iommu_table_setparms(phb, dn, tbl);
 723                 tbl->it_ops = &iommu_table_pseries_ops;
 724                 iommu_init_table(tbl, phb->node);
 725                 iommu_register_group(PCI_DN(dn)->table_group,
 726                                 pci_domain_nr(phb->bus), 0);
 727                 set_iommu_table_base(&dev->dev, tbl);
 728                 iommu_add_device(&dev->dev);
 729                 return;
 730         }
 731
 732         /* If this device is further down the bus tree, search upwards until
 733          * an already allocated iommu table is found and use that.
 734          */
 735
 736         while (dn && PCI_DN(dn) && PCI_DN(dn)->table_group == NULL)
 737                 dn = dn->parent;
 738
 739         if (dn && PCI_DN(dn)) {
 740                 set_iommu_table_base(&dev->dev,
 741                                 PCI_DN(dn)->table_group->tables[0]);
 742                 iommu_add_device(&dev->dev);
 743         } else
 744                 printk(KERN_WARNING "iommu: Device %s has no iommu table\n",
 745                        pci_name(dev));
 746 }
 747
 748 static int __read_mostly disable_ddw;
 749
 750 static int __init disable_ddw_setup(char *str)
 751 {
 752         disable_ddw = 1;
 753         printk(KERN_INFO "ppc iommu: disabling ddw.\n");
 754
 755         return 0;
 756 }
 757
 758 early_param("disable_ddw", disable_ddw_setup);
 759
 760 static void remove_ddw(struct device_node *np, bool remove_prop)
 761 {
 762         struct dynamic_dma_window_prop *dwp;
 763         struct property *win64;
 764         u32 ddw_avail[3];
 765         u64 liobn;
 766         int ret = 0;
 767
 768         ret = of_property_read_u32_array(np, "ibm,ddw-applicable",
 769                                          &ddw_avail[0], 3);
 770
 771         win64 = of_find_property(np, DIRECT64_PROPNAME, NULL);
 772         if (!win64)
 773                 return;
 774
 775         if (ret || win64->length < sizeof(*dwp))
 776                 goto delprop;
 777
 778         dwp = win64->value;
 779         liobn = (u64)be32_to_cpu(dwp->liobn);
 780
 781         /* clear the whole window, note the arg is in kernel pages */
 782         ret = tce_clearrange_multi_pSeriesLP(0,
 783                 1ULL << (be32_to_cpu(dwp->window_shift) - PAGE_SHIFT), dwp);
 784         if (ret)
 785                 pr_warning("%s failed to clear tces in window.\n",
 786                          np->full_name);
 787         else
 788                 pr_debug("%s successfully cleared tces in window.\n",
 789                          np->full_name);
 790
 791         ret = rtas_call(ddw_avail[2], 1, 1, NULL, liobn);
 792         if (ret)
 793                 pr_warning("%s: failed to remove direct window: rtas returned "
 794                         "%d to ibm,remove-pe-dma-window(%x) %llx\n",
 795                         np->full_name, ret, ddw_avail[2], liobn);
 796         else
 797                 pr_debug("%s: successfully removed direct window: rtas returned "
 798                         "%d to ibm,remove-pe-dma-window(%x) %llx\n",
 799                         np->full_name, ret, ddw_avail[2], liobn);
 800
 801 delprop:
 802         if (remove_prop)
 803                 ret = of_remove_property(np, win64);
 804         if (ret)
 805                 pr_warning("%s: failed to remove direct window property: %d\n",
 806                         np->full_name, ret);
 807 }
 808
 809 static u64 find_existing_ddw(struct device_node *pdn)
 810 {
 811         struct direct_window *window;
 812         const struct dynamic_dma_window_prop *direct64;
 813         u64 dma_addr = 0;
 814
 815         spin_lock(&direct_window_list_lock);
 816         /* check if we already created a window and dupe that config if so */
 817         list_for_each_entry(window, &direct_window_list, list) {
 818                 if (window->device == pdn) {
 819                         direct64 = window->prop;
 820                         dma_addr = be64_to_cpu(direct64->dma_base);
 821                         break;
 822                 }
 823         }
 824         spin_unlock(&direct_window_list_lock);
 825
 826         return dma_addr;
 827 }
 828
 829 static int find_existing_ddw_windows(void)
 830 {
 831         int len;
 832         struct device_node *pdn;
 833         struct direct_window *window;
 834         const struct dynamic_dma_window_prop *direct64;
 835
 836         if (!firmware_has_feature(FW_FEATURE_LPAR))
 837                 return 0;
 838
 839         for_each_node_with_property(pdn, DIRECT64_PROPNAME) {
 840                 direct64 = of_get_property(pdn, DIRECT64_PROPNAME, &len);
 841                 if (!direct64)
 842                         continue;
 843
 844                 window = kzalloc(sizeof(*window), GFP_KERNEL);
 845                 if (!window || len < sizeof(struct dynamic_dma_window_prop)) {
 846                         kfree(window);
 847                         remove_ddw(pdn, true);
 848                         continue;
 849                 }
 850
 851                 window->device = pdn;
 852                 window->prop = direct64;
 853                 spin_lock(&direct_window_list_lock);
 854                 list_add(&window->list, &direct_window_list);
 855                 spin_unlock(&direct_window_list_lock);
 856         }
 857
 858         return 0;
 859 }
 860 machine_arch_initcall(pseries, find_existing_ddw_windows);
 861
 862 static int query_ddw(struct pci_dev *dev, const u32 *ddw_avail,
 863                         struct ddw_query_response *query)
 864 {
 865         struct device_node *dn;
 866         struct pci_dn *pdn;
 867         u32 cfg_addr;
 868         u64 buid;
 869         int ret;
 870
 871         /*
 872          * Get the config address and phb buid of the PE window.
 873          * Rely on eeh to retrieve this for us.
 874          * Retrieve them from the pci device, not the node with the
 875          * dma-window property
 876          */
 877         dn = pci_device_to_OF_node(dev);
 878         pdn = PCI_DN(dn);
 879         buid = pdn->phb->buid;
 880         cfg_addr = ((pdn->busno << 16) | (pdn->devfn << 8));
 881
 882         ret = rtas_call(ddw_avail[0], 3, 5, (u32 *)query,
 883                   cfg_addr, BUID_HI(buid), BUID_LO(buid));
 884         dev_info(&dev->dev, "ibm,query-pe-dma-windows(%x) %x %x %x"
 885                 " returned %d\n", ddw_avail[0], cfg_addr, BUID_HI(buid),
 886                 BUID_LO(buid), ret);
 887         return ret;
 888 }
 889
 890 static int create_ddw(struct pci_dev *dev, const u32 *ddw_avail,
 891                         struct ddw_create_response *create, int page_shift,
 892                         int window_shift)
 893 {
 894         struct device_node *dn;
 895         struct pci_dn *pdn;
 896         u32 cfg_addr;
 897         u64 buid;
 898         int ret;
 899
 900         /*
 901          * Get the config address and phb buid of the PE window.
 902          * Rely on eeh to retrieve this for us.
 903          * Retrieve them from the pci device, not the node with the
 904          * dma-window property
 905          */
 906         dn = pci_device_to_OF_node(dev);
 907         pdn = PCI_DN(dn);
 908         buid = pdn->phb->buid;
 909         cfg_addr = ((pdn->busno << 16) | (pdn->devfn << 8));
 910
 911         do {
 912                 /* extra outputs are LIOBN and dma-addr (hi, lo) */
 913                 ret = rtas_call(ddw_avail[1], 5, 4, (u32 *)create,
 914                                 cfg_addr, BUID_HI(buid), BUID_LO(buid),
 915                                 page_shift, window_shift);
 916         } while (rtas_busy_delay(ret));
 917         dev_info(&dev->dev,
 918                 "ibm,create-pe-dma-window(%x) %x %x %x %x %x returned %d "
 919                 "(liobn = 0x%x starting addr = %x %x)\n", ddw_avail[1],
 920                  cfg_addr, BUID_HI(buid), BUID_LO(buid), page_shift,
 921                  window_shift, ret, create->liobn, create->addr_hi, create->addr_lo);
 922
 923         return ret;
 924 }
 925
 926 struct failed_ddw_pdn {
 927         struct device_node *pdn;
 928         struct list_head list;
 929 };
 930
 931 static LIST_HEAD(failed_ddw_pdn_list);
 932
 933 /*
 934  * If the PE supports dynamic dma windows, and there is space for a table
 935  * that can map all pages in a linear offset, then setup such a table,
 936  * and record the dma-offset in the struct device.
 937  *
 938  * dev: the pci device we are checking
 939  * pdn: the parent pe node with the ibm,dma_window property
 940  * Future: also check if we can remap the base window for our base page size
 941  *
 942  * returns the dma offset for use by dma_set_mask
 943  */
 944 static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
 945 {
 946         int len, ret;
 947         struct ddw_query_response query;
 948         struct ddw_create_response create;
 949         int page_shift;
 950         u64 dma_addr, max_addr;
 951         struct device_node *dn;
 952         u32 ddw_avail[3];
 953         struct direct_window *window;
 954         struct property *win64;
 955         struct dynamic_dma_window_prop *ddwprop;
 956         struct failed_ddw_pdn *fpdn;
 957
 958         mutex_lock(&direct_window_init_mutex);
 959
 960         dma_addr = find_existing_ddw(pdn);
 961         if (dma_addr != 0)
 962                 goto out_unlock;
 963
 964         /*
 965          * If we already went through this for a previous function of
 966          * the same device and failed, we don't want to muck with the
 967          * DMA window again, as it will race with in-flight operations
 968          * and can lead to EEHs. The above mutex protects access to the
 969          * list.
 970          */
 971         list_for_each_entry(fpdn, &failed_ddw_pdn_list, list) {
 972                 if (!strcmp(fpdn->pdn->full_name, pdn->full_name))
 973                         goto out_unlock;
 974         }
 975
 976         /*
 977          * the ibm,ddw-applicable property holds the tokens for:
 978          * ibm,query-pe-dma-window
 979          * ibm,create-pe-dma-window
 980          * ibm,remove-pe-dma-window
 981          * for the given node in that order.
 982          * the property is actually in the parent, not the PE
 983          */
 984         ret = of_property_read_u32_array(pdn, "ibm,ddw-applicable",
 985                                          &ddw_avail[0], 3);
 986         if (ret)
 987                 goto out_failed;
 988
 989        /*
 990          * Query if there is a second window of size to map the
 991          * whole partition.  Query returns number of windows, largest
 992          * block assigned to PE (partition endpoint), and two bitmasks
 993          * of page sizes: supported and supported for migrate-dma.
 994          */
 995         dn = pci_device_to_OF_node(dev);
 996         ret = query_ddw(dev, ddw_avail, &query);
 997         if (ret != 0)
 998                 goto out_failed;
 999
1000         if (query.windows_available == 0) {
1001                 /*
1002                  * no additional windows are available for this device.
1003                  * We might be able to reallocate the existing window,
1004                  * trading in for a larger page size.
1005                  */
1006                 dev_dbg(&dev->dev, "no free dynamic windows");
1007                 goto out_failed;
1008         }
1009         if (query.page_size & 4) {
1010                 page_shift = 24; /* 16MB */
1011         } else if (query.page_size & 2) {
1012                 page_shift = 16; /* 64kB */
1013         } else if (query.page_size & 1) {
1014                 page_shift = 12; /* 4kB */
1015         } else {
1016                 dev_dbg(&dev->dev, "no supported direct page size in mask %x",
1017                           query.page_size);
1018                 goto out_failed;
1019         }
1020         /* verify the window * number of ptes will map the partition */
1021         /* check largest block * page size > max memory hotplug addr */
1022         max_addr = memory_hotplug_max();
1023         if (query.largest_available_block < (max_addr >> page_shift)) {
1024                 dev_dbg(&dev->dev, "can't map partition max 0x%llx with %u "
1025                           "%llu-sized pages\n", max_addr,  query.largest_available_block,
1026                           1ULL << page_shift);
1027                 goto out_failed;
1028         }
1029         len = order_base_2(max_addr);
1030         win64 = kzalloc(sizeof(struct property), GFP_KERNEL);
1031         if (!win64) {
1032                 dev_info(&dev->dev,
1033                         "couldn't allocate property for 64bit dma window\n");
1034                 goto out_failed;
1035         }
1036         win64->name = kstrdup(DIRECT64_PROPNAME, GFP_KERNEL);
1037         win64->value = ddwprop = kmalloc(sizeof(*ddwprop), GFP_KERNEL);
1038         win64->length = sizeof(*ddwprop);
1039         if (!win64->name || !win64->value) {
1040                 dev_info(&dev->dev,
1041                         "couldn't allocate property name and value\n");
1042                 goto out_free_prop;
1043         }
1044
1045         ret = create_ddw(dev, ddw_avail, &create, page_shift, len);
1046         if (ret != 0)
1047                 goto out_free_prop;
1048
1049         ddwprop->liobn = cpu_to_be32(create.liobn);
1050         ddwprop->dma_base = cpu_to_be64(((u64)create.addr_hi << 32) |
1051                         create.addr_lo);
1052         ddwprop->tce_shift = cpu_to_be32(page_shift);
1053         ddwprop->window_shift = cpu_to_be32(len);
1054
1055         dev_dbg(&dev->dev, "created tce table LIOBN 0x%x for %s\n",
1056                   create.liobn, dn->full_name);
1057
1058         window = kzalloc(sizeof(*window), GFP_KERNEL);
1059         if (!window)
1060                 goto out_clear_window;
1061
1062         ret = walk_system_ram_range(0, memblock_end_of_DRAM() >> PAGE_SHIFT,
1063                         win64->value, tce_setrange_multi_pSeriesLP_walk);
1064         if (ret) {
1065                 dev_info(&dev->dev, "failed to map direct window for %s: %d\n",
1066                          dn->full_name, ret);
1067                 goto out_free_window;
1068         }
1069
1070         ret = of_add_property(pdn, win64);
1071         if (ret) {
1072                 dev_err(&dev->dev, "unable to add dma window property for %s: %d",
1073                          pdn->full_name, ret);
1074                 goto out_free_window;
1075         }
1076
1077         window->device = pdn;
1078         window->prop = ddwprop;
1079         spin_lock(&direct_window_list_lock);
1080         list_add(&window->list, &direct_window_list);
1081         spin_unlock(&direct_window_list_lock);
1082
1083         dma_addr = be64_to_cpu(ddwprop->dma_base);
1084         goto out_unlock;
1085
1086 out_free_window:
1087         kfree(window);
1088
1089 out_clear_window:
1090         remove_ddw(pdn, true);
1091
1092 out_free_prop:
1093         kfree(win64->name);
1094         kfree(win64->value);
1095         kfree(win64);
1096
1097 out_failed:
1098
1099         fpdn = kzalloc(sizeof(*fpdn), GFP_KERNEL);
1100         if (!fpdn)
1101                 goto out_unlock;
1102         fpdn->pdn = pdn;
1103         list_add(&fpdn->list, &failed_ddw_pdn_list);
1104
1105 out_unlock:
1106         mutex_unlock(&direct_window_init_mutex);
1107         return dma_addr;
1108 }
1109
1110 static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev)
1111 {
1112         struct device_node *pdn, *dn;
1113         struct iommu_table *tbl;
1114         const __be32 *dma_window = NULL;
1115         struct pci_dn *pci;
1116
1117         pr_debug("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev));
1118
1119         /* dev setup for LPAR is a little tricky, since the device tree might
1120          * contain the dma-window properties per-device and not necessarily
1121          * for the bus. So we need to search upwards in the tree until we
1122          * either hit a dma-window property, OR find a parent with a table
1123          * already allocated.
1124          */
1125         dn = pci_device_to_OF_node(dev);
1126         pr_debug("  node is %s\n", dn->full_name);
1127
1128         for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->table_group;
1129              pdn = pdn->parent) {
1130                 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1131                 if (dma_window)
1132                         break;
1133         }
1134
1135         if (!pdn || !PCI_DN(pdn)) {
1136                 printk(KERN_WARNING "pci_dma_dev_setup_pSeriesLP: "
1137                        "no DMA window found for pci dev=%s dn=%s\n",
1138                                  pci_name(dev), of_node_full_name(dn));
1139                 return;
1140         }
1141         pr_debug("  parent is %s\n", pdn->full_name);
1142
1143         pci = PCI_DN(pdn);
1144         if (!pci->table_group) {
1145                 pci->table_group = iommu_pseries_alloc_group(pci->phb->node);
1146                 tbl = pci->table_group->tables[0];
1147                 iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window);
1148                 tbl->it_ops = &iommu_table_lpar_multi_ops;
1149                 iommu_init_table(tbl, pci->phb->node);
1150                 iommu_register_group(pci->table_group,
1151                                 pci_domain_nr(pci->phb->bus), 0);
1152                 pr_debug("  created table: %p\n", pci->table_group);
1153         } else {
1154                 pr_debug("  found DMA window, table: %p\n", pci->table_group);
1155         }
1156
1157         set_iommu_table_base(&dev->dev, pci->table_group->tables[0]);
1158         iommu_add_device(&dev->dev);
1159 }
1160
1161 static int dma_set_mask_pSeriesLP(struct device *dev, u64 dma_mask)
1162 {
1163         bool ddw_enabled = false;
1164         struct device_node *pdn, *dn;
1165         struct pci_dev *pdev;
1166         const __be32 *dma_window = NULL;
1167         u64 dma_offset;
1168
1169         if (!dev->dma_mask)
1170                 return -EIO;
1171
1172         if (!dev_is_pci(dev))
1173                 goto check_mask;
1174
1175         pdev = to_pci_dev(dev);
1176
1177         /* only attempt to use a new window if 64-bit DMA is requested */
1178         if (!disable_ddw && dma_mask == DMA_BIT_MASK(64)) {
1179                 dn = pci_device_to_OF_node(pdev);
1180                 dev_dbg(dev, "node is %s\n", dn->full_name);
1181
1182                 /*
1183                  * the device tree might contain the dma-window properties
1184                  * per-device and not necessarily for the bus. So we need to
1185                  * search upwards in the tree until we either hit a dma-window
1186                  * property, OR find a parent with a table already allocated.
1187                  */
1188                 for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->table_group;
1189                                 pdn = pdn->parent) {
1190                         dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1191                         if (dma_window)
1192                                 break;
1193                 }
1194                 if (pdn && PCI_DN(pdn)) {
1195                         dma_offset = enable_ddw(pdev, pdn);
1196                         if (dma_offset != 0) {
1197                                 dev_info(dev, "Using 64-bit direct DMA at offset %llx\n", dma_offset);
1198                                 set_dma_offset(dev, dma_offset);
1199                                 set_dma_ops(dev, &dma_direct_ops);
1200                                 ddw_enabled = true;
1201                         }
1202                 }
1203         }
1204
1205         /* fall back on iommu ops */
1206         if (!ddw_enabled && get_dma_ops(dev) != &dma_iommu_ops) {
1207                 dev_info(dev, "Restoring 32-bit DMA via iommu\n");
1208                 set_dma_ops(dev, &dma_iommu_ops);
1209         }
1210
1211 check_mask:
1212         if (!dma_supported(dev, dma_mask))
1213                 return -EIO;
1214
1215         *dev->dma_mask = dma_mask;
1216         return 0;
1217 }
1218
1219 static u64 dma_get_required_mask_pSeriesLP(struct device *dev)
1220 {
1221         if (!dev->dma_mask)
1222                 return 0;
1223
1224         if (!disable_ddw && dev_is_pci(dev)) {
1225                 struct pci_dev *pdev = to_pci_dev(dev);
1226                 struct device_node *dn;
1227
1228                 dn = pci_device_to_OF_node(pdev);
1229
1230                 /* search upwards for ibm,dma-window */
1231                 for (; dn && PCI_DN(dn) && !PCI_DN(dn)->table_group;
1232                                 dn = dn->parent)
1233                         if (of_get_property(dn, "ibm,dma-window", NULL))
1234                                 break;
1235                 /* if there is a ibm,ddw-applicable property require 64 bits */
1236                 if (dn && PCI_DN(dn) &&
1237                                 of_get_property(dn, "ibm,ddw-applicable", NULL))
1238                         return DMA_BIT_MASK(64);
1239         }
1240
1241         return dma_iommu_ops.get_required_mask(dev);
1242 }
1243
1244 static int iommu_mem_notifier(struct notifier_block *nb, unsigned long action,
1245                 void *data)
1246 {
1247         struct direct_window *window;
1248         struct memory_notify *arg = data;
1249         int ret = 0;
1250
1251         switch (action) {
1252         case MEM_GOING_ONLINE:
1253                 spin_lock(&direct_window_list_lock);
1254                 list_for_each_entry(window, &direct_window_list, list) {
1255                         ret |= tce_setrange_multi_pSeriesLP(arg->start_pfn,
1256                                         arg->nr_pages, window->prop);
1257                         /* XXX log error */
1258                 }
1259                 spin_unlock(&direct_window_list_lock);
1260                 break;
1261         case MEM_CANCEL_ONLINE:
1262         case MEM_OFFLINE:
1263                 spin_lock(&direct_window_list_lock);
1264                 list_for_each_entry(window, &direct_window_list, list) {
1265                         ret |= tce_clearrange_multi_pSeriesLP(arg->start_pfn,
1266                                         arg->nr_pages, window->prop);
1267                         /* XXX log error */
1268                 }
1269                 spin_unlock(&direct_window_list_lock);
1270                 break;
1271         default:
1272                 break;
1273         }
1274         if (ret && action != MEM_CANCEL_ONLINE)
1275                 return NOTIFY_BAD;
1276
1277         return NOTIFY_OK;
1278 }
1279
1280 static struct notifier_block iommu_mem_nb = {
1281         .notifier_call = iommu_mem_notifier,
1282 };
1283
1284 static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *data)
1285 {
1286         int err = NOTIFY_OK;
1287         struct of_reconfig_data *rd = data;
1288         struct device_node *np = rd->dn;
1289         struct pci_dn *pci = PCI_DN(np);
1290         struct direct_window *window;
1291
1292         switch (action) {
1293         case OF_RECONFIG_DETACH_NODE:
1294                 /*
1295                  * Removing the property will invoke the reconfig
1296                  * notifier again, which causes dead-lock on the
1297                  * read-write semaphore of the notifier chain. So
1298                  * we have to remove the property when releasing
1299                  * the device node.
1300                  */
1301                 remove_ddw(np, false);
1302                 if (pci && pci->table_group)
1303                         iommu_pseries_free_group(pci->table_group,
1304                                         np->full_name);
1305
1306                 spin_lock(&direct_window_list_lock);
1307                 list_for_each_entry(window, &direct_window_list, list) {
1308                         if (window->device == np) {
1309                                 list_del(&window->list);
1310                                 kfree(window);
1311                                 break;
1312                         }
1313                 }
1314                 spin_unlock(&direct_window_list_lock);
1315                 break;
1316         default:
1317                 err = NOTIFY_DONE;
1318                 break;
1319         }
1320         return err;
1321 }
1322
1323 static struct notifier_block iommu_reconfig_nb = {
1324         .notifier_call = iommu_reconfig_notifier,
1325 };
1326
1327 /* These are called very early. */
1328 void iommu_init_early_pSeries(void)
1329 {
1330         if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL))
1331                 return;
1332
1333         if (firmware_has_feature(FW_FEATURE_LPAR)) {
1334                 pseries_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pSeriesLP;
1335                 pseries_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pSeriesLP;
1336                 ppc_md.dma_set_mask = dma_set_mask_pSeriesLP;
1337                 ppc_md.dma_get_required_mask = dma_get_required_mask_pSeriesLP;
1338         } else {
1339                 pseries_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pSeries;
1340                 pseries_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pSeries;
1341         }
1342
1343
1344         of_reconfig_notifier_register(&iommu_reconfig_nb);
1345         register_memory_notifier(&iommu_mem_nb);
1346
1347         set_pci_dma_ops(&dma_iommu_ops);
1348 }
1349
1350 static int __init disable_multitce(char *str)
1351 {
1352         if (strcmp(str, "off") == 0 &&
1353             firmware_has_feature(FW_FEATURE_LPAR) &&
1354             firmware_has_feature(FW_FEATURE_MULTITCE)) {
1355                 printk(KERN_INFO "Disabling MULTITCE firmware feature\n");
1356                 powerpc_firmware_features &= ~FW_FEATURE_MULTITCE;
1357         }
1358         return 1;
1359 }
1360
1361 __setup("multitce=", disable_multitce);
1362
1363 machine_subsys_initcall_sync(pseries, tce_iommu_bus_notifier_init);