2 * arch/powerpc/platforms/pseries/xics.c
4 * Copyright 2000 IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #include <linux/types.h>
13 #include <linux/threads.h>
14 #include <linux/kernel.h>
15 #include <linux/irq.h>
16 #include <linux/smp.h>
17 #include <linux/interrupt.h>
18 #include <linux/init.h>
19 #include <linux/radix-tree.h>
20 #include <linux/cpu.h>
21 #include <linux/msi.h>
23 #include <linux/percpu.h>
25 #include <asm/firmware.h>
27 #include <asm/pgtable.h>
30 #include <asm/hvcall.h>
31 #include <asm/machdep.h>
34 #include "plpar_wrappers.h"
36 static struct irq_host *xics_host;
39 #define XICS_IRQ_SPURIOUS 0
41 /* Want a priority other than 0. Various HW issues require this. */
42 #define DEFAULT_PRIORITY 5
45 * Mark IPIs as higher priority so we can take them inside interrupts that
46 * arent marked IRQF_DISABLED
48 #define IPI_PRIORITY 4
50 /* The least favored priority */
51 #define LOWEST_PRIORITY 0xFF
53 /* The number of priorities defined above */
54 #define MAX_NUM_PRIORITIES 3
56 static unsigned int default_server = 0xFF;
57 static unsigned int default_distrib_server = 0;
58 static unsigned int interrupt_server_size = 8;
60 /* RTAS service tokens */
61 static int ibm_get_xive;
62 static int ibm_set_xive;
63 static int ibm_int_on;
64 static int ibm_int_off;
67 unsigned char stack[MAX_NUM_PRIORITIES];
71 static DEFINE_PER_CPU(struct xics_cppr, xics_cppr);
73 /* Direct hardware low level accessors */
75 /* The part of the interrupt presentation layer that we care about */
92 static struct xics_ipl __iomem *xics_per_cpu[NR_CPUS];
94 static inline unsigned int direct_xirr_info_get(void)
96 int cpu = smp_processor_id();
98 return in_be32(&xics_per_cpu[cpu]->xirr.word);
101 static inline void direct_xirr_info_set(unsigned int value)
103 int cpu = smp_processor_id();
105 out_be32(&xics_per_cpu[cpu]->xirr.word, value);
108 static inline void direct_cppr_info(u8 value)
110 int cpu = smp_processor_id();
112 out_8(&xics_per_cpu[cpu]->xirr.bytes[0], value);
115 static inline void direct_qirr_info(int n_cpu, u8 value)
117 out_8(&xics_per_cpu[n_cpu]->qirr.bytes[0], value);
121 /* LPAR low level accessors */
123 static inline unsigned int lpar_xirr_info_get(void)
125 unsigned long lpar_rc;
126 unsigned long return_value;
128 lpar_rc = plpar_xirr(&return_value);
129 if (lpar_rc != H_SUCCESS)
130 panic(" bad return code xirr - rc = %lx \n", lpar_rc);
131 return (unsigned int)return_value;
134 static inline void lpar_xirr_info_set(unsigned int value)
136 unsigned long lpar_rc;
138 lpar_rc = plpar_eoi(value);
139 if (lpar_rc != H_SUCCESS)
140 panic("bad return code EOI - rc = %ld, value=%x\n", lpar_rc,
144 static inline void lpar_cppr_info(u8 value)
146 unsigned long lpar_rc;
148 lpar_rc = plpar_cppr(value);
149 if (lpar_rc != H_SUCCESS)
150 panic("bad return code cppr - rc = %lx\n", lpar_rc);
153 static inline void lpar_qirr_info(int n_cpu , u8 value)
155 unsigned long lpar_rc;
157 lpar_rc = plpar_ipi(get_hard_smp_processor_id(n_cpu), value);
158 if (lpar_rc != H_SUCCESS)
159 panic("bad return code qirr - rc = %lx\n", lpar_rc);
163 /* Interface to generic irq subsystem */
166 static int get_irq_server(unsigned int virq, unsigned int strict_check)
169 /* For the moment only implement delivery to all cpus or one cpu */
171 cpumask_t tmp = CPU_MASK_NONE;
173 cpumask_copy(&cpumask, irq_to_desc(virq)->affinity);
174 if (!distribute_irqs)
175 return default_server;
177 if (!cpus_equal(cpumask, CPU_MASK_ALL)) {
178 cpus_and(tmp, cpu_online_map, cpumask);
180 server = first_cpu(tmp);
182 if (server < NR_CPUS)
183 return get_hard_smp_processor_id(server);
189 if (cpus_equal(cpu_online_map, cpu_present_map))
190 return default_distrib_server;
192 return default_server;
195 static int get_irq_server(unsigned int virq, unsigned int strict_check)
197 return default_server;
201 static void xics_unmask_irq(unsigned int virq)
207 pr_devel("xics: unmask virq %d\n", virq);
209 irq = (unsigned int)irq_map[virq].hwirq;
210 pr_devel(" -> map to hwirq 0x%x\n", irq);
211 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
214 server = get_irq_server(virq, 0);
216 call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server,
218 if (call_status != 0) {
220 "%s: ibm_set_xive irq %u server %x returned %d\n",
221 __func__, irq, server, call_status);
225 /* Now unmask the interrupt (often a no-op) */
226 call_status = rtas_call(ibm_int_on, 1, 1, NULL, irq);
227 if (call_status != 0) {
228 printk(KERN_ERR "%s: ibm_int_on irq=%u returned %d\n",
229 __func__, irq, call_status);
234 static unsigned int xics_startup(unsigned int virq)
237 * The generic MSI code returns with the interrupt disabled on the
238 * card, using the MSI mask bits. Firmware doesn't appear to unmask
239 * at that level, so we do it here by hand.
241 if (irq_to_desc(virq)->msi_desc)
242 unmask_msi_irq(virq);
245 xics_unmask_irq(virq);
249 static void xics_mask_real_irq(unsigned int irq)
256 call_status = rtas_call(ibm_int_off, 1, 1, NULL, irq);
257 if (call_status != 0) {
258 printk(KERN_ERR "%s: ibm_int_off irq=%u returned %d\n",
259 __func__, irq, call_status);
263 /* Have to set XIVE to 0xff to be able to remove a slot */
264 call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq,
265 default_server, 0xff);
266 if (call_status != 0) {
267 printk(KERN_ERR "%s: ibm_set_xive(0xff) irq=%u returned %d\n",
268 __func__, irq, call_status);
273 static void xics_mask_irq(unsigned int virq)
277 pr_devel("xics: mask virq %d\n", virq);
279 irq = (unsigned int)irq_map[virq].hwirq;
280 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
282 xics_mask_real_irq(irq);
285 static void xics_mask_unknown_vec(unsigned int vec)
287 printk(KERN_ERR "Interrupt %u (real) is invalid, disabling it.\n", vec);
288 xics_mask_real_irq(vec);
291 static inline unsigned int xics_xirr_vector(unsigned int xirr)
294 * The top byte is the old cppr, to be restored on EOI.
295 * The remaining 24 bits are the vector.
297 return xirr & 0x00ffffff;
300 static void push_cppr(unsigned int vec)
302 struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
304 if (WARN_ON(os_cppr->index >= MAX_NUM_PRIORITIES - 1))
308 os_cppr->stack[++os_cppr->index] = IPI_PRIORITY;
310 os_cppr->stack[++os_cppr->index] = DEFAULT_PRIORITY;
313 static unsigned int xics_get_irq_direct(void)
315 unsigned int xirr = direct_xirr_info_get();
316 unsigned int vec = xics_xirr_vector(xirr);
319 if (vec == XICS_IRQ_SPURIOUS)
322 irq = irq_radix_revmap_lookup(xics_host, vec);
323 if (likely(irq != NO_IRQ)) {
328 /* We don't have a linux mapping, so have rtas mask it. */
329 xics_mask_unknown_vec(vec);
331 /* We might learn about it later, so EOI it */
332 direct_xirr_info_set(xirr);
336 static unsigned int xics_get_irq_lpar(void)
338 unsigned int xirr = lpar_xirr_info_get();
339 unsigned int vec = xics_xirr_vector(xirr);
342 if (vec == XICS_IRQ_SPURIOUS)
345 irq = irq_radix_revmap_lookup(xics_host, vec);
346 if (likely(irq != NO_IRQ)) {
351 /* We don't have a linux mapping, so have RTAS mask it. */
352 xics_mask_unknown_vec(vec);
354 /* We might learn about it later, so EOI it */
355 lpar_xirr_info_set(xirr);
359 static unsigned char pop_cppr(void)
361 struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
363 if (WARN_ON(os_cppr->index < 1))
364 return LOWEST_PRIORITY;
366 return os_cppr->stack[--os_cppr->index];
369 static void xics_eoi_direct(unsigned int virq)
371 unsigned int irq = (unsigned int)irq_map[virq].hwirq;
374 direct_xirr_info_set((pop_cppr() << 24) | irq);
377 static void xics_eoi_lpar(unsigned int virq)
379 unsigned int irq = (unsigned int)irq_map[virq].hwirq;
382 lpar_xirr_info_set((pop_cppr() << 24) | irq);
385 static int xics_set_affinity(unsigned int virq, const struct cpumask *cpumask)
392 irq = (unsigned int)irq_map[virq].hwirq;
393 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
396 status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
399 printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n",
400 __func__, irq, status);
405 * For the moment only implement delivery to all cpus or one cpu.
406 * Get current irq_server for the given irq
408 irq_server = get_irq_server(virq, 1);
409 if (irq_server == -1) {
411 cpumask_scnprintf(cpulist, sizeof(cpulist), cpumask);
413 "%s: No online cpus in the mask %s for irq %d\n",
414 __func__, cpulist, virq);
418 status = rtas_call(ibm_set_xive, 3, 1, NULL,
419 irq, irq_server, xics_status[1]);
422 printk(KERN_ERR "%s: ibm,set-xive irq=%u returns %d\n",
423 __func__, irq, status);
430 static struct irq_chip xics_pic_direct = {
432 .startup = xics_startup,
433 .mask = xics_mask_irq,
434 .unmask = xics_unmask_irq,
435 .eoi = xics_eoi_direct,
436 .set_affinity = xics_set_affinity
439 static struct irq_chip xics_pic_lpar = {
441 .startup = xics_startup,
442 .mask = xics_mask_irq,
443 .unmask = xics_unmask_irq,
444 .eoi = xics_eoi_lpar,
445 .set_affinity = xics_set_affinity
449 /* Interface to arch irq controller subsystem layer */
451 /* Points to the irq_chip we're actually using */
452 static struct irq_chip *xics_irq_chip;
454 static int xics_host_match(struct irq_host *h, struct device_node *node)
456 /* IBM machines have interrupt parents of various funky types for things
457 * like vdevices, events, etc... The trick we use here is to match
458 * everything here except the legacy 8259 which is compatible "chrp,iic"
460 return !of_device_is_compatible(node, "chrp,iic");
463 static int xics_host_map(struct irq_host *h, unsigned int virq,
466 pr_devel("xics: map virq %d, hwirq 0x%lx\n", virq, hw);
468 /* Insert the interrupt mapping into the radix tree for fast lookup */
469 irq_radix_revmap_insert(xics_host, virq, hw);
471 irq_to_desc(virq)->status |= IRQ_LEVEL;
472 set_irq_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq);
476 static int xics_host_xlate(struct irq_host *h, struct device_node *ct,
477 const u32 *intspec, unsigned int intsize,
478 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
481 /* Current xics implementation translates everything
482 * to level. It is not technically right for MSIs but this
483 * is irrelevant at this point. We might get smarter in the future
485 *out_hwirq = intspec[0];
486 *out_flags = IRQ_TYPE_LEVEL_LOW;
491 static struct irq_host_ops xics_host_ops = {
492 .match = xics_host_match,
493 .map = xics_host_map,
494 .xlate = xics_host_xlate,
497 static void __init xics_init_host(void)
499 if (firmware_has_feature(FW_FEATURE_LPAR))
500 xics_irq_chip = &xics_pic_lpar;
502 xics_irq_chip = &xics_pic_direct;
504 xics_host = irq_alloc_host(NULL, IRQ_HOST_MAP_TREE, 0, &xics_host_ops,
506 BUG_ON(xics_host == NULL);
507 irq_set_default_host(xics_host);
511 /* Inter-processor interrupt support */
515 * XICS only has a single IPI, so encode the messages per CPU
517 struct xics_ipi_struct {
519 } ____cacheline_aligned;
521 static struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned;
523 static inline void smp_xics_do_message(int cpu, int msg)
525 set_bit(msg, &xics_ipi_message[cpu].value);
527 if (firmware_has_feature(FW_FEATURE_LPAR))
528 lpar_qirr_info(cpu, IPI_PRIORITY);
530 direct_qirr_info(cpu, IPI_PRIORITY);
533 void smp_xics_message_pass(int target, int msg)
537 if (target < NR_CPUS) {
538 smp_xics_do_message(target, msg);
540 for_each_online_cpu(i) {
541 if (target == MSG_ALL_BUT_SELF
542 && i == smp_processor_id())
544 smp_xics_do_message(i, msg);
549 static irqreturn_t xics_ipi_dispatch(int cpu)
551 WARN_ON(cpu_is_offline(cpu));
553 mb(); /* order mmio clearing qirr */
554 while (xics_ipi_message[cpu].value) {
555 if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION,
556 &xics_ipi_message[cpu].value)) {
557 smp_message_recv(PPC_MSG_CALL_FUNCTION);
559 if (test_and_clear_bit(PPC_MSG_RESCHEDULE,
560 &xics_ipi_message[cpu].value)) {
561 smp_message_recv(PPC_MSG_RESCHEDULE);
563 if (test_and_clear_bit(PPC_MSG_CALL_FUNC_SINGLE,
564 &xics_ipi_message[cpu].value)) {
565 smp_message_recv(PPC_MSG_CALL_FUNC_SINGLE);
567 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
568 if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK,
569 &xics_ipi_message[cpu].value)) {
570 smp_message_recv(PPC_MSG_DEBUGGER_BREAK);
577 static irqreturn_t xics_ipi_action_direct(int irq, void *dev_id)
579 int cpu = smp_processor_id();
581 direct_qirr_info(cpu, 0xff);
583 return xics_ipi_dispatch(cpu);
586 static irqreturn_t xics_ipi_action_lpar(int irq, void *dev_id)
588 int cpu = smp_processor_id();
590 lpar_qirr_info(cpu, 0xff);
592 return xics_ipi_dispatch(cpu);
595 static void xics_request_ipi(void)
600 ipi = irq_create_mapping(xics_host, XICS_IPI);
601 BUG_ON(ipi == NO_IRQ);
604 * IPIs are marked IRQF_DISABLED as they must run with irqs
607 set_irq_handler(ipi, handle_percpu_irq);
608 if (firmware_has_feature(FW_FEATURE_LPAR))
609 rc = request_irq(ipi, xics_ipi_action_lpar,
610 IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL);
612 rc = request_irq(ipi, xics_ipi_action_direct,
613 IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL);
617 int __init smp_xics_probe(void)
621 return cpus_weight(cpu_possible_map);
624 #endif /* CONFIG_SMP */
629 static void xics_update_irq_servers(void)
632 struct device_node *np;
637 /* Find the server numbers for the boot cpu. */
638 np = of_get_cpu_node(boot_cpuid, NULL);
641 ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
647 i = ilen / sizeof(int);
648 hcpuid = get_hard_smp_processor_id(boot_cpuid);
650 /* Global interrupt distribution server is specified in the last
651 * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
652 * entry fom this property for current boot cpu id and use it as
653 * default distribution server
655 for (j = 0; j < i; j += 2) {
656 if (ireg[j] == hcpuid) {
657 default_server = hcpuid;
658 default_distrib_server = ireg[j+1];
665 static void __init xics_map_one_cpu(int hw_id, unsigned long addr,
670 /* This may look gross but it's good enough for now, we don't quite
671 * have a hard -> linux processor id matching.
673 for_each_possible_cpu(i) {
676 if (hw_id == get_hard_smp_processor_id(i)) {
677 xics_per_cpu[i] = ioremap(addr, size);
683 static void __init xics_init_one_node(struct device_node *np,
689 /* This code does the theorically broken assumption that the interrupt
690 * server numbers are the same as the hard CPU numbers.
691 * This happens to be the case so far but we are playing with fire...
692 * should be fixed one of these days. -BenH.
694 ireg = of_get_property(np, "ibm,interrupt-server-ranges", NULL);
696 /* Do that ever happen ? we'll know soon enough... but even good'old
697 * f80 does have that property ..
699 WARN_ON(ireg == NULL);
702 * set node starting index for this node
706 ireg = of_get_property(np, "reg", &ilen);
708 panic("xics_init_IRQ: can't find interrupt reg property");
710 while (ilen >= (4 * sizeof(u32))) {
711 unsigned long addr, size;
713 /* XXX Use proper OF parsing code here !!! */
714 addr = (unsigned long)*ireg++ << 32;
718 size = (unsigned long)*ireg++ << 32;
722 xics_map_one_cpu(*indx, addr, size);
727 void __init xics_init_IRQ(void)
729 struct device_node *np;
734 ppc64_boot_msg(0x20, "XICS Init");
736 ibm_get_xive = rtas_token("ibm,get-xive");
737 ibm_set_xive = rtas_token("ibm,set-xive");
738 ibm_int_on = rtas_token("ibm,int-on");
739 ibm_int_off = rtas_token("ibm,int-off");
741 for_each_node_by_type(np, "PowerPC-External-Interrupt-Presentation") {
743 if (firmware_has_feature(FW_FEATURE_LPAR)) {
747 xics_init_one_node(np, &indx);
752 /* get the bit size of server numbers */
755 for_each_compatible_node(np, NULL, "ibm,ppc-xics") {
756 isize = of_get_property(np, "ibm,interrupt-server#-size", NULL);
762 interrupt_server_size = *isize;
764 } else if (*isize != interrupt_server_size) {
765 printk(KERN_WARNING "XICS: "
766 "mismatched ibm,interrupt-server#-size\n");
767 interrupt_server_size = max(*isize,
768 interrupt_server_size);
772 xics_update_irq_servers();
775 if (firmware_has_feature(FW_FEATURE_LPAR))
776 ppc_md.get_irq = xics_get_irq_lpar;
778 ppc_md.get_irq = xics_get_irq_direct;
782 ppc64_boot_msg(0x21, "XICS Done");
785 /* Cpu startup, shutdown, and hotplug */
787 static void xics_set_cpu_priority(unsigned char cppr)
789 struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
791 BUG_ON(os_cppr->index != 0);
793 os_cppr->stack[os_cppr->index] = cppr;
795 if (firmware_has_feature(FW_FEATURE_LPAR))
796 lpar_cppr_info(cppr);
798 direct_cppr_info(cppr);
802 /* Have the calling processor join or leave the specified global queue */
803 static void xics_set_cpu_giq(unsigned int gserver, unsigned int join)
808 if (!rtas_indicator_present(GLOBAL_INTERRUPT_QUEUE, NULL))
811 index = (1UL << interrupt_server_size) - 1 - gserver;
813 status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, index, join);
815 WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n",
816 GLOBAL_INTERRUPT_QUEUE, index, join, status);
819 void xics_setup_cpu(void)
821 xics_set_cpu_priority(LOWEST_PRIORITY);
823 xics_set_cpu_giq(default_distrib_server, 1);
826 void xics_teardown_cpu(void)
828 int cpu = smp_processor_id();
830 xics_set_cpu_priority(0);
832 /* Clear any pending IPI request */
833 if (firmware_has_feature(FW_FEATURE_LPAR))
834 lpar_qirr_info(cpu, 0xff);
836 direct_qirr_info(cpu, 0xff);
839 void xics_kexec_teardown_cpu(int secondary)
844 * we take the ipi irq but and never return so we
845 * need to EOI the IPI, but want to leave our priority 0
847 * should we check all the other interrupts too?
848 * should we be flagging idle loop instead?
849 * or creating some task to be scheduled?
852 if (firmware_has_feature(FW_FEATURE_LPAR))
853 lpar_xirr_info_set((0x00 << 24) | XICS_IPI);
855 direct_xirr_info_set((0x00 << 24) | XICS_IPI);
858 * Some machines need to have at least one cpu in the GIQ,
859 * so leave the master cpu in the group.
862 xics_set_cpu_giq(default_distrib_server, 0);
865 #ifdef CONFIG_HOTPLUG_CPU
867 /* Interrupts are disabled. */
868 void xics_migrate_irqs_away(void)
870 int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
871 unsigned int irq, virq;
873 /* If we used to be the default server, move to the new "boot_cpuid" */
874 if (hw_cpu == default_server)
875 xics_update_irq_servers();
877 /* Reject any interrupt that was queued to us... */
878 xics_set_cpu_priority(0);
880 /* Remove ourselves from the global interrupt queue */
881 xics_set_cpu_giq(default_distrib_server, 0);
883 /* Allow IPIs again... */
884 xics_set_cpu_priority(DEFAULT_PRIORITY);
887 struct irq_desc *desc;
892 /* We cant set affinity on ISA interrupts */
893 if (virq < NUM_ISA_INTERRUPTS)
895 if (irq_map[virq].host != xics_host)
897 irq = (unsigned int)irq_map[virq].hwirq;
898 /* We need to get IPIs still. */
899 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
901 desc = irq_to_desc(virq);
903 /* We only need to migrate enabled IRQS */
904 if (desc == NULL || desc->chip == NULL
905 || desc->action == NULL
906 || desc->chip->set_affinity == NULL)
909 spin_lock_irqsave(&desc->lock, flags);
911 status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
913 printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n",
914 __func__, irq, status);
919 * We only support delivery to all cpus or to one cpu.
920 * The irq has to be migrated only in the single cpu
923 if (xics_status[0] != hw_cpu)
926 printk(KERN_WARNING "IRQ %u affinity broken off cpu %u\n",
929 /* Reset affinity to all cpus */
930 cpumask_setall(irq_to_desc(virq)->affinity);
931 desc->chip->set_affinity(virq, cpu_all_mask);
933 spin_unlock_irqrestore(&desc->lock, flags);