2 * Freescale LBC and UPM routines.
4 * Copyright © 2007-2008 MontaVista Software, Inc.
5 * Copyright © 2010 Freescale Semiconductor
7 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
8 * Author: Jack Lan <Jack.Lan@freescale.com>
9 * Author: Roy Zang <tie-fei.zang@freescale.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/compiler.h>
21 #include <linux/spinlock.h>
22 #include <linux/types.h>
25 #include <linux/slab.h>
26 #include <linux/platform_device.h>
27 #include <linux/interrupt.h>
28 #include <linux/mod_devicetable.h>
30 #include <asm/fsl_lbc.h>
32 static spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
33 struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
34 EXPORT_SYMBOL(fsl_lbc_ctrl_dev);
37 * fsl_lbc_addr - convert the base address
38 * @addr_base: base address of the memory bank
40 * This function converts a base address of lbc into the right format for the
41 * BR register. If the SOC has eLBC then it returns 32bit physical address
42 * else it convers a 34bit local bus physical address to correct format of
43 * 32bit address for BR register (Example: MPC8641).
45 u32 fsl_lbc_addr(phys_addr_t addr_base)
47 struct device_node *np = fsl_lbc_ctrl_dev->dev->of_node;
48 u32 addr = addr_base & 0xffff8000;
50 if (of_device_is_compatible(np, "fsl,elbc"))
53 return addr | ((addr_base & 0x300000000ull) >> 19);
55 EXPORT_SYMBOL(fsl_lbc_addr);
58 * fsl_lbc_find - find Localbus bank
59 * @addr_base: base address of the memory bank
61 * This function walks LBC banks comparing "Base address" field of the BR
62 * registers with the supplied addr_base argument. When bases match this
63 * function returns bank number (starting with 0), otherwise it returns
64 * appropriate errno value.
66 int fsl_lbc_find(phys_addr_t addr_base)
69 struct fsl_lbc_regs __iomem *lbc;
71 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
74 lbc = fsl_lbc_ctrl_dev->regs;
75 for (i = 0; i < ARRAY_SIZE(lbc->bank); i++) {
76 __be32 br = in_be32(&lbc->bank[i].br);
77 __be32 or = in_be32(&lbc->bank[i].or);
79 if (br & BR_V && (br & or & BR_BA) == fsl_lbc_addr(addr_base))
85 EXPORT_SYMBOL(fsl_lbc_find);
88 * fsl_upm_find - find pre-programmed UPM via base address
89 * @addr_base: base address of the memory bank controlled by the UPM
90 * @upm: pointer to the allocated fsl_upm structure
92 * This function fills fsl_upm structure so you can use it with the rest of
93 * UPM API. On success this function returns 0, otherwise it returns
94 * appropriate errno value.
96 int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm)
100 struct fsl_lbc_regs __iomem *lbc;
102 bank = fsl_lbc_find(addr_base);
106 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
109 lbc = fsl_lbc_ctrl_dev->regs;
110 br = in_be32(&lbc->bank[bank].br);
112 switch (br & BR_MSEL) {
114 upm->mxmr = &lbc->mamr;
117 upm->mxmr = &lbc->mbmr;
120 upm->mxmr = &lbc->mcmr;
126 switch (br & BR_PS) {
142 EXPORT_SYMBOL(fsl_upm_find);
145 * fsl_upm_run_pattern - actually run an UPM pattern
146 * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
147 * @io_base: remapped pointer to where memory access should happen
148 * @mar: MAR register content during pattern execution
150 * This function triggers dummy write to the memory specified by the io_base,
151 * thus UPM pattern actually executed. Note that mar usage depends on the
152 * pre-programmed AMX bits in the UPM RAM.
154 int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar)
159 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
162 spin_lock_irqsave(&fsl_lbc_lock, flags);
164 out_be32(&fsl_lbc_ctrl_dev->regs->mar, mar);
166 switch (upm->width) {
171 out_be16(io_base, 0x0);
174 out_be32(io_base, 0x0);
181 spin_unlock_irqrestore(&fsl_lbc_lock, flags);
185 EXPORT_SYMBOL(fsl_upm_run_pattern);
187 static int __devinit fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl,
188 struct device_node *node)
190 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
192 /* clear event registers */
193 setbits32(&lbc->ltesr, LTESR_CLEAR);
194 out_be32(&lbc->lteatr, 0);
195 out_be32(&lbc->ltear, 0);
196 out_be32(&lbc->lteccr, LTECCR_CLEAR);
197 out_be32(&lbc->ltedr, LTEDR_ENABLE);
199 /* Set the monitor timeout value to the maximum for erratum A001 */
200 if (of_device_is_compatible(node, "fsl,elbc"))
201 clrsetbits_be32(&lbc->lbcr, LBCR_BMT, LBCR_BMTPS);
207 * NOTE: This interrupt is used to report localbus events of various kinds,
208 * such as transaction errors on the chipselects.
211 static irqreturn_t fsl_lbc_ctrl_irq(int irqno, void *data)
213 struct fsl_lbc_ctrl *ctrl = data;
214 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
217 status = in_be32(&lbc->ltesr);
221 out_be32(&lbc->ltesr, LTESR_CLEAR);
222 out_be32(&lbc->lteatr, 0);
223 out_be32(&lbc->ltear, 0);
224 ctrl->irq_status = status;
226 if (status & LTESR_BM)
227 dev_err(ctrl->dev, "Local bus monitor time-out: "
228 "LTESR 0x%08X\n", status);
229 if (status & LTESR_WP)
230 dev_err(ctrl->dev, "Write protect error: "
231 "LTESR 0x%08X\n", status);
232 if (status & LTESR_ATMW)
233 dev_err(ctrl->dev, "Atomic write error: "
234 "LTESR 0x%08X\n", status);
235 if (status & LTESR_ATMR)
236 dev_err(ctrl->dev, "Atomic read error: "
237 "LTESR 0x%08X\n", status);
238 if (status & LTESR_CS)
239 dev_err(ctrl->dev, "Chip select error: "
240 "LTESR 0x%08X\n", status);
241 if (status & LTESR_UPM)
243 if (status & LTESR_FCT) {
244 dev_err(ctrl->dev, "FCM command time-out: "
245 "LTESR 0x%08X\n", status);
247 wake_up(&ctrl->irq_wait);
249 if (status & LTESR_PAR) {
250 dev_err(ctrl->dev, "Parity or Uncorrectable ECC error: "
251 "LTESR 0x%08X\n", status);
253 wake_up(&ctrl->irq_wait);
255 if (status & LTESR_CC) {
257 wake_up(&ctrl->irq_wait);
259 if (status & ~LTESR_MASK)
260 dev_err(ctrl->dev, "Unknown error: "
261 "LTESR 0x%08X\n", status);
268 * called by device layer when it finds a device matching
269 * one our driver can handled. This code allocates all of
270 * the resources needed for the controller only. The
271 * resources for the NAND banks themselves are allocated
272 * in the chip probe function.
275 static int __devinit fsl_lbc_ctrl_probe(struct platform_device *dev)
279 if (!dev->dev.of_node) {
280 dev_err(&dev->dev, "Device OF-Node is NULL");
284 fsl_lbc_ctrl_dev = kzalloc(sizeof(*fsl_lbc_ctrl_dev), GFP_KERNEL);
285 if (!fsl_lbc_ctrl_dev)
288 dev_set_drvdata(&dev->dev, fsl_lbc_ctrl_dev);
290 spin_lock_init(&fsl_lbc_ctrl_dev->lock);
291 init_waitqueue_head(&fsl_lbc_ctrl_dev->irq_wait);
293 fsl_lbc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0);
294 if (!fsl_lbc_ctrl_dev->regs) {
295 dev_err(&dev->dev, "failed to get memory region\n");
300 fsl_lbc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
301 if (fsl_lbc_ctrl_dev->irq == NO_IRQ) {
302 dev_err(&dev->dev, "failed to get irq resource\n");
307 fsl_lbc_ctrl_dev->dev = &dev->dev;
309 ret = fsl_lbc_ctrl_init(fsl_lbc_ctrl_dev, dev->dev.of_node);
313 ret = request_irq(fsl_lbc_ctrl_dev->irq, fsl_lbc_ctrl_irq, 0,
314 "fsl-lbc", fsl_lbc_ctrl_dev);
316 dev_err(&dev->dev, "failed to install irq (%d)\n",
317 fsl_lbc_ctrl_dev->irq);
318 ret = fsl_lbc_ctrl_dev->irq;
322 /* Enable interrupts for any detected events */
323 out_be32(&fsl_lbc_ctrl_dev->regs->lteir, LTEIR_ENABLE);
328 iounmap(fsl_lbc_ctrl_dev->regs);
329 kfree(fsl_lbc_ctrl_dev);
333 static const struct of_device_id fsl_lbc_match[] = {
334 { .compatible = "fsl,elbc", },
335 { .compatible = "fsl,pq3-localbus", },
336 { .compatible = "fsl,pq2-localbus", },
337 { .compatible = "fsl,pq2pro-localbus", },
341 static struct platform_driver fsl_lbc_ctrl_driver = {
344 .of_match_table = fsl_lbc_match,
346 .probe = fsl_lbc_ctrl_probe,
349 static int __init fsl_lbc_init(void)
351 return platform_driver_register(&fsl_lbc_ctrl_driver);
353 module_init(fsl_lbc_init);